diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
index 0b8206a504340b81a151bfd29722347207d066fb..f206d62ef103dfd75769e32f7a2545aa363960c0 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
@@ -34,60 +34,72 @@ USE work.tech_mac_10g_component_pkg.ALL;
 USE work.tech_mac_10g_pkg.ALL;
 
 ENTITY tech_mac_10g_arria10 IS
-	PORT (
-		-- MM
-		mm_clk           : IN  STD_LOGIC;
-		mm_rst           : IN  STD_LOGIC;
-		csr_mosi         : IN  t_mem_mosi;  -- CSR = control status register
-		csr_miso         : OUT t_mem_miso;
+  PORT (
+    -- MM
+    mm_clk           : IN  STD_LOGIC;
+    mm_rst           : IN  STD_LOGIC;
+    csr_mosi         : IN  t_mem_mosi;  -- CSR = control status register
+    csr_miso         : OUT t_mem_miso;
 
     -- ST
-		tx_clk           : IN  STD_LOGIC;
-		tx_rst           : IN  STD_LOGIC;
-		tx_snk_in        : IN  t_dp_sosi; 
-		tx_snk_out       : OUT t_dp_siso; 
-		
-		rx_clk           : IN  STD_LOGIC;
-		rx_rst           : IN  STD_LOGIC;
-		rx_src_out       : OUT t_dp_sosi; 
-		rx_src_in        : IN  t_dp_siso; 
-		
+    tx_clk_2x        : IN  STD_LOGIC;
+    tx_clk           : IN  STD_LOGIC;
+    tx_rst           : IN  STD_LOGIC;
+    tx_snk_in        : IN  t_dp_sosi; 
+    tx_snk_out       : OUT t_dp_siso; 
+    
+    rx_clk_2x        : IN  STD_LOGIC;
+    rx_clk           : IN  STD_LOGIC;
+    rx_rst           : IN  STD_LOGIC;
+    rx_src_out       : OUT t_dp_sosi; 
+    rx_src_in        : IN  t_dp_siso; 
+    
     -- XGMII
-		xgmii_tx_data    : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0);  -- 72 bit
-		xgmii_rx_data    : IN  STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0)   -- 72 bit
-	);
+    xgmii_tx_data    : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0);  -- 72 bit
+    xgmii_rx_data    : IN  STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0)   -- 72 bit
+  );
 END tech_mac_10g_arria10;
 
 
 ARCHITECTURE str OF tech_mac_10g_arria10 IS  
  
-  CONSTANT c_mac_10g_csr_addr_w   : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10);  -- = 10
+  CONSTANT c_mac_10g_csr_addr_w   : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10);  -- = 13
   
   SIGNAL mm_rst_n     : STD_LOGIC;
   SIGNAL tx_rst_n     : STD_LOGIC;
   SIGNAL rx_rst_n     : STD_LOGIC;
   
+  SIGNAL avalon_rx_src_out : t_dp_sosi := c_dp_sosi_rst;
+  
 BEGIN
  
   mm_rst_n <= NOT mm_rst;
   tx_rst_n <= NOT tx_rst;
   rx_rst_n <= NOT rx_rst;
   
+  -- Default frame level flow control
   tx_snk_out.xon <= '1';
   
-  u_ip_mac_10g : ip_arria10_mac_10g
-	PORT MAP (
+  -- Force rx_src_out.sop = 0 when rx_src_out.valid = '0'
+  p_rx_src_out : PROCESS(avalon_rx_src_out)
+  BEGIN
+    rx_src_out     <= avalon_rx_src_out;
+    rx_src_out.sop <= avalon_rx_src_out.sop AND avalon_rx_src_out.valid;
+  END PROCESS;
+  
+  u_ip_mac_10g : ip_arria10_mac_10g_top
+  PORT MAP (
     csr_clk                         => mm_clk,
     csr_rst_n                       => mm_rst_n,
     
-    csr_address                     => csr_mosi.address(c_mac_10g_csr_addr_w-1 DOWNTO 0),     -- 10 bit
+    csr_address                     => csr_mosi.address(c_mac_10g_csr_addr_w-1 DOWNTO 0),     -- 13 bit
     csr_read                        => csr_mosi.rd,
     csr_write                       => csr_mosi.wr,
     csr_writedata                   => csr_mosi.wrdata(c_word_w-1 DOWNTO 0),                  -- 32 bit
     csr_readdata                    => csr_miso.rddata(c_word_w-1 DOWNTO 0),                  -- 32 bit
     csr_waitrequest                 => csr_miso.waitrequest,
     
-    tx_312_5_clk                    => '0',
+    tx_312_5_clk                    => tx_clk_2x,
     tx_156_25_clk                   => tx_clk,
     tx_rst_n                        => tx_rst_n,
     
@@ -106,19 +118,19 @@ BEGIN
     avalon_st_txstatus_data         => OPEN,
     avalon_st_txstatus_error        => OPEN,
     
-    rx_312_5_clk                    => '0',
+    rx_312_5_clk                    => rx_clk_2x,
     rx_156_25_clk                   => rx_clk,
     rx_rst_n                        => rx_rst_n,
     
     xgmii_rx                        => xgmii_rx_data,                                         -- 72 bit
     
     avalon_st_rx_ready              => rx_src_in.ready,
-    avalon_st_rx_startofpacket      => rx_src_out.sop,
-    avalon_st_rx_endofpacket        => rx_src_out.eop,
-    avalon_st_rx_valid              => rx_src_out.valid,
-    avalon_st_rx_data               => rx_src_out.data(c_xgmii_data_w-1 DOWNTO 0),            -- 64 bit
-    avalon_st_rx_empty              => rx_src_out.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0),   --  3 bit
-    avalon_st_rx_error              => rx_src_out.err(c_tech_mac_10g_rx_error_w-1 DOWNTO 0),  --  6 bit
+    avalon_st_rx_startofpacket      => avalon_rx_src_out.sop,
+    avalon_st_rx_endofpacket        => avalon_rx_src_out.eop,
+    avalon_st_rx_valid              => avalon_rx_src_out.valid,
+    avalon_st_rx_data               => avalon_rx_src_out.data(c_xgmii_data_w-1 DOWNTO 0),            -- 64 bit
+    avalon_st_rx_empty              => avalon_rx_src_out.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0),   --  3 bit
+    avalon_st_rx_error              => avalon_rx_src_out.err(c_tech_mac_10g_rx_error_w-1 DOWNTO 0),  --  6 bit
     
     avalon_st_rxstatus_valid        => OPEN,
     avalon_st_rxstatus_data         => OPEN,