From 6dd7c1c40654b843c6c8e419ace31a11f7abb85a Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 21 Jun 2021 17:45:02 +0200
Subject: [PATCH] renamed val to recover val and added comment
---
.../base/dp/src/vhdl/dp_sync_recover.vhd | 43 ++++++++++---------
.../base/dp/tb/vhdl/tb_dp_sync_recover.vhd | 2 +-
libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd | 15 ++-----
3 files changed, 28 insertions(+), 32 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
index 5c8b24ce8b..f4ff1b9746 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
@@ -20,18 +20,21 @@
-------------------------------------------------------------------------------
-- Author : R vd Walle
--- Purpose : Recover DP control signals (sync, valid, sop, eop, bsn) from input with only valid and sync.
--- Description: dp_sync_recover generates the control signals based on in_sosi.sync, in_sosi.bsn and val.
--- . A data counter is used to count the valids from the input "val" and compare to g_nof_data_per_block to generate sop/eop.
+-- Purpose : Recover DP control signals (sync, valid, sop, eop, bsn) from input of a processing component and the out valid of that component.
+-- Description: dp_sync_recover generates the control signals based on in_sosi.sync, in_sosi.bsn and recover_val.
+-- dp_sync_recover is used in combination with a processing component that doesn't keep the control signals. By connecting the input of the
+-- processing component to in_sosi and the valid of the output of the processing component to recover_val, dp_sync_recover will generate the
+-- missing control signals at out_sosi.
+-- . A data counter is used to count the valids from the input "recover_val" and compare to g_nof_data_per_block to generate sop/eop.
-- . A block counter is used generate the BSN
-- . The BSN at sync of in_sosi is captured to determine when to generate the sync at the output.
--- . IN val is used to indicate when to start outputting the control signals. val is also used for out_sosi.valid, these are connected as wires, so no latency.
+-- . IN recover_val is used to indicate when to start outputting the control signals. recover_val is also used for out_sosi.valid, these are connected as wires, so no latency.
-- . IN restart is used to restart the counters. On the restart pulse the in_sosi.bsn is used as the initial value for the bsn counter.
-- Remarks:
--- . The val input signal should be connected to the desired valid of the output. It determines when
+-- . The recover_val input signal should be connected to the valid of the output of the related processing component. It determines when
-- the first block will start after a (re)start.
--- . It is assumed that the restart pulse is synchornous with in_sosi.sop (if it would have a sop)
--- . IN val should have at least a latency of 1 compared to in_sosi.
+-- . It is assumed that the restart pulse is synchronous with in_sosi.sop (if it would have a sop)
+-- . IN recover_val should have at least a latency of 1 compared to in_sosi.
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
@@ -48,14 +51,14 @@ ENTITY dp_sync_recover IS
PORT (
-- Clocks and reset
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
- in_sosi : IN t_dp_sosi := c_dp_sosi_rst;
- val : IN STD_LOGIC; -- desired valid of the output
- restart : IN STD_LOGIC := '0'; -- pulse to restart bsn counter
- -- Streaming source
- out_sosi : OUT t_dp_sosi
+ in_sosi : IN t_dp_sosi := c_dp_sosi_rst;
+ recover_val : IN STD_LOGIC; -- valid of the out_sosi that needs to be recoverd.
+ restart : IN STD_LOGIC := '0'; -- pulse to restart bsn counter
+
+ out_sosi : OUT t_dp_sosi
);
END dp_sync_recover;
@@ -63,9 +66,9 @@ END dp_sync_recover;
ARCHITECTURE rtl OF dp_sync_recover IS
TYPE t_reg IS RECORD -- local registers
- bsn_at_sync : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
- bsn_before_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
- bsn_at_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
+ bsn_at_sync : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0); -- bsn to store at which to generate a sync pulse.
+ bsn_before_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0); -- bsn to store at which to restart te bsn counter.
+ bsn_at_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0); -- bsn to store inital bsn after (re)start.
restart : STD_LOGIC;
started : STD_LOGIC;
data_cnt : NATURAL RANGE 0 TO g_nof_data_per_block;
@@ -92,12 +95,12 @@ BEGIN
END IF;
END PROCESS;
- p_comb : PROCESS(r, in_sosi, val)
+ p_comb : PROCESS(r, in_sosi, recover_val)
VARIABLE v : t_reg;
BEGIN
v := r;
v.out_sosi := c_dp_sosi_rst;
- v.out_sosi.valid := val;
+ v.out_sosi.valid := recover_val;
v.out_sosi.bsn := r.out_sosi.bsn;
IF r.restart = '0' AND restart = '0' THEN -- keep track of last bsn before restart
@@ -108,7 +111,7 @@ BEGIN
v.bsn_at_sync := in_sosi.bsn;
END IF;
- IF val = '1' THEN
+ IF recover_val = '1' THEN
v.data_cnt := r.data_cnt + 1;
IF r.data_cnt = 0 THEN -- generate sop + bsn
v.out_sosi.sop := '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
index 3df2c6b6a0..7650451cd0 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
@@ -184,7 +184,7 @@ BEGIN
-- Streaming sink
in_sosi => ref_sosi,
- val => dly_ref_sosi_arr(g_dut_latency).valid,
+ recover_val => dly_ref_sosi_arr(g_dut_latency).valid,
restart => restart,
-- Streaming source
out_sosi => out_sosi
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index 32b4568068..5188d93bd2 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -448,9 +448,6 @@ architecture str of wpfb_unit_dev is
signal fft_out_im_arr_pipe : t_fft_slv_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
signal fft_out_val_arr : std_logic_vector(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
- signal fft_out_sosi : t_dp_sosi;
- signal fft_out_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0) := (others => c_dp_sosi_rst);
-
signal pfb_out_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0) := (others => c_dp_sosi_rst);
signal ctrl_pfb_out_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -624,10 +621,6 @@ begin
-- Capture input BSN at input sync and pass the captured input BSN it on to PFB output sync.
-- The FFT output valid defines PFB output sync, sop, eop.
- fft_out_sosi.sync <= r.in_sosi_arr(0).sync;
- fft_out_sosi.bsn <= r.in_sosi_arr(0).bsn;
- fft_out_sosi.valid <= fft_out_val_arr(0);
-
u_dp_sync_recover : ENTITY dp_lib.dp_sync_recover
GENERIC MAP(
g_nof_data_per_block => c_nof_valid_per_block
@@ -636,10 +629,10 @@ begin
dp_rst => dp_rst,
dp_clk => dp_clk,
- in_sosi => fft_out_sosi,
- val => fft_out_sosi.valid,
- restart => r.bsn_source_restart,
- out_sosi => ctrl_pfb_out_sosi
+ in_sosi => r.in_sosi_arr(0),
+ recover_val => fft_out_val_arr(0),
+ restart => r.bsn_source_restart,
+ out_sosi => ctrl_pfb_out_sosi
);
wire_pfb_out_sosi_arr : for I in 0 to g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 generate
--
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