From 6d479748c1b084242f19d2a1e625dd595e8ff565 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 18 Dec 2014 13:59:13 +0000
Subject: [PATCH] Moved ddr3/ VHDL files to ddr/.
---
.../{ddr3/tech_ddr3.vhd => ddr/tech_ddr.vhd} | 6 +++---
.../tech_ddr_component_pkg.vhd} | 8 ++++----
.../tech_ddr_stratixiv.vhd} | 14 ++++++++------
3 files changed, 15 insertions(+), 13 deletions(-)
rename libraries/technology/{ddr3/tech_ddr3.vhd => ddr/tech_ddr.vhd} (97%)
rename libraries/technology/{ddr3/tech_ddr3_component_pkg.vhd => ddr/tech_ddr_component_pkg.vhd} (97%)
rename libraries/technology/{ddr3/tech_ddr3_stratixiv.vhd => ddr/tech_ddr_stratixiv.vhd} (96%)
diff --git a/libraries/technology/ddr3/tech_ddr3.vhd b/libraries/technology/ddr/tech_ddr.vhd
similarity index 97%
rename from libraries/technology/ddr3/tech_ddr3.vhd
rename to libraries/technology/ddr/tech_ddr.vhd
index 09a3b5ab52..c9b3de81af 100644
--- a/libraries/technology/ddr3/tech_ddr3.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
-ENTITY tech_ddr3 IS
+ENTITY tech_ddr IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr
@@ -52,10 +52,10 @@ ENTITY tech_ddr3 IS
phy_io : INOUT t_tech_ddr_phy_io;
phy_ou : OUT t_tech_ddr_phy_ou
);
-END tech_ddr3;
+END tech_ddr;
-ARCHITECTURE str OF tech_ddr3 IS
+ARCHITECTURE str OF tech_ddr IS
BEGIN
diff --git a/libraries/technology/ddr3/tech_ddr3_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
similarity index 97%
rename from libraries/technology/ddr3/tech_ddr3_component_pkg.vhd
rename to libraries/technology/ddr/tech_ddr_component_pkg.vhd
index ed7ad267ee..ddbd7908de 100644
--- a/libraries/technology/ddr3/tech_ddr3_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -26,7 +26,7 @@ LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE technology_lib.technology_pkg.ALL;
-PACKAGE tech_ddr3_component_pkg IS
+PACKAGE tech_ddr_component_pkg IS
------------------------------------------------------------------------------
-- ip_stratixiv
@@ -135,9 +135,9 @@ PACKAGE tech_ddr3_component_pkg IS
);
END COMPONENT;
-END tech_ddr3_component_pkg;
+END tech_ddr_component_pkg;
-PACKAGE BODY tech_ddr3_component_pkg IS
+PACKAGE BODY tech_ddr_component_pkg IS
-END tech_ddr3_component_pkg;
+END tech_ddr_component_pkg;
diff --git a/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
similarity index 96%
rename from libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
rename to libraries/technology/ddr/tech_ddr_stratixiv.vhd
index 40220af65e..284727598e 100644
--- a/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
+++ b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
@@ -28,9 +28,9 @@ LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
-USE work.tech_ddr3_component_pkg.ALL;
+USE work.tech_ddr_component_pkg.ALL;
-ENTITY tech_ddr3_stratixiv IS
+ENTITY tech_ddr_stratixiv IS
GENERIC (
g_tech_ddr : t_c_tech_ddr
);
@@ -55,17 +55,19 @@ ENTITY tech_ddr3_stratixiv IS
phy_io : INOUT t_tech_ddr_phy_io;
phy_ou : OUT t_tech_ddr_phy_ou
);
-END tech_ddr3_stratixiv;
+END tech_ddr_stratixiv;
-ARCHITECTURE str OF tech_ddr3_stratixiv IS
+ARCHITECTURE str OF tech_ddr_stratixiv IS
+
+ CONSTANT c_gigabytes : NATURAL := func_tech_ddr_module_size(g_tech_ddr)
SIGNAL i_ctlr_gen_rst : STD_LOGIC;
SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC;
BEGIN
- gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF func_tech_ddr_module_size(g_tech_ddr)=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE GENERATE
+ gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
PORT MAP (
pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
@@ -117,7 +119,7 @@ BEGIN
);
END GENERATE;
- gen_ip_stratixiv_ddr3_uphy_4g_800_slave : IF func_tech_ddr_module_size(g_tech_ddr)=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=FALSE GENERATE
+ gen_ip_stratixiv_ddr3_uphy_4g_800_slave : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=FALSE GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
PORT MAP (
pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
--
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