diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd
index 2cf7286d9f9eadc29916fb9655ea99e3777b5f73..6d464cde5dd91303448c89a6c59b2c4746ecd9d8 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd
@@ -431,7 +431,7 @@ ARCHITECTURE str OF arts_unb1_sc4_mm_master IS
reg_tab_dest_ip_write_export : OUT STD_LOGIC;
reg_tab_dest_ip_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_tab_dest_mac_address_export : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ reg_tab_dest_mac_address_export : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
reg_tab_dest_mac_read_export : OUT STD_LOGIC;
reg_tab_dest_mac_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_tab_dest_mac_write_export : OUT STD_LOGIC;
@@ -849,7 +849,7 @@ BEGIN
reg_tab_dest_ip_write_export => reg_tab_dest_ip_mosi.wr,
reg_tab_dest_ip_writedata_export => reg_tab_dest_ip_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_tab_dest_mac_address_export => reg_tab_dest_mac_mosi.address(2 DOWNTO 0),
+ reg_tab_dest_mac_address_export => reg_tab_dest_mac_mosi.address(3 DOWNTO 0),
reg_tab_dest_mac_read_export => reg_tab_dest_mac_mosi.rd,
reg_tab_dest_mac_readdata_export => reg_tab_dest_mac_miso.rddata(c_word_w-1 DOWNTO 0),
reg_tab_dest_mac_write_export => reg_tab_dest_mac_mosi.wr,
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab.vhd
index 72941b7ebd107cd218ec9858f7ef126ca40452bf..8a81e17d6aa459b8b7308f646bf06ff1b0256198 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab.vhd
@@ -118,15 +118,14 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab IS
SIGNAL dp_pipeline_ready_snk_in_arr : t_dp_sosi_arr(2-1 DOWNTO 0);
SIGNAL dp_pipeline_ready_snk_out_arr : t_dp_siso_arr(2-1 DOWNTO 0);
- SIGNAL dp_mux_src_out : t_dp_sosi;
CONSTANT c_nof_cbs_per_node : NATURAL := 5;
-- Signals for getting the destination ip and mac addresses from Python
CONSTANT c_mm_reg_dest_ip : t_c_mem := (1, ceil_log2(c_nof_cbs_per_node), 32, c_nof_cbs_per_node, '0'); -- latency, adr_w, dat_w, optional actual data words used (<= 2^adr_w), optional init value
- CONSTANT c_mm_reg_dest_mac : t_c_mem := (1, ceil_log2(c_nof_cbs_per_node), 48, c_nof_cbs_per_node, '0');
+ CONSTANT c_mm_reg_dest_mac : t_c_mem := (1, ceil_log2(c_nof_cbs_per_node*2), 32, c_nof_cbs_per_node*2, '0');
CONSTANT c_mm_reg_init_dest_ip : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := RESIZE_UVEC( X"05050505" & X"04040404" & X"03030303" & X"02020202" & X"01010101", c_mem_reg_init_w);
- CONSTANT c_mm_reg_init_dest_mac : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := RESIZE_UVEC(X"AAAA05050505" & X"AAAA04040404" & X"AAAA03030303" & X"AAAA02020202" & X"AAAA01010101", c_mem_reg_init_w);
+ CONSTANT c_mm_reg_init_dest_mac : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := RESIZE_UVEC(X"0000AAAA05050505" & X"0000AAAA04040404" & X"0000AAAA03030303" & X"0000AAAA02020202" & X"0000AAAA01010101", c_mem_reg_init_w);
SIGNAL reg_dest_ip : STD_LOGIC_VECTOR(32*c_nof_cbs_per_node-1 downto 0);
- SIGNAL reg_dest_mac : STD_LOGIC_VECTOR(48*c_nof_cbs_per_node-1 downto 0);
+ SIGNAL reg_dest_mac : STD_LOGIC_VECTOR(32*2*c_nof_cbs_per_node-1 downto 0);
BEGIN
@@ -312,27 +311,31 @@ BEGIN
-----------------------------------------------------------------------------
-- Mux IQUV and I streams onto single 64b stream
-----------------------------------------------------------------------------
- dp_pipeline_ready_snk_in_arr(0) <= arts_unb1_sc4_output_iquv_packetizer_src_out;
- arts_unb1_sc4_output_iquv_packetizer_src_in <= dp_pipeline_ready_snk_out_arr(0);
-
- dp_pipeline_ready_snk_in_arr(1) <= arts_unb1_sc4_output_i_packetizer_src_out;
- arts_unb1_sc4_output_i_packetizer_src_in <= dp_pipeline_ready_snk_out_arr(1);
+-- dp_pipeline_ready_snk_in_arr(0) <= arts_unb1_sc4_output_iquv_packetizer_src_out;
+ dp_mux_snk_in_arr(0) <= arts_unb1_sc4_output_iquv_packetizer_src_out;
+-- arts_unb1_sc4_output_iquv_packetizer_src_in <= dp_pipeline_ready_snk_out_arr(0);
+ arts_unb1_sc4_output_iquv_packetizer_src_in <= dp_mux_snk_out_arr(0);
+
+-- dp_pipeline_ready_snk_in_arr(1) <= arts_unb1_sc4_output_i_packetizer_src_out;
+ dp_mux_snk_in_arr(1) <= arts_unb1_sc4_output_i_packetizer_src_out;
+-- arts_unb1_sc4_output_i_packetizer_src_in <= dp_pipeline_ready_snk_out_arr(1);
+ arts_unb1_sc4_output_i_packetizer_src_in <= dp_mux_snk_out_arr(1);
-- arts_unb1_sc4_output_i_packetizer_src_in <= c_dp_siso_rdy;
-- dp_mux_snk_in_arr(1) <= c_dp_sosi_rst;
- gen_pipeline_ready : FOR i IN 0 TO 1 GENERATE
- u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
- PORT MAP(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_pipeline_ready_snk_in_arr(i),
- snk_out => dp_pipeline_ready_snk_out_arr(i),
-
- src_in => dp_mux_snk_out_arr(i),
- src_out => dp_mux_snk_in_arr(i)
- );
- END GENERATE;
+-- gen_pipeline_ready : FOR i IN 0 TO 1 GENERATE
+-- u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
+-- PORT MAP(
+-- rst => dp_rst,
+-- clk => dp_clk,
+--
+-- snk_in => dp_pipeline_ready_snk_in_arr(i),
+-- snk_out => dp_pipeline_ready_snk_out_arr(i),
+--
+-- src_in => dp_mux_snk_out_arr(i),
+-- src_out => dp_mux_snk_in_arr(i)
+-- );
+-- END GENERATE;
u_dp_mux : ENTITY dp_lib.dp_mux
GENERIC MAP (
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
index 7ca14de0911839f2368ebc6cd3af21b96af8f03b..8247e3b4a191f283264785d98fd3c941b406f913 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
@@ -61,7 +61,7 @@ ENTITY arts_unb1_sc4_output_tab_i_packetizer IS
general_bsn : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
reg_dest_ip : STD_LOGIC_VECTOR(32*5-1 downto 0);
- reg_dest_mac : STD_LOGIC_VECTOR(48*5-1 downto 0);
+ reg_dest_mac : STD_LOGIC_VECTOR(64*5-1 downto 0);
src_out : OUT t_dp_sosi;
src_in : IN t_dp_siso;
@@ -161,7 +161,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS
CONSTANT c_udp_dst_prt_base : NATURAL := 5000;
CONSTANT c_nof_bytes_per_header : NATURAL := 90;
- CONSTANT c_dp_fifo_sc_large_size : NATURAL := 16384;
+ CONSTANT c_dp_fifo_sc_large_size : NATURAL := 4096;--16384;
CONSTANT c_fifo_fill_fill : NATURAL := ceil_div((g_nof_bytes_per_packet + c_nof_bytes_per_header), 8);
CONSTANT c_fifo_fill_size : NATURAL := 1024;
@@ -199,14 +199,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS
SIGNAL dp_xonoff_snk_in : t_dp_sosi;
SIGNAL dp_xonoff_snk_out : t_dp_siso;
SIGNAL dp_xonoff_src_out : t_dp_sosi;
--- SIGNAL dp_xonoff_src_in : t_dp_siso;
--- SIGNAL dp_field_blk_snk_in_arr : t_dp_sosi_arr(c_nof_offloadstreams-1 DOWNTO 0);
--- SIGNAL dp_field_blk_snk_out_arr : t_dp_siso_arr(c_nof_offloadstreams-1 DOWNTO 0);
--- SIGNAL dp_field_blk_src_out_arr : t_dp_sosi_arr(c_nof_offloadstreams-1 DOWNTO 0);
--- SIGNAL dp_field_blk_src_in_arr : t_dp_siso_arr(c_nof_offloadstreams-1 DOWNTO 0);
-
--- SIGNAL arts_unb1_sc4_output_i_framer_src_out : t_dp_sosi;
SIGNAL dp_fifo_sc_large_snk_in : t_dp_sosi;
SIGNAL dp_fifo_sc_large_src_out : t_dp_sosi;
SIGNAL dp_fifo_sc_large_src_in : t_dp_siso;
@@ -214,12 +207,6 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS
SIGNAL dp_fifo_info_src_out : t_dp_sosi;
SIGNAL dp_fifo_fill_sc_snk_in : t_dp_sosi;
SIGNAL dp_fifo_fill_sc_snk_out : t_dp_siso;
--- SIGNAL dp_demux_inverted_src_out_arr : t_dp_sosi_arr(0 TO c_nof_offloadstreams-1);
--- SIGNAL dp_demux_inverted_src_in_arr : t_dp_siso_arr(0 TO c_nof_offloadstreams-1);
--- SIGNAL dp_mux_inverted_snk_in_arr : t_dp_sosi_arr(0 TO c_nof_offloadstreams-1);
--- SIGNAL dp_mux_inverted_snk_out_arr : t_dp_siso_arr(0 TO c_nof_offloadstreams-1);
--- SIGNAL dp_mux_src_out : t_dp_sosi;
--- SIGNAL dp_mux_src_in : t_dp_siso;
BEGIN
@@ -415,7 +402,7 @@ BEGIN
);
-- Large dp_fifo
- -- This Fifo is 16k deep x 64 wide data + control signals
+ -- This Fifo is 4k deep x 64 wide data + control signals
-- The channel and empty fields go through dp_fifo_info instead, to save blockram
-- Its purpose is to hold enough data ahead of the I/IQUV mux that the backpressure path
-- all the way back through the packetizer and reordering logic can be broken
@@ -467,69 +454,12 @@ BEGIN
);
- -----------------------------------------------------------------------------
- -- Distribute the packets to the five concat blocks
- -----------------------------------------------------------------------------
--- u_dp_demux : ENTITY dp_lib.dp_demux
--- GENERIC MAP (
--- g_mode => 2, -- Use sel ctrl
--- g_combined => FALSE, -- Only the current channel needs to be ready
--- g_nof_output => c_nof_offloadstreams,
--- g_remove_channel_lo => FALSE
--- )
--- PORT MAP (
--- clk => dp_clk,
--- rst => dp_rst,
---
--- sel_ctrl => TO_UINT(dp_xonoff_src_out.channel(15 DOWNTO 13)), -- Field that contains the 3 bits needed to encode beam index 0..4
---
--- snk_in => dp_xonoff_src_out,
--- snk_out => dp_xonoff_src_in,
---
--- src_out_arr => dp_demux_inverted_src_out_arr, -- output: 5 streams (0 TO 4)
--- src_in_arr => dp_demux_inverted_src_in_arr -- backpressure input: 5 streams (0 TO 4)
--- );
-----------------------------------------------------------------------------
-- Header insertion
-----------------------------------------------------------------------------
--- gen_reorder_demux_src : FOR i IN 0 to c_nof_offloadstreams-1 GENERATE
--- BEGIN
--- dp_field_blk_snk_in_arr(i) <= dp_demux_inverted_src_out_arr(i);
--- dp_demux_inverted_src_in_arr(i) <= dp_field_blk_snk_out_arr(i);
--- END GENERATE;
-
-
--- u_dp_concat_field_blk : ENTITY dp_lib.dp_concat_field_blk
--- GENERIC MAP (
--- g_nof_streams => c_nof_offloadstreams,
--- g_data_w => c_data_w,
--- g_hdr_field_arr => c_hdr_field_arr,
--- g_hdr_field_sel => c_hdr_field_sel,
--- g_in_symbol_w => c_byte_w,
--- g_out_symbol_w => c_byte_w
--- )
--- PORT MAP (
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
---
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
- -- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
--- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
---
--- snk_in_arr => dp_field_blk_snk_in_arr,
--- snk_out_arr => dp_field_blk_snk_out_arr,
---
- -- src_out_arr => dp_field_blk_src_out_arr,
--- src_in_arr => dp_field_blk_src_in_arr,
---
--- hdr_fields_in_arr => hdr_fields_in_arr
--- );
-
---------------------------------------------------------------------------------------
-- Extract the chip and backplane numbers from ID
---------------------------------------------------------------------------------------
@@ -556,7 +486,7 @@ BEGIN
id_tab <= RESIZE_UVEC(dp_fifo_info_src_out.channel(19 DOWNTO 16), c_byte_w);
id_udp_dst_prt <= TO_UVEC(c_udp_dst_prt_base + TO_UINT(id_cb), 16);
id_dest_ip <= reg_dest_ip(TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*32+31 DOWNTO TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*32);
- id_dest_mac <= reg_dest_ip(TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*48+47 DOWNTO TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*48);
+ id_dest_mac <= reg_dest_mac(TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*64+47 DOWNTO TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*64);
---------------------------------------------------------------------------------------
@@ -607,53 +537,6 @@ BEGIN
hdr_fields_in_arr => hdr_fields_in_arr
);
- -----------------------------------------------------------------------------
- -- dp_mux the 5 streams into a single stream again
- -- TODO: better to pass the channel through dp_concat_field_blk
- -- TODO: save resources by not muxing the data
- -----------------------------------------------------------------------------
--- gen_reorder_mux_snk : FOR i IN 0 to c_nof_offloadstreams-1 GENERATE
--- BEGIN
--- dp_mux_inverted_snk_in_arr(i) <= dp_field_blk_src_out_arr(i);
--- dp_field_blk_src_in_arr(i) <= dp_mux_inverted_snk_out_arr(i);
--- END GENERATE;
---
--- u_mux : ENTITY dp_lib.dp_mux
--- GENERIC MAP (
--- g_data_w => c_data_w,
--- g_empty_w => c_empty_w,
--- g_use_empty => TRUE,
--- g_error_w => 1,
--- g_mode => 2, -- use sel ctrl input
--- g_nof_input => c_nof_offloadstreams,
--- g_fifo_size => array_init(1024, c_nof_offloadstreams), -- FIFO is not used, but generic must match g_nof_input
--- g_fifo_fill => array_init(0, c_nof_offloadstreams) -- FIFO is not used, but generic must match g_nof_input
--- )
--- PORT MAP (
--- rst => dp_rst,
--- clk => dp_clk,
---
--- sel_ctrl => TO_UINT(dp_xonoff_src_out.channel(15 DOWNTO 13)), -- Field that contains the 3 bits needed to encode beam index 0..4
---
--- -- ST sinks
--- snk_out_arr => dp_mux_inverted_snk_out_arr,
--- snk_in_arr => dp_mux_inverted_snk_in_arr,
--- -- ST source
--- src_in => dp_mux_src_in,
--- src_out => dp_mux_src_out
--- );
---
--- u_dp_pipeline_ready_postmux : ENTITY dp_lib.dp_pipeline_ready
--- PORT MAP(
--- rst => dp_rst,
--- clk => dp_clk,
---
--- snk_in => dp_mux_src_out,
--- snk_out => dp_mux_src_in,
---
--- src_in => c_dp_siso_rdy, --dp_fifo_fill_sc_snk_out,
--- src_out => dp_fifo_sc_large_snk_in
--- );
-----------------------------------------------------------------------------
-- Fill FIFO to buffer 8000 Bytes
@@ -671,6 +554,7 @@ BEGIN
g_use_complex => FALSE,
g_fifo_fill => c_fifo_fill_fill,
g_fifo_size => c_fifo_fill_size
+ --g_fifo_af_margin => 16 -- margin below full
)
PORT MAP (
rst => dp_rst,
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd
index 3252ea5e2103b3c0cc52d516e0faa372f4ac0c60..d57ca792d401a6c277fd3ac890fc0a3c081a4659 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd
@@ -63,6 +63,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_reorder IS
CONSTANT c_data_w : NATURAL := c_indata_w * 8;
CONSTANT c_empty_w : NATURAL := ceil_log2(c_data_w /c_byte_w);
CONSTANT c_nof_fifos : NATURAL := g_nof_tabs * g_nof_frequency_channels;
+ CONSTANT c_gap : NATURAL := 1024;
CONSTANT c_nof_words_per_packet : NATURAL := ceil_div(g_nof_bytes_per_packet, (c_data_w/c_byte_w));
CONSTANT c_dp_fifo_sc_size : NATURAL := 1024; --8192/8;
@@ -73,11 +74,12 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_reorder IS
SIGNAL dp_repack_snk_in_arr : t_dp_sosi_arr(g_nof_tabs*g_nof_frequency_channels-1 DOWNTO 0);
SIGNAL dp_fifo_sc_snk_in_arr : t_dp_sosi_arr(g_nof_tabs*g_nof_frequency_channels-1 DOWNTO 0);
SIGNAL dp_fifo_sc_src_out_arr : t_dp_sosi_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1);
+ SIGNAL dp_folder_snk_in_arr : t_dp_sosi_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1);
SIGNAL dp_fifo_sc_src_in_arr : t_dp_siso_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1);
SIGNAL dp_fifo_sc_src_in_arr_1 : t_dp_siso_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1);
SIGNAL dp_folder_src_out_arr : t_dp_sosi_arr(0 TO 0);
- SIGNAL dp_pipeline_ready_src_out_arr : t_dp_sosi_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1);
- SIGNAL dp_pipeline_ready_src_in_arr : t_dp_siso_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1);
+-- SIGNAL dp_pipeline_ready_src_out_arr : t_dp_sosi_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1);
+-- SIGNAL dp_pipeline_ready_src_in_arr : t_dp_siso_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1);
SIGNAL dp_counter_count_src_out_arr : t_dp_sosi_arr(1 DOWNTO 0);
SIGNAL dp_mux_src_in : t_dp_siso;
SIGNAL dp_mux_src_out : t_dp_sosi;
@@ -224,32 +226,12 @@ BEGIN
src_out => dp_fifo_sc_src_out_arr(tabno*g_nof_frequency_channels + i)
);
--- u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
--- PORT MAP(
--- rst => dp_rst,
--- clk => dp_clk,
---
--- snk_in => dp_fifo_sc_src_out_arr(tabno*g_nof_frequency_channels + i),
--- snk_out => dp_fifo_sc_src_in_arr(tabno*g_nof_frequency_channels + i),
---
--- src_in => dp_pipeline_ready_src_in_arr(tabno*g_nof_frequency_channels + i),
--- src_out => dp_pipeline_ready_src_out_arr(tabno*g_nof_frequency_channels + i)
--- );
---
--- u_dp_src_out_timer : ENTITY dp_lib.dp_src_out_timer
--- GENERIC MAP (
--- g_init_valid_delay => (c_nof_words_per_packet + 16) * (tabno*g_nof_frequency_channels + i),
--- g_block_period => c_nof_words_per_packet,
--- g_block_len => c_nof_words_per_packet
--- )
--- PORT MAP (
--- rst => dp_rst,
--- clk => dp_clk,
---
--- init_valid_delay_ref => dp_counter_count_src_out_arr(1).eop,
--- snk_in => dp_pipeline_ready_src_out_arr(tabno*g_nof_frequency_channels + i),
--- snk_out => dp_pipeline_ready_src_in_arr(tabno*g_nof_frequency_channels + i)
--- );
+
+ p_emptytochannel : PROCESS(dp_fifo_sc_src_out_arr(tabno*g_nof_frequency_channels + i))
+ BEGIN
+ dp_folder_snk_in_arr(tabno*g_nof_frequency_channels + i) <= dp_fifo_sc_src_out_arr(tabno*g_nof_frequency_channels + i);
+ dp_folder_snk_in_arr(tabno*g_nof_frequency_channels + i).channel(c_empty_w-1 downto 0) <= dp_fifo_sc_src_out_arr(tabno*g_nof_frequency_channels + i).empty(c_empty_w-1 downto 0);
+ END PROCESS;
END GENERATE;
END GENERATE;
@@ -257,23 +239,29 @@ BEGIN
------------------------------------------------------------------------------
-- Alternative to mux. Assumes no backpressure.
-- Fold onto one stream
+ -- It doesn't forward the empty field, so use channel instead
------------------------------------------------------------------------------
u_dp_folder : ENTITY dp_lib.dp_folder
GENERIC MAP (
g_nof_inputs => g_nof_tabs * g_nof_frequency_channels,
- g_nof_folds => -1
+ g_nof_folds => -1,
+ g_use_channel => TRUE
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
- snk_in_arr => dp_fifo_sc_src_out_arr,
+ snk_in_arr => dp_folder_snk_in_arr,
src_out_arr => dp_folder_src_out_arr
);
- src_out <= dp_folder_src_out_arr(0);
+ p_channeltoempty : PROCESS(dp_folder_src_out_arr(0))
+ BEGIN
+ src_out <= dp_folder_src_out_arr(0);
+ src_out.empty(c_empty_w-1 downto 0) <= dp_folder_src_out_arr(0).channel(c_empty_w-1 downto 0);
+ END PROCESS;
-----------------------------------------------------------------------------
@@ -358,7 +346,7 @@ BEGIN
GENERIC MAP (
g_nof_counters => 2,
g_range_start => (0,0,0,0,0,0,0,0, 0, 0),
- g_range_stop => (0,0,0,0,0,0,0,0, g_nof_frequency_channels*g_nof_tabs, c_nof_words_per_packet),
+ g_range_stop => (0,0,0,0,0,0,0,0, g_nof_frequency_channels*g_nof_tabs, c_nof_words_per_packet+c_gap),
g_range_step => (0,0,0,0,0,0,0,0, 1, 1),
g_pipeline_src_out => 1,
g_pipeline_src_in => 0
@@ -379,7 +367,8 @@ BEGIN
gen_readout_ready : FOR i IN 0 TO g_nof_frequency_channels*g_nof_tabs - 1 GENERATE
dp_fifo_sc_src_in_arr(i).xon <= '1';
- dp_fifo_sc_src_in_arr(i).ready <= '1' WHEN dp_counter_readout_enable_1 = '1' and dp_counter_readout_count_src_out_arr(1).data(5 DOWNTO 0) = TO_UVEC(i, 6) ELSE '0';
+ dp_fifo_sc_src_in_arr(i).ready <= '1' WHEN dp_counter_readout_enable_1 = '1' and dp_counter_readout_count_src_out_arr(1).data(5 DOWNTO 0) = TO_UVEC(i, 6)
+ and dp_counter_readout_count_src_out_arr(0).data(10 DOWNTO 0) < TO_UVEC(c_nof_words_per_packet,11) ELSE '0';
END GENERATE;
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
index 7a6c76e7106f6d7851f7cf17da9766204447eee4..8f949e5522ca02e9249987419367f0609e2dffc8 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
@@ -76,6 +76,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_iquv_buffer IS
SIGNAL dp_fifo_sc_src_out_arr : t_dp_sosi_arr(0 TO g_nof_tabs-1);
SIGNAL dp_fifo_sc_src_in_arr : t_dp_siso_arr(0 TO g_nof_tabs-1);
SIGNAL dp_fifo_sc_src_in_arr_1 : t_dp_siso_arr(0 TO g_nof_tabs-1);
+ SIGNAL dp_folder_snk_in_arr : t_dp_sosi_arr(0 TO g_nof_tabs-1);
SIGNAL dp_folder_src_out_arr : t_dp_sosi_arr(0 TO 0);
SIGNAL dp_pipeline_ready_src_out_arr : t_dp_sosi_arr(0 TO g_nof_tabs-1);
SIGNAL dp_pipeline_ready_src_in_arr : t_dp_siso_arr(0 TO g_nof_tabs-1);
@@ -198,33 +199,12 @@ BEGIN
src_out => dp_fifo_sc_src_out_arr(tabno)
);
--- u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
--- PORT MAP(
--- rst => dp_rst,
--- clk => dp_clk,
---
--- snk_in => dp_fifo_sc_src_out_arr(tabno),
--- snk_out => dp_fifo_sc_src_in_arr(tabno),
---
--- src_in => dp_pipeline_ready_src_in_arr(tabno),
--- src_out => dp_pipeline_ready_src_out_arr(tabno)
--- );
---
---
--- u_dp_src_out_timer : ENTITY dp_lib.dp_src_out_timer
--- GENERIC MAP (
--- g_init_valid_delay => (c_nof_words_per_packet + 16) * tabno,
--- g_block_period => c_nof_words_per_packet + 16,
--- g_block_len => c_nof_words_per_packet
--- )
--- PORT MAP (
--- rst => dp_rst,
--- clk => dp_clk,
---
--- init_valid_delay_ref => dp_counter_count_src_out_arr(0).eop,
--- snk_in => dp_pipeline_ready_src_out_arr(tabno),
--- snk_out => dp_pipeline_ready_src_in_arr(tabno)
--- );
+
+ p_emptytochannel : PROCESS(dp_fifo_sc_src_out_arr(tabno))
+ BEGIN
+ dp_folder_snk_in_arr(tabno) <= dp_fifo_sc_src_out_arr(tabno);
+ dp_folder_snk_in_arr(tabno).channel(c_empty_w-1 downto 0) <= dp_fifo_sc_src_out_arr(tabno).empty(c_empty_w-1 downto 0);
+ END PROCESS;
END GENERATE;
@@ -236,61 +216,23 @@ BEGIN
u_dp_folder : ENTITY dp_lib.dp_folder
GENERIC MAP (
g_nof_inputs => g_nof_tabs,
- g_nof_folds => -1
+ g_nof_folds => -1,
+ g_use_channel => TRUE
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
- snk_in_arr => dp_fifo_sc_src_out_arr,
+ snk_in_arr => dp_folder_snk_in_arr,
src_out_arr => dp_folder_src_out_arr
);
- src_out <= dp_folder_src_out_arr(0);
-
- -----------------------------------------------------------------------------
- -- dp_mux the g_nof_tabs streams into a single stream
- -----------------------------------------------------------------------------
--- u_mux : ENTITY dp_lib.dp_mux
--- GENERIC MAP (
--- g_data_w => c_data_w,
--- g_empty_w => c_empty_w,
--- g_use_empty => TRUE,
--- g_error_w => 1,
--- g_mode => 1, -- forced round robin mode
--- g_nof_input => g_nof_tabs,
--- g_fifo_size => array_init(1024, g_nof_tabs), -- FIFO is not used, but generic must match g_nof_input
--- g_fifo_fill => array_init(0, g_nof_tabs) -- FIFO is not used, but generic must match g_nof_input
--- )
--- PORT MAP (
--- rst => dp_rst,
--- clk => dp_clk,
- -- ST sinks
--- snk_out_arr => dp_pipeline_ready_src_in_arr, -- OUT = request to upstream ST source
--- snk_in_arr => dp_pipeline_ready_src_out_arr,
- -- ST source
--- src_in => c_dp_siso_rdy, --dp_mux_src_in, -- IN = request from downstream ST sink
--- src_out => dp_mux_src_out
--- );
---
--- u_dp_pipeline_ready_postmux : ENTITY dp_lib.dp_pipeline_ready
--- PORT MAP(
--- rst => dp_rst,
--- clk => dp_clk,
---
--- snk_in => dp_mux_src_out,
--- snk_out => dp_mux_src_in,
---
--- src_in => dp_pipeline_ready_postmux_src_in,
--- src_out => open --src_out
--- );
-
- -----------------------------------------------------------------------------
- -- Enable fifo readout
- -----------------------------------------------------------------------------
--- dp_pipeline_ready_postmux_src_in.ready <= src_in.ready and end_of_packet_latched and not dp_fifo_sc_src_out_arr(c_nof_fifos-1).eop;
--- dp_pipeline_ready_postmux_src_in.xon <= src_in.xon ;
+ p_channeltoempty : PROCESS(dp_folder_src_out_arr(0))
+ BEGIN
+ src_out <= dp_folder_src_out_arr(0);
+ src_out.empty(c_empty_w-1 downto 0) <= dp_folder_src_out_arr(0).channel(c_empty_w-1 downto 0);
+ END PROCESS;
-----------------------------------------------------------------------------
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
index b3289064760595d025cafda8d56a78d424180702..6e3c1fc27b2aa2edb1921adda599cd05073fe9a5 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
@@ -61,7 +61,7 @@ ENTITY arts_unb1_sc4_output_tab_iquv_packetizer IS
general_bsn : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
reg_dest_ip : STD_LOGIC_VECTOR(32*5-1 downto 0);
- reg_dest_mac : STD_LOGIC_VECTOR(48*5-1 downto 0);
+ reg_dest_mac : STD_LOGIC_VECTOR(64*5-1 downto 0);
snk_in : IN t_dp_sosi;
snk_out : OUT t_dp_siso;
@@ -111,7 +111,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_iquv_packetizer IS
CONSTANT c_nof_words_per_block : NATURAL := 8000;
CONSTANT c_nof_blocks_per_packet : NATURAL := 1;
CONSTANT c_nof_offloadstreams : NATURAL := 5;
- CONSTANT c_udp_dst_prt_base : NATURAL := 5000;
+ CONSTANT c_udp_dst_prt_base : NATURAL := 6000;
CONSTANT c_nof_bytes_per_header : NATURAL := 90;
CONSTANT c_dp_fifo_sc_large_size : NATURAL := 8192;
CONSTANT c_fifo_fill_fill : NATURAL := ceil_div((g_nof_bytes_per_packet + c_nof_bytes_per_header), 8);
@@ -155,7 +155,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_iquv_packetizer IS
( field_name_pad("id_cb_index" ), "RW", 8, field_default(0) ),
( field_name_pad("id_tab_index" ), "RW", 8, field_default(0) ),
( field_name_pad("id_channel_index" ), "RW", 16, field_default(0) ),
- ( field_name_pad("id_application_payload_size" ), "RW", 16, field_default(6250) ),
+ ( field_name_pad("id_application_payload_size" ), "RW", 16, field_default(8000) ),
( field_name_pad("id_timestamp" ), "RW", 64, field_default(0) ),
( field_name_pad("id_sequence_number" ), "RW", 8, field_default(0) ),
( field_name_pad("id_reserved" ), "RW", 56, field_default(0) ),
@@ -397,7 +397,7 @@ BEGIN
g_nof_streams => 1,
g_combine_streams => TRUE,
g_bypass => FALSE,
- g_timeout_time => 10,
+-- g_timeout_time => 10,
g_default_value => sel_a_b(g_sim, '1', '0') -- Sim: on by default like block gens
)
PORT MAP(
@@ -556,7 +556,7 @@ BEGIN
id_tab <= RESIZE_UVEC(dp_fifo_info_src_out.channel(19 DOWNTO 16), c_byte_w);
id_udp_dst_prt <= TO_UVEC(c_udp_dst_prt_base + TO_UINT(id_cb), 16);
id_dest_ip <= reg_dest_ip(TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*32+31 DOWNTO TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*32);
- id_dest_mac <= reg_dest_ip(TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*48+47 DOWNTO TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*48);
+ id_dest_mac <= reg_dest_mac(TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*64+47 DOWNTO TO_UINT(dp_fifo_info_src_out.channel(15 DOWNTO 13))*64);
---------------------------------------------------------------------------------------
-- Wire the hardwired header fields to DP signals and ID