diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index f2bf0353631a4a74acbd488437b114704bbec67c..75b9c2f3d0cee73a2f5c7bf3f328d6366460d78c 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -82,15 +82,25 @@ ENTITY mmm_unb2_test IS
reg_ppsh_mosi : OUT t_mem_mosi;
reg_ppsh_miso : IN t_mem_miso;
- -- eth1g
- eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_tse_mosi : OUT t_mem_mosi;
- eth1g_tse_miso : IN t_mem_miso;
- eth1g_reg_mosi : OUT t_mem_mosi;
- eth1g_reg_miso : IN t_mem_miso;
- eth1g_reg_interrupt : IN STD_LOGIC;
- eth1g_ram_mosi : OUT t_mem_mosi;
- eth1g_ram_miso : IN t_mem_miso;
+ -- eth1g ch0
+ eth1g_eth0_mm_rst : OUT STD_LOGIC;
+ eth1g_eth0_tse_mosi : OUT t_mem_mosi;
+ eth1g_eth0_tse_miso : IN t_mem_miso;
+ eth1g_eth0_reg_mosi : OUT t_mem_mosi;
+ eth1g_eth0_reg_miso : IN t_mem_miso;
+ eth1g_eth0_reg_interrupt : IN STD_LOGIC;
+ eth1g_eth0_ram_mosi : OUT t_mem_mosi;
+ eth1g_eth0_ram_miso : IN t_mem_miso;
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst : OUT STD_LOGIC;
+ eth1g_eth1_tse_mosi : OUT t_mem_mosi;
+ eth1g_eth1_tse_miso : IN t_mem_miso;
+ eth1g_eth1_reg_mosi : OUT t_mem_mosi;
+ eth1g_eth1_reg_miso : IN t_mem_miso;
+ eth1g_eth1_reg_interrupt : IN STD_LOGIC;
+ eth1g_eth1_ram_mosi : OUT t_mem_mosi;
+ eth1g_eth1_ram_miso : IN t_mem_miso;
-- EPCS read
reg_dpmm_data_mosi : OUT t_mem_mosi;
@@ -216,10 +226,10 @@ ARCHITECTURE str OF mmm_unb2_test IS
SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
SIGNAL sim_eth_psc_access : STD_LOGIC;
- SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
- SIGNAL i_eth1g_reg_miso : t_mem_miso;
+ SIGNAL i_eth1g_eth1_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth1g_eth1_reg_miso : t_mem_miso;
- SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL sim_eth1g_eth1_reg_mosi : t_mem_mosi;
SIGNAL i_reset_n : STD_LOGIC;
----------------------------------------------------------------------------
@@ -246,7 +256,8 @@ BEGIN
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
- eth1g_mm_rst <= mm_rst;
+ eth1g_eth0_mm_rst <= mm_rst;
+ eth1g_eth1_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -313,8 +324,10 @@ BEGIN
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso);
+ u_mm_file_reg_eth0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, mm_clk, eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+ u_mm_file_reg_eth1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
+ PORT MAP(mm_rst, mm_clk, eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
@@ -330,25 +343,25 @@ BEGIN
BEGIN
sim_eth_mm_bus_switch <= '1';
- eth1g_tse_mosi.wr <= '0';
- eth1g_tse_mosi.rd <= '0';
+ eth1g_eth1_tse_mosi.wr <= '0';
+ eth1g_eth1_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
WAIT UNTIL rising_edge(mm_clk);
- proc_tech_tse_setup(c_tech_arria10, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+ proc_tech_tse_setup(c_tech_arria10, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth1_tse_miso, eth1g_eth1_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth1_reg_miso, sim_eth1g_eth1_reg_mosi); -- control rx en
sim_eth_mm_bus_switch <= '0';
WAIT;
END PROCESS;
- p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
+ p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_eth1_reg_mosi, i_eth1g_eth1_reg_mosi)
BEGIN
IF sim_eth_mm_bus_switch = '1' THEN
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ eth1g_eth1_reg_mosi <= sim_eth1g_eth1_reg_mosi;
ELSE
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ eth1g_eth1_reg_mosi <= i_eth1g_eth1_reg_mosi;
END IF;
END PROCESS;
@@ -376,25 +389,45 @@ BEGIN
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
pio_wdi_external_connection_export => pout_wdi,
- avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_reset_export => eth1g_eth0_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
+ avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
+
+ avs_eth_1_reset_export => eth1g_eth1_mm_rst,
+ avs_eth_1_clk_export => OPEN,
+ avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
+ avs_eth_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
+ avs_eth_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
+ avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
+ avs_eth_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
+ avs_eth_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
+ avs_eth_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
+ avs_eth_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_irq_export => eth1g_eth1_reg_interrupt,
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 0a02f4433e1c8288653c6e3848f88810ec17dcca..0eaf14baa5bbf5b1525495a2da5a33d25ee7750a 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -216,15 +216,25 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_unb_sens_mosi : t_mem_mosi;
SIGNAL reg_unb_sens_miso : t_mem_miso;
- -- eth1g
- SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso;
+ -- eth1g ch0
+ SIGNAL eth1g_eth0_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_eth0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_eth0_tse_miso : t_mem_miso;
+ SIGNAL eth1g_eth0_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_eth0_reg_miso : t_mem_miso;
+ SIGNAL eth1g_eth0_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_eth0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_eth0_ram_miso : t_mem_miso;
+
+ -- eth1g ch1
+ SIGNAL eth1g_eth1_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_eth1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_eth1_tse_miso : t_mem_miso;
+ SIGNAL eth1g_eth1_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_eth1_reg_miso : t_mem_miso;
+ SIGNAL eth1g_eth1_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_eth1_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_eth1_ram_miso : t_mem_miso;
-- EPCS read
SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
@@ -422,15 +432,15 @@ BEGIN
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
-- eth1g UDP streaming ports
udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
@@ -501,15 +511,25 @@ BEGIN
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-- EPCS read
reg_dpmm_data_mosi => reg_dpmm_data_mosi,
@@ -658,11 +678,14 @@ BEGIN
-- Interface : 1GbE
-----------------------------------------------------------------------------
gen_wires_1GbE : IF c_use_1GbE=TRUE GENERATE
- eth1g_udp_tx_sosi_arr(0) <= dp_offload_tx_1GbE_src_out_arr(0);
- dp_offload_tx_1GbE_src_in_arr(0) <= eth1g_udp_tx_siso_arr(0);
+ gen_1GbE_wires : FOR i IN 0 TO c_nof_streams_1GbE-1 GENERATE
- dp_offload_rx_1GbE_snk_in_arr(0) <= eth1g_udp_rx_sosi_arr(0);
- eth1g_udp_rx_siso_arr(0) <= dp_offload_rx_1GbE_snk_out_arr(0);
+ eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
+ dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
+ dp_offload_rx_1GbE_snk_in_arr(i) <= eth1g_udp_rx_sosi_arr(i);
+ eth1g_udp_rx_siso_arr(i) <= dp_offload_rx_1GbE_snk_out_arr(i);
+
+ END GENERATE;
END GENERATE;