From 6ca4a3ac3fe51e095cc69d0592836cab03c90375 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Wed, 18 Feb 2015 14:54:20 +0000
Subject: [PATCH] design with 4xQSFP and 24xBack 10GbE. Synthese OK
---
.../uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd | 10 +++++-----
.../libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd | 3 ++-
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 3fff3c144e..6704cc7938 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -49,7 +49,7 @@ ENTITY unb2_test IS
g_factory_image : BOOLEAN := FALSE;
g_nof_streams_qsfp : NATURAL := 4;--c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
g_nof_streams_ring : NATURAL := 0; --FIXME
- g_nof_streams_back : NATURAL := 4 --FIXME
+ g_nof_streams_back : NATURAL := 24 --FIXME
);
PORT (
-- GENERAL
@@ -74,9 +74,9 @@ ENTITY unb2_test IS
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
-- Transceiver clocks
- SA_CLK : IN STD_LOGIC; -- SerDes Clock 10GbE front and ring
- SB_CLK : IN STD_LOGIC; -- SerDes Clock 10GbE back
- BCK_REF_CLK : IN STD_LOGIC; --
+ SA_CLK : IN STD_LOGIC; -- Clock 10GbE front (qsfp) and ring lines
+ SB_CLK : IN STD_LOGIC; -- Clock 10GbE back upper 24 lines
+ BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
@@ -816,7 +816,7 @@ BEGIN
g_tx_fifo_size => c_def_10GbE_block_size*2
)
PORT MAP (
- tr_ref_clk => SB_CLK,
+ tr_ref_clk => BCK_REF_CLK,--SB_CLK,
-- MM interface
mm_rst => mm_rst,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
index 7acf5df20c..45c2bc2b81 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
@@ -72,7 +72,8 @@ PACKAGE unb2_board_pkg IS
END RECORD;
--CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 48, 3); -- per node: 1 bus with 48 channels
- CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 4, 3); -- per node: 1 bus with 48 channels
+ --CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 4, 3); -- per node: 1 bus with 48 channels
+ CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 24, 3); -- per node: 1 bus with 48 channels
CONSTANT c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
CONSTANT c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
CONSTANT c_unb2_board_tr_qsfp_nof_leds : NATURAL := c_unb2_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
--
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