From 6bb66c3da4cb924dac0fa2c7bef428d0ae94d1a2 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 21 May 2015 13:11:27 +0000
Subject: [PATCH] Move the unb2_board_clk_rst.vhd functionality to
unb2_board_node_ctrl.vhd. Rename sys_clk into mm_clk.
---
.../uniboard2/libraries/unb2_board/hdllib.cfg | 1 -
.../unb2_board/src/vhdl/ctrl_unb2_board.vhd | 24 +--
.../src/vhdl/unb2_board_node_ctrl.vhd | 154 ++++++++++++------
.../tb/vhdl/tb_unb2_board_node_ctrl.vhd | 32 ++--
4 files changed, 132 insertions(+), 79 deletions(-)
diff --git a/boards/uniboard2/libraries/unb2_board/hdllib.cfg b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
index 2f3f38074a..7adbbdd6a9 100644
--- a/boards/uniboard2/libraries/unb2_board/hdllib.cfg
+++ b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
@@ -10,7 +10,6 @@ synth_files =
src/vhdl/unb2_board_system_info.vhd
src/vhdl/unb2_board_system_info_reg.vhd
src/vhdl/mms_unb2_board_system_info.vhd
- src/vhdl/unb2_board_clk_rst.vhd
src/vhdl/unb2_board_clk200_pll.vhd
src/vhdl/unb2_board_clk25_pll.vhd
src/vhdl/unb2_board_clk125_pll.vhd
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 607b5c2a2d..191150b5fe 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -374,27 +374,29 @@ BEGIN
i_tse_clk <= i_xo_ethclk;
-
-
u_unb2_board_node_ctrl : ENTITY work.unb2_board_node_ctrl
GENERIC MAP (
g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
PORT MAP (
+ -- xo_clk domain
xo_clk => i_xo_ethclk,
xo_rst_n => i_xo_rst_n,
- sys_clk => i_mm_clk,
- sys_locked => i_mm_locked,
- sys_rst => i_mm_rst,
+ -- mm_clk domain
+ mm_clk => i_mm_clk,
+ mm_locked => i_mm_locked,
+ mm_rst => i_mm_rst,
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s, -- could be used to toggle a LED
+ -- cal_clk domain
cal_clk => '0',
cal_rst => OPEN,
+ -- st_clk domain
st_clk => node_ctrl_dp_clk_in,
- st_rst => node_ctrl_dp_rst_out,
- wdi_in => pout_wdi,
- wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- pulse_us => OPEN,
- pulse_ms => mm_pulse_ms,
- pulse_s => mm_pulse_s -- could be used to toggle a LED
+ st_rst => node_ctrl_dp_rst_out
);
-- System info
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
index a08bb216b0..22d7af8a8d 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -24,34 +24,43 @@ LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
--- Purpose:
--- Provide the basic node control along with an SOPC Builder system:
--- . sys_rst for sys_clk
--- . pulse every 1 us, 1 ms and 1 s
--- . extend WDI to avoid watchdog reset during SW reload
+-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
+-- Description:
+-- 1) Create xo_rst for xo_clk
+-- 2) Create mm_rst for mm_clk and also:
+-- . pulse every 1 us, 1 ms and 1 s
+-- . extend WDI to avoid watchdog reset during software reload
+-- 3) Use mm_rst to release other clock domain resets
ENTITY unb2_board_node_ctrl IS
GENERIC (
g_pulse_us : NATURAL := 125; -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
g_pulse_ms : NATURAL := 1000; -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
g_pulse_s : NATURAL := 1000; -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
- g_wdi_extend_w : NATURAL := 14 -- extend wdi by about 2**(14-1)= 8 s
+ g_wdi_extend_w : NATURAL := 14 -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
);
PORT (
- xo_clk : IN STD_LOGIC; -- from pin, also used as reference for the PLL in the SOPC design
- xo_rst_n : OUT STD_LOGIC; -- to SOPC design
- sys_clk : IN STD_LOGIC; -- system clock from PLL in SOPC design (= mm_clk)
- sys_locked : IN STD_LOGIC; -- system clock PLL locked from SOPC design
- sys_rst : OUT STD_LOGIC; -- system reset released after system clock PLL has locked (= mm_rst)
+ -- xo_clk domain
+ xo_clk : IN STD_LOGIC; -- from pin, may also be used as reference for the PLL in a SOPC design
+ xo_rst_n : OUT STD_LOGIC; -- XO reset to SOPC design
+
+ -- mm_clk domain
+ mm_clk : IN STD_LOGIC; -- MM clock
+ mm_locked : IN STD_LOGIC := '1'; -- MM clock PLL locked (or use default '1')
+ mm_rst : OUT STD_LOGIC; -- MM reset released after MM clock PLL has locked
+ mm_wdi_in : IN STD_LOGIC; -- from software running on the NIOS2 in the SOPC design
+ mm_wdi_out : OUT STD_LOGIC; -- to FPGA pin
+ mm_pulse_us : OUT STD_LOGIC; -- pulses every us
+ mm_pulse_ms : OUT STD_LOGIC; -- pulses every ms
+ mm_pulse_s : OUT STD_LOGIC; -- pulses every s
+
+ -- cal_clk domain
cal_clk : IN STD_LOGIC := '0'; -- calibration or configuration interface clock
- cal_rst : OUT STD_LOGIC; -- calibration or configuration interface reset, released after sys_rst is released
+ cal_rst : OUT STD_LOGIC; -- calibration or configuration interface reset, released after mm_rst is released
+
+ -- st_clk domain
st_clk : IN STD_LOGIC := '0'; -- streaming interface clock
- st_rst : OUT STD_LOGIC; -- streaming interface reset, released after sys_rst is released
- wdi_in : IN STD_LOGIC; -- from SW running on the NIOS2 in the SOPC design
- wdi_out : OUT STD_LOGIC; -- to FPGA pin
- pulse_us : OUT STD_LOGIC; -- pulses every us
- pulse_ms : OUT STD_LOGIC; -- pulses every ms
- pulse_s : OUT STD_LOGIC -- pulses every s
+ st_rst : OUT STD_LOGIC -- streaming interface reset, released after mm_rst is released
);
END unb2_board_node_ctrl;
@@ -60,46 +69,55 @@ ARCHITECTURE str OF unb2_board_node_ctrl IS
CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
- SIGNAL i_sys_rst : STD_LOGIC;
- SIGNAL i_pulse_ms : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC; -- initial reset released after some XO clock cycles
+ SIGNAL mm_locked_n : STD_LOGIC;
+ SIGNAL i_mm_rst : STD_LOGIC;
+ SIGNAL i_mm_pulse_ms : STD_LOGIC;
BEGIN
- sys_rst <= i_sys_rst;
+ ----------------------------------------------------------------------------
+ -- xo_clk domain
+ ----------------------------------------------------------------------------
- pulse_ms <= i_pulse_ms;
+ -- Create xo_rst reset in xo_clk domain after fixed delay
+ xo_rst_n <= NOT xo_rst;
- u_unb2_board_clk_rst : ENTITY work.unb2_board_clk_rst
- PORT MAP (
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => i_sys_rst -- release reset some clock cycles after sys_locked went high
- );
-
- u_common_areset_cal : ENTITY common_lib.common_areset
+ u_common_areset_xo : ENTITY common_lib.common_areset
GENERIC MAP (
- g_rst_level => '1',
+ g_rst_level => '1', -- power up default will be inferred in FPGA
g_delay_len => c_reset_len
)
PORT MAP (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
- clk => cal_clk,
- out_rst => cal_rst
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
);
- u_common_areset_st : ENTITY common_lib.common_areset
+
+ ----------------------------------------------------------------------------
+ -- mm_clk domain
+ ----------------------------------------------------------------------------
+
+ -- Create mm_rst reset in mm_clk domain based on mm_locked
+ mm_rst <= i_mm_rst;
+
+ mm_locked_n <= NOT mm_locked;
+
+ u_common_areset_mm : ENTITY common_lib.common_areset
GENERIC MAP (
- g_rst_level => '1',
+ g_rst_level => '1', -- power up default will be inferred in FPGA
g_delay_len => c_reset_len
)
PORT MAP (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
- clk => st_clk,
- out_rst => st_rst
- );
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
+ -- Create 1 pulse per us, per ms and per s
+ mm_pulse_ms <= i_mm_pulse_ms;
+
u_common_pulser_us_ms_s : ENTITY common_lib.common_pulser_us_ms_s
GENERIC MAP (
g_pulse_us => g_pulse_us,
@@ -107,23 +125,55 @@ BEGIN
g_pulse_s => g_pulse_s
)
PORT MAP (
- rst => i_sys_rst,
- clk => sys_clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => pulse_s
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
);
+ -- Toggle the WDI every 1 ms
u_unb2_board_wdi_extend : ENTITY work.unb2_board_wdi_extend
GENERIC MAP (
g_extend_w => g_wdi_extend_w
)
PORT MAP (
- rst => i_sys_rst,
- clk => sys_clk,
- pulse_ms => i_pulse_ms,
- wdi_in => wdi_in,
- wdi_out => wdi_out
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
+
+
+ ----------------------------------------------------------------------------
+ -- cal_clk domain
+ ----------------------------------------------------------------------------
+
+ u_common_areset_cal : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => cal_clk,
+ out_rst => cal_rst
);
+ ----------------------------------------------------------------------------
+ -- st_clk domain
+ ----------------------------------------------------------------------------
+
+ u_common_areset_st : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => st_clk,
+ out_rst => st_rst
+ );
+
END str;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index f39bf1acb5..1e95c283cc 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -34,8 +34,8 @@ ARCHITECTURE tb OF tb_unb2_board_node_ctrl IS
CONSTANT c_scale : NATURAL := 100; -- scale to speed up simulation
CONSTANT c_xo_clk_period : TIME := 1 us; -- 1 MHz XO, slow XO to speed up simulation
- CONSTANT c_sys_clk_period : TIME := c_xo_clk_period/5; -- 5 MHz PLL output from XO reference
- CONSTANT c_sys_locked_time : TIME := 10 us;
+ CONSTANT c_mm_clk_period : TIME := c_xo_clk_period/5; -- 5 MHz PLL output from XO reference
+ CONSTANT c_mm_locked_time : TIME := 10 us;
CONSTANT c_pulse_us : NATURAL := 5; -- nof 5 MHz clk cycles to get us period
CONSTANT c_pulse_ms : NATURAL := 1000/c_scale; -- nof pulse_us pulses to get ms period
@@ -52,9 +52,9 @@ ARCHITECTURE tb OF tb_unb2_board_node_ctrl IS
SIGNAL xo_clk : STD_LOGIC := '0';
SIGNAL xo_rst_n : STD_LOGIC;
- SIGNAL sys_clk : STD_LOGIC := '0';
- SIGNAL sys_locked : STD_LOGIC := '0';
- SIGNAL sys_rst : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC := '0';
+ SIGNAL mm_locked : STD_LOGIC := '0';
+ SIGNAL mm_rst : STD_LOGIC;
SIGNAL wdi : STD_LOGIC := '0';
SIGNAL wdi_in : STD_LOGIC;
@@ -72,8 +72,8 @@ BEGIN
xo_clk <= NOT xo_clk AFTER c_xo_clk_period/2;
- sys_clk <= NOT sys_clk AFTER c_sys_clk_period/2;
- sys_locked <= '0', '1' AFTER c_sys_locked_time;
+ mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
+ mm_locked <= '0', '1' AFTER c_mm_locked_time;
wdi <= NOT wdi AFTER c_wdi_period/c_scale; -- wd interrupt
sw <= NOT sw AFTER c_sw_period/c_scale; -- sw active / reload
@@ -88,16 +88,18 @@ BEGIN
g_wdi_extend_w => c_wdi_extend_w
)
PORT MAP (
+ -- xo_clk domain
xo_clk => xo_clk,
xo_rst_n => xo_rst_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => sys_rst,
- wdi_in => wdi_in,
- wdi_out => wdi_out,
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s
+ -- mm_clk domain
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
);
END tb;
--
GitLab