diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
index 4568aee466e37a76240a0701df64a9de8650319a..b1212614046a9bc1491c10d7e1fa6c4c74394290 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
@@ -42,6 +42,8 @@ qsys-generate ip_arria10_e1sg_ddr4_8g_2400.qsys \
               --simulation=VHDL \
               --output-directory=generated \
               --allow-mixed-language-simulation
+# the generated map is not named generated, dispite the output-directory parameter is set to generated.
+mv ip_arria10_e1sg_ddr4_8g_2400 generated
               
 # Also generate the testbench IP, this is not useful because it only generates bus functional models, so not a  DDR4 memory model
 #qsys-generate ip_arria10_e1sg_ddr4_8g_2400.qsys \