diff --git a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
index 94afd7a102363deeda6454d343458bcae30b9ffb..11d7c598bd7ffb73861a2dc95bcab76ce8f5393e 100644
--- a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
+++ b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
@@ -27,7 +27,9 @@
-- g_wideband_big_endian=TRUE sthe first sample is in the MS symbol.
-- Remark:
-- . Only for simulation.
-
+-- . When g_use_sclk=TRUE then the input SCLK is used. Else the SCLK is derived
+-- from the DCLK so that it does not have to be applied via an input. This
+-- eases the use of this scope within a design.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -36,14 +38,18 @@ USE work.common_pkg.ALL;
ENTITY common_wideband_data_scope IS
GENERIC (
g_sim : BOOLEAN := FALSE;
+ g_use_sclk : BOOLEAN := TRUE;
g_wideband_factor : NATURAL := 4; -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
g_wideband_big_endian : BOOLEAN := TRUE; -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
g_dat_w : NATURAL := 8 -- Actual width of the data samples
);
PORT (
- -- Sample clock
- SCLK : IN STD_LOGIC := '0'; -- sample clk, use only for simulation purposes
+ -- Digital processing clk
+ DCLK : IN STD_LOGIC := '0';
+ -- Sampling clk, for simulation only
+ SCLK : IN STD_LOGIC := '0'; -- SCLK rate = g_wideband_factor * DCLK rate
+
-- Streaming input data
in_data : IN STD_LOGIC_VECTOR(g_wideband_factor*g_dat_w-1 DOWNTO 0);
in_val : IN STD_LOGIC;
@@ -58,17 +64,25 @@ END common_wideband_data_scope;
ARCHITECTURE beh OF common_wideband_data_scope IS
+ SIGNAL SCLKi : STD_LOGIC; -- sampling clk, for simulation only
SIGNAL scope_cnt : NATURAL;
SIGNAL scope_dat : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
BEGIN
sim_only : IF g_sim=TRUE GENERATE
+ use_sclk : IF g_use_sclk=TRUE GENERATE
+ SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
+ END GENERATE;
+ gen_sclk : IF g_use_sclk=FALSE GENERATE
+ proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
+ END GENERATE;
+
-- View in_data at the sample rate using out_dat
- p_scope_dat : PROCESS(SCLK)
+ p_scope_dat : PROCESS(SCLKi)
VARIABLE vI : NATURAL;
BEGIN
- IF rising_edge(SCLK) THEN
+ IF rising_edge(SCLKi) THEN
IF g_wideband_big_endian=TRUE THEN
vI := g_wideband_factor-1-scope_cnt;
ELSE
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
index 35445bb7df7bdc247130b48ae4872a7bea4f3fd2..342f0d94a7ab94119149fa7395c97827a3a785b1 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
@@ -30,26 +30,45 @@
-- Window to observe the signal shape at the SCLK sample rate.
-- Remark:
-- . Only for simulation.
+-- . When g_use_sclk=TRUE then the input SCLK is used. Else the SCLK is derived
+-- from the DCLK so that it does not have to be applied via an input. This
+-- eases the use of this scope within a design.
-- . The concatenated parallel data width is g_wideband_factor * g_dat_w and
--- must fit the sosi.data, re, im fields.
+-- must fit the sosi.data, re, im fields. Therefor use g_complex to avoid
+-- out of range failure on re, im in case data has too large g_dat_w to also
+-- fit for re, im, which can happen because c_dp_stream_data_w >>
+-- c_dp_stream_dsp_data_w.
+-- . In this dp_wideband_sp_arr_scope the input is one or more wideband streams
+-- and the input sosi array has size g_nof_streams, so the wideband data is
+-- carried by g_wideband_factor concatenated symbols in the data field or in
+-- the (re, im) fields.
+-- In dp_wideband_wb_arr_scope the input is only one wideband stream
+-- and the input sosi array has size g_wideband_factor, so there the wideband
+-- data is carried via the sosi array dimension.
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
ENTITY dp_wideband_sp_arr_scope IS
GENERIC (
g_sim : BOOLEAN := FALSE;
+ g_use_sclk : BOOLEAN := TRUE;
+ g_complex : BOOLEAN := FALSE;
g_nof_streams : NATURAL := 4;
g_wideband_factor : NATURAL := 4; -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
g_wideband_big_endian : BOOLEAN := FALSE; -- When true sp_sosi_arr[].data[3:0] = sample[t0,t1,t2,t3], else when false : sp_sosi_arr[].data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w : NATURAL := 8 -- Actual width of the data field or of the re field, im field
+ g_dat_w : NATURAL := 8 -- Actual g_dat_w width of the data field or g_dat_w/2 width in case of the re field, im field
);
PORT (
- -- Sample clock
- SCLK : IN STD_LOGIC := '0'; -- sample clk, use only for simulation purposes
+ -- Digital processing clk
+ DCLK : IN STD_LOGIC := '0';
+
+ -- Sampling clk, for simulation only
+ SCLK : IN STD_LOGIC := '0'; -- SCLK rate = g_wideband_factor * DCLK rate
-- Streaming input samples for g_nof_streams
sp_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- = [3:0] = Signal Paths [D,C,B,A]
@@ -62,18 +81,26 @@ END dp_wideband_sp_arr_scope;
ARCHITECTURE beh OF dp_wideband_sp_arr_scope IS
+ SIGNAL SCLKi : STD_LOGIC; -- sampling clk, for simulation only
SIGNAL scope_cnt_arr : t_natural_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL st_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
BEGIN
sim_only : IF g_sim=TRUE GENERATE
+ use_sclk : IF g_use_sclk=TRUE GENERATE
+ SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
+ END GENERATE;
+ gen_sclk : IF g_use_sclk=FALSE GENERATE
+ proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
+ END GENERATE;
+
-- View sp_sosi_arr at the sample rate using st_sosi_arr
gen_arr : FOR I IN 0 TO g_nof_streams-1 GENERATE
- p_st_sosi_arr : PROCESS(SCLK)
+ p_st_sosi_arr : PROCESS(SCLKi)
VARIABLE vI : NATURAL;
BEGIN
- IF rising_edge(SCLK) THEN
+ IF rising_edge(SCLKi) THEN
IF g_wideband_big_endian=TRUE THEN
vI := g_wideband_factor-1-scope_cnt_arr(I);
ELSE
@@ -83,14 +110,20 @@ BEGIN
IF sp_sosi_arr(I).valid='1' AND scope_cnt_arr(I) < g_wideband_factor-1 THEN
scope_cnt_arr(I) <= scope_cnt_arr(I) + 1;
END IF;
- st_sosi_arr(I) <= sp_sosi_arr(I);
- st_sosi_arr(I).data <= RESIZE_DP_SDATA( sp_sosi_arr(I).data((g_wideband_factor-vI)*g_dat_w-1 DOWNTO (g_wideband_factor-vI-1)*g_dat_w));
- -- Set unused sp_sosi_arr(I) fields to 0 to avoid Warning: NUMERIC_STD.TO_INTEGER: metavalue detected within func_dp_stream_slv_to_integer()
+ st_sosi_arr(I) <= sp_sosi_arr(I);
+ -- Default set unused sp_sosi_arr(I) fields to 0 to avoid Warning: NUMERIC_STD.TO_INTEGER: metavalue detected within func_dp_stream_slv_to_integer()
+ st_sosi_arr(I).data <= (OTHERS=>'0');
st_sosi_arr(I).re <= (OTHERS=>'0');
st_sosi_arr(I).im <= (OTHERS=>'0');
st_sosi_arr(I).empty <= (OTHERS=>'0');
st_sosi_arr(I).channel <= (OTHERS=>'0');
st_sosi_arr(I).err <= (OTHERS=>'0');
+ IF g_complex THEN
+ st_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(sp_sosi_arr(I).re((g_wideband_factor-vI)*g_dat_w-1 DOWNTO (g_wideband_factor-vI-1)*g_dat_w));
+ st_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(sp_sosi_arr(I).im((g_wideband_factor-vI)*g_dat_w-1 DOWNTO (g_wideband_factor-vI-1)*g_dat_w));
+ ELSE
+ st_sosi_arr(I).data <= RESIZE_DP_SDATA(sp_sosi_arr(I).data((g_wideband_factor-vI)*g_dat_w-1 DOWNTO (g_wideband_factor-vI-1)*g_dat_w));
+ END IF;
END IF;
END PROCESS;
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
index 8e240344192638432914e5de8bc0ed82f6e7b8b9..550737bde2d42f684696c8590edd6d0223754ae9 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
@@ -22,8 +22,22 @@
-- Purpose: Scope component to show the arrayed DP SOSI data at the SCLK
-- sample rate
-- Description:
+-- The SCLK rate is g_wideband_factor faster than the DCLK rate. The input
+-- is one wideband stream that is carried by an array of g_wideband_factor
+-- sosi streams at the DCLK rate. The output is a single sosi integer stream
+-- at the SCLK rate.
-- Remark:
-- . Only for simulation.
+-- . When g_use_sclk=TRUE then the input SCLK is used. Else the SCLK is derived
+-- from the DCLK so that it does not have to be applied via an input. This
+-- eases the use of this scope within a design.
+-- . In this dp_wideband_wb_arr_scope the input is only one wideband stream
+-- and the input sosi array has size g_wideband_factor, so the wideband
+-- data is carried via the sosi array dimension.
+-- In dp_wideband_sp_arr_scope the input is one or more wideband streams
+-- and the input sosi array has size g_nof_streams, so there the wideband
+-- data is carried by g_wideband_factor concatenated symbols in the data
+-- field or in the (re, im) fields.
LIBRARY IEEE, common_lib;
@@ -34,13 +48,17 @@ USE work.dp_stream_pkg.ALL;
ENTITY dp_wideband_wb_arr_scope IS
GENERIC (
g_sim : BOOLEAN := FALSE;
+ g_use_sclk : BOOLEAN := TRUE;
g_wideband_factor : NATURAL := 4; -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
g_wideband_big_endian : BOOLEAN := FALSE; -- When true wb_sosi_arr[3:0] = sample[t0,t1,t2,t3], else when false : wb_sosi_arr[3:0] = sample[t3,t2,t1,t0]
g_dat_w : NATURAL := 8 -- Actual width of the data field or of the re field, im field
);
PORT (
- -- Sample clock
- SCLK : IN STD_LOGIC := '0'; -- sample clk, use only for simulation purposes
+ -- Digital processing clk
+ DCLK : IN STD_LOGIC := '0';
+
+ -- Sampling clk, for simulation only
+ SCLK : IN STD_LOGIC := '0'; -- SCLK rate = g_wideband_factor * DCLK rate
-- Streaming input samples for one stream
wb_sosi_arr : IN t_dp_sosi_arr(g_wideband_factor-1 DOWNTO 0); -- = [3:0] = Signal Path time samples [t3,t2,t1,t0]
@@ -53,16 +71,24 @@ END dp_wideband_wb_arr_scope;
ARCHITECTURE beh OF dp_wideband_wb_arr_scope IS
+ SIGNAL SCLKi : STD_LOGIC; -- sampling clk, for simulation only
SIGNAL sample_cnt : NATURAL RANGE 0 TO g_wideband_factor-1 := 0;
SIGNAL st_sosi : t_dp_sosi;
BEGIN
sim_only : IF g_sim=TRUE GENERATE
+ use_sclk : IF g_use_sclk=TRUE GENERATE
+ SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
+ END GENERATE;
+ gen_sclk : IF g_use_sclk=FALSE GENERATE
+ proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
+ END GENERATE;
+
-- View wb_sosi_arr at the sample rate using st_sosi
- p_st_sosi : PROCESS(SCLK)
+ p_st_sosi : PROCESS(SCLKi)
BEGIN
- IF rising_edge(SCLK) THEN
+ IF rising_edge(SCLKi) THEN
IF g_wideband_big_endian=TRUE THEN
st_sosi <= wb_sosi_arr(g_wideband_factor-1-sample_cnt);
ELSE