diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 34a2c49f89a64e30918443ee012c44e85d40f1d5..fdead4ddbcbdaa5a5e5274ef6dbb2a49e688a1da 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -300,6 +300,7 @@ test_bench_files =
tb/vhdl/tb_tb_dp_block_validate_channel.vhd
tb/vhdl/tb_tb_dp_bsn_align.vhd
tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+ tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
tb/vhdl/tb_tb_dp_concat.vhd
@@ -357,7 +358,6 @@ regression_test_vhdl =
tb/vhdl/tb_dp_latency_adapter.vhd
tb/vhdl/tb_dp_shiftreg.vhd
tb/vhdl/tb_dp_bsn_source.vhd
- tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
tb/vhdl/tb_mms_dp_bsn_source.vhd
tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -372,6 +372,7 @@ regression_test_vhdl =
tb/vhdl/tb_tb_dp_block_from_mm.vhd
tb/vhdl/tb_tb_dp_block_validate_channel.vhd
tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+ tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
tb/vhdl/tb_tb_dp_concat.vhd
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index a7b2234a79a41c7fb71c5250e2a999c8d3cbb43e..d9fd975a4eb30877fd101260a963134aab754ba7 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -45,6 +45,9 @@ USE work.dp_stream_pkg.ALL;
USE work.tb_dp_pkg.ALL;
ENTITY tb_mmp_dp_bsn_align_v2 IS
+ GENERIC (
+ g_lost_input : BOOLEAN := TRUE -- when TRUE use c_nof_streams-1 as lost input
+ );
END tb_mmp_dp_bsn_align_v2;
@@ -60,11 +63,12 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
-- Fixed dut generics
-- . for dp_bsn_align_v2
- CONSTANT c_nof_streams : NATURAL := 3;
+ CONSTANT c_nof_streams : NATURAL := 5;
CONSTANT c_bsn_latency_max : NATURAL := 1;
CONSTANT c_nof_aligners_max : POSITIVE := 1; -- fixed in this tb
CONSTANT c_block_size : NATURAL := 11;
CONSTANT c_block_period : NATURAL := 11;
+ CONSTANT c_block_per_sync : NATURAL := 7;
CONSTANT c_bsn_w : NATURAL := c_dp_stream_bsn_w;
CONSTANT c_data_w : NATURAL := 16;
CONSTANT c_data_replacement_value : INTEGER := 17;
@@ -73,7 +77,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
CONSTANT c_pipeline_output : NATURAL := 1;
CONSTANT c_rd_latency : NATURAL := 2;
-- . for mms_dp_bsn_monitor_v2
- CONSTANT c_nof_clk_per_sync : NATURAL := 200*10**6;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_block_per_sync * c_block_period;
CONSTANT c_nof_input_bsn_monitors : NATURAL := c_nof_streams;
CONSTANT c_use_bsn_output_monitor : BOOLEAN := TRUE;
@@ -96,8 +100,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
CONSTANT c_bsn_init : NATURAL := 3;
CONSTANT c_channel_init : INTEGER := 0;
CONSTANT c_err_init : NATURAL := 247;
- CONSTANT c_sync_period : NATURAL := 7;
- CONSTANT c_sync_offset : NATURAL := 2;
+ CONSTANT c_sync_bsn_offset : NATURAL := 2;
CONSTANT c_gap_size : NATURAL := c_block_period - c_block_size;
-- DUT latency
@@ -138,8 +141,8 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
SIGNAL reg_output_monitor_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_output_monitor_cipo : t_mem_cipo;
- SIGNAL mon_latency_input_arr : t_nat_natural_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL mon_latency_output : NATURAL;
+ SIGNAL mon_latency_input_arr : t_integer_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL mon_latency_output : INTEGER;
-- DP clock domain
SIGNAL dp_clk : STD_LOGIC := '1';
@@ -173,7 +176,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
SIGNAL out_err_arr : t_err_arr;
SIGNAL verify_done_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL verify_done : STD_LOGIC;
+ SIGNAL verify_done : STD_LOGIC := '0';
SIGNAL hold_out_sop_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL expected_out_bsn_arr : t_bsn_arr;
@@ -257,15 +260,19 @@ BEGIN
FOR I IN 0 TO c_nof_streams-1 LOOP
proc_mem_mm_bus_rd(6 + I*c_reg_bsn_monitor_span, mm_clk, reg_input_monitor_cipo, reg_input_monitor_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- mon_latency_input_arr(I) <= TO_UINT(reg_input_monitor_cipo.rddata);
+ mon_latency_input_arr(I) <= TO_SINT(reg_input_monitor_cipo.rddata(31 DOWNTO 0));
proc_common_wait_some_cycles(mm_clk, 1);
- ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) SEVERITY ERROR;
+ IF g_lost_input = TRUE AND I = c_nof_streams-1 THEN
+ ASSERT mon_latency_input_arr(I) = -1 REPORT "Wrong input BSN monitor latency timeout for input " & int_to_str(I) SEVERITY ERROR;
+ ELSE
+ ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) SEVERITY ERROR;
+ END IF;
END LOOP;
-- Read output BSN monitor
proc_mem_mm_bus_rd(6, mm_clk, reg_output_monitor_cipo, reg_output_monitor_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- mon_latency_output <= TO_UINT(reg_output_monitor_cipo.rddata);
+ mon_latency_output <= TO_SINT(reg_output_monitor_cipo.rddata(31 DOWNTO 0));
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_latency_output = c_total_latency REPORT "Wrong output BSN monitor latency" SEVERITY ERROR;
@@ -299,14 +306,14 @@ BEGIN
FOR S IN 0 TO c_tb_nof_restart-1 LOOP
v_bsn := c_bsn_init;
FOR R IN 0 TO c_tb_nof_blocks-1 LOOP
- v_sync := sel_a_b(v_bsn MOD c_sync_period = c_sync_offset, '1', '0');
+ v_sync := sel_a_b(v_bsn MOD c_block_per_sync = c_sync_bsn_offset, '1', '0');
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, c_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), dp_clk, sl1, ref_siso_arr(I), ref_sosi_arr(I));
v_bsn := v_bsn + 1;
v_data := v_data + c_block_size;
proc_common_wait_some_cycles(dp_clk, c_gap_size); -- create gap between frames
END LOOP;
-- Create gap between restarts
- proc_common_wait_some_cycles(dp_clk, 100);
+ proc_common_wait_some_cycles(dp_clk, 10);
restart_cnt_arr(I) <= restart_cnt_arr(I) + 1;
END LOOP;
@@ -314,10 +321,15 @@ BEGIN
-- . default c_bsn_latency_max blocks remain in DUT buffer
expected_out_bsn_arr(I) <= TO_UVEC(v_bsn-1 - c_align_latency_nof_blocks, c_bsn_w);
expected_out_data_arr(I) <= TO_UVEC(v_data-1 - c_align_latency_nof_valid, c_data_w);
- -- . default no data is lost, so all channel(0) lost data flags are 0
+ -- . default no data is lost, so all channel(bit 0) lost data flags are 0
expected_out_channel_arr(I) <= TO_DP_CHANNEL(0);
-
- proc_common_wait_some_cycles(dp_clk, 100);
+ IF g_lost_input = TRUE THEN
+ IF I = c_nof_streams-1 THEN
+ expected_out_data_arr(I) <= TO_UVEC(c_data_replacement_value, c_data_w);
+ expected_out_channel_arr(I) <= TO_DP_CHANNEL(1);
+ END IF;
+ END IF;
+ proc_common_wait_some_cycles(dp_clk, 10);
verify_done_arr(I) <= '1';
proc_common_wait_some_cycles(dp_clk, 1);
verify_done_arr(I) <= '0';
@@ -329,15 +341,25 @@ BEGIN
END PROCESS;
END GENERATE;
- verify_done <= verify_done_arr(0);
+ verify_done <= '1' WHEN verify_done_arr(0) = '1';
restart_cnt <= restart_cnt_arr(0);
dp_end <= vector_and(dp_end_arr);
-- Model misalignment latency between the input streams to have different
-- input BSN monitor latencies
- gen_rx_sosi_arr : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE
- in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period;
+ no_lost_input : IF g_lost_input = FALSE GENERATE
+ gen_in_sosi_arr : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE
+ in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period;
+ END GENERATE;
+ END GENERATE;
+
+ one_lost_input : IF g_lost_input = TRUE GENERATE
+ -- Model missing enabled input stream at index c_lost_input = c_nof_streams-1
+ in_sosi_arr(c_nof_streams-1) <= c_dp_sosi_rst;
+ gen_in_sosi_arr : FOR I IN c_nof_streams-2 DOWNTO 0 GENERATE
+ in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period;
+ END GENERATE;
END GENERATE;
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7eea68cc3bdd53a99d18a3334f5df6d2a1fa3f16
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
@@ -0,0 +1,46 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+--
+-- Author: E. Kooistra, 2 march 2022
+-- Purpose: Regression multi tb for mmp_dp_bsn_align_v2
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE work.tb_dp_pkg.ALL;
+
+
+ENTITY tb_tb_mmp_dp_bsn_align_v2 IS
+END tb_tb_mmp_dp_bsn_align_v2;
+
+
+ARCHITECTURE tb OF tb_tb_mmp_dp_bsn_align_v2 IS
+
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+
+BEGIN
+
+ -- g_lost_input : BOOLEAN := FALSE
+
+ u_no_lost_input : ENTITY work.tb_mmp_dp_bsn_align_v2 GENERIC MAP (FALSE);
+ u_one_lost_input : ENTITY work.tb_mmp_dp_bsn_align_v2 GENERIC MAP (TRUE);
+
+END tb;