diff --git a/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd b/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd
index 0187277b3dd8fe7782e4fd1ef0907e32eab4ab6d..965564ea25c13c9cf8c3ca7feaf62bd5c7b1593b 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd
@@ -28,7 +28,7 @@ ENTITY st_histogram_8_april IS
END st_histogram_8_april;
-ARCHITECTURE str OF st_histogram_8_april IS
+ARCHITECTURE rtl OF st_histogram_8_april IS
CONSTANT c_adr_w : NATURAL := ceil_log2(g_nof_bins);
CONSTANT c_ram : t_c_mem := (latency => 1,
@@ -59,22 +59,25 @@ ARCHITECTURE str OF st_histogram_8_april IS
SIGNAL common_ram_r_w_0_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL init_phase : STD_LOGIC := '1';
- SIGNAL rd_cnt_allowed : STD_LOGIC := '0';
- SIGNAL rd_cnt_allowed_pp : STD_LOGIC := '0';
- SIGNAL nxt_rd_adr_cnt : NATURAL := 0;
- SIGNAL rd_adr_cnt : NATURAL;-- := 0;
- SIGNAL toggle_detect : STD_LOGIC := '0';
- SIGNAL toggle_detect_pp : STD_LOGIC;
- SIGNAL toggle_detect_false : STD_LOGIC := '1';
+ SIGNAL init_phase : STD_LOGIC := '1';
+ SIGNAL rd_cnt_allowed : STD_LOGIC := '0';
+ SIGNAL rd_cnt_allowed_pp : STD_LOGIC := '0';
+ SIGNAL nxt_rd_adr_cnt : NATURAL := 0;
+ SIGNAL rd_adr_cnt : NATURAL;-- := 0;
+ SIGNAL toggle_detect : STD_LOGIC := '0';
+ SIGNAL toggle_detect_pp : STD_LOGIC;
+ SIGNAL toggle_detect_false : STD_LOGIC := '1';
-- SIGNAL nxt_toggle_adr_cnt : NATURAL := 0;
-- SIGNAL toggle_adr_cnt : NATURAL;-- := 0;
- SIGNAL nxt_prev_wrdata : NATURAL;
- SIGNAL prev_wrdata : NATURAL;
- SIGNAL prev_prev_wrdata : NATURAL;
- SIGNAL sync_detect : STD_LOGIC := '0';
- SIGNAL sync_detect_ppp : STD_LOGIC;
+ SIGNAL nxt_prev_wrdata : NATURAL;
+ SIGNAL prev_wrdata : NATURAL;
+ SIGNAL prev_prev_wrdata : NATURAL;
+ SIGNAL prev_prev_prev_wrdata: NATURAL;
+ SIGNAL sync_detect : STD_LOGIC := '0';
+ SIGNAL sync_detect_pp : STD_LOGIC;
-- SIGNAL adr_w : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
+ SIGNAL same_r_w_address : STD_LOGIC;
+ SIGNAL same_r_w_address_pp : STD_LOGIC;
--pipelined signals
SIGNAL dp_pipeline_src_out_p : t_dp_sosi;
@@ -84,9 +87,10 @@ ARCHITECTURE str OF st_histogram_8_april IS
SIGNAL bin_reader_mosi_ppp : t_mem_mosi := c_mem_mosi_rst;
--debug signals
- SIGNAL nxt_dbg_sync_detect : STD_LOGIC;
- SIGNAL dbg_sync_detect : STD_LOGIC;
+-- SIGNAL nxt_dbg_sync_detect : STD_LOGIC;
+-- SIGNAL dbg_sync_detect : STD_LOGIC;
SIGNAL dbg_state_string : STRING(1 TO 3) := " ";
+ SIGNAL dbg_snk_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
BEGIN
@@ -126,8 +130,10 @@ BEGIN
src_out => dp_pipeline_src_out_pp
);
+ dbg_snk_data <= dp_pipeline_src_out_pp.data(g_in_data_w-1 DOWNTO 0);
+
toggle_detect_false <= '0' WHEN dp_pipeline_src_out_pp.sync = '1';
- sync_detect <= '1' WHEN (snk_in.sync='1' OR dp_pipeline_src_out_p.sync='1' OR dp_pipeline_src_out_pp.sync='1') ELSE '0';
+ sync_detect <= snk_in.valid WHEN (snk_in.sync='1' OR dp_pipeline_src_out_p.sync='1' OR dp_pipeline_src_out_pp.sync='1') ELSE '0';
-- u_dp_sync_detect_3_cycle : ENTITY dp_lib.dp_pipeline
-- GENERIC MAP (
@@ -140,14 +146,14 @@ BEGIN
-- src_out => sync_detect_ppp
-- );
- u_common_pipeline_sl_sync_detect_3_cycle : ENTITY common_lib.common_pipeline_sl
+ u_common_pipeline_sl_sync_detect_2_cycle : ENTITY common_lib.common_pipeline_sl
GENERIC MAP(
- g_pipeline => 3 -- 0 for wires, > 0 for registers,
+ g_pipeline => 2 -- 0 for wires, > 0 for registers,
)
PORT MAP (
clk => dp_clk,
in_dat => sync_detect,
- out_dat => sync_detect_ppp
+ out_dat => sync_detect_pp
);
--prev_bin_reader_mosi pipeline
@@ -216,7 +222,10 @@ BEGIN
-- src_out => bin_reader_mosi_pp
-- );
- rd_cnt_allowed <= snk_in.valid WHEN (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase = '0') ELSE '0'; -- AND snk_in.sync='0' <--
+-- rd_cnt_allowed <= snk_in.valid WHEN (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase = '0') ELSE '0'; -- AND snk_in.sync='0'
+ rd_cnt_allowed <= snk_in.valid WHEN ( bin_reader_mosi.address = prev_bin_reader_mosi.address AND ( (dp_pipeline_src_out_p.sync='1' AND dp_pipeline_src_out_p.valid='1') OR (dp_pipeline_src_out_pp.sync='1' AND dp_pipeline_src_out_p.valid='1') ) )
+ ELSE snk_in.valid WHEN (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase='0' AND snk_in.sync='0')
+ ELSE '0';
--rd_cnt_allowed_pp pipeline
u_common_pipeline_sl_rd_cnt_allowed : ENTITY common_lib.common_pipeline_sl
@@ -229,7 +238,7 @@ BEGIN
out_dat => rd_cnt_allowed_pp
);
- toggle_detect <= '1' WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0') ELSE '0'; --AND (snk_in.sync='0' OR dp_pipeline_src_out_p.sync='0')
+ toggle_detect <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0') ELSE '0'; --AND (snk_in.sync='0' OR dp_pipeline_src_out_p.sync='0')
u_common_pipeline_sl_toggle_detect : ENTITY common_lib.common_pipeline_sl
GENERIC MAP(
@@ -240,18 +249,32 @@ BEGIN
in_dat => toggle_detect,
out_dat => toggle_detect_pp
);
+
+ same_r_w_address <= snk_in.valid WHEN (bin_reader_mosi.address = bin_reader_mosi_ppp.address AND init_phase = '0' AND sync_detect = '0') ELSE '0';
+
+ u_common_pipeline_sl_same_r_w_address : ENTITY common_lib.common_pipeline_sl
+ GENERIC MAP(
+ g_pipeline => 2 -- 0 for wires, > 0 for registers,
+ )
+ PORT MAP (
+ clk => dp_clk,
+ in_dat => same_r_w_address,
+ out_dat => same_r_w_address_pp
+ );
-----------------------------------------------------------------------------
-- Bin writer : increments current bin value and sets up write request
+ -- . in : dp_pipeline_src_out_pp (latency: 2)
-- . in : toggle_detect_pp (latency: 2)
+ -- . in : same_r_w_address_pp (latency: 2)
-- . in : bin_reader_mosi_pp (latency: 2)
-- . in : common_ram_r_w_0_miso (latency: 2)
-- . in : rd_cnt_allowed_pp (latency: 2)
-- . out : bin_writer_mosi (latency: 3)
-----------------------------------------------------------------------------
p_nxt_bin_writer_mosi : PROCESS(common_ram_r_w_0_miso, common_ram_r_w_0_miso.rdval, common_ram_r_w_0_miso.rddata,
- bin_reader_mosi_pp.address, toggle_detect, rd_cnt_allowed_pp, rd_adr_cnt, init_phase, prev_wrdata, prev_prev_wrdata, sync_detect_ppp) IS
+ bin_reader_mosi_pp.address, toggle_detect, rd_cnt_allowed_pp, rd_adr_cnt, init_phase, prev_wrdata, prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp, dp_pipeline_src_out_pp.valid) IS
BEGIN
nxt_bin_writer_mosi <= c_mem_mosi_rst;
dbg_state_string <= "unv";
@@ -286,18 +309,24 @@ BEGIN
-- END IF;
nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- ELSIF sync_detect_ppp = '1' THEN -- snk_in.sync at least -- good as it is!
+ ELSIF sync_detect_pp = '1' THEN -- snk_in.sync at least -- good as it is!
nxt_bin_writer_mosi.wr <= '1';
nxt_bin_writer_mosi.wrdata <= TO_UVEC(1, c_mem_data_w); -- snk_in.sync: 1; dp_pipeline_src_out_p.sync (thus new adress): 1; dp_pipeline_src_out_pp.sync (thus new adress): 1
nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
-- nxt_rd_adr_cnt <= 0; -- really necessary ??
nxt_prev_wrdata <= 1;
- nxt_dbg_sync_detect <= '1';
dbg_state_string <= "sd ";
+
+ ELSIF same_r_w_address_pp = '1' THEN
+ nxt_bin_writer_mosi.wr <= '1';
+ nxt_bin_writer_mosi.wrdata <= TO_UVEC( (prev_prev_prev_wrdata+1), c_mem_data_w);
+ nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
+ nxt_prev_wrdata <= prev_prev_prev_wrdata + 1;
+ dbg_state_string <= "srw";
END IF;
END PROCESS;
- p_bin_writer_mosi : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi, nxt_rd_adr_cnt, nxt_prev_wrdata) IS
+ p_bin_writer_mosi : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi, nxt_rd_adr_cnt, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata) IS
BEGIN
IF dp_rst = '1' THEN
bin_writer_mosi <= c_mem_mosi_rst;
@@ -307,17 +336,9 @@ BEGIN
-- toggle_adr_cnt <= nxt_toggle_adr_cnt;
prev_wrdata <= nxt_prev_wrdata;
prev_prev_wrdata<= prev_wrdata;
+ prev_prev_prev_wrdata <= prev_prev_wrdata;
END IF;
END PROCESS;
-
- -- . Compare adress with the two previous adresses and if:
- -- . it is the same as the last adress increase a counter
- -- . it is the same as 2 cycles back but not the last copy the data to be
- -- written directly into the counter instead of trying to read (ask) it
- -- back from RAM at the same clock cycle (which is impossible)
- -- . it is not the same enable the nxt_wr_dat data to be written
- -- at the next cycle by making nxt_wr_en high
- -- . Write the wr_dat data to the RAM
-----------------------------------------------------------------------------
@@ -371,16 +392,8 @@ BEGIN
rd_dat => common_ram_r_w_0_miso.rddata(c_word_w-1 DOWNTO 0),
rd_val => common_ram_r_w_0_miso.rdval
);
-
- p_debug : PROCESS(nxt_dbg_sync_detect) IS
- BEGIN
- dbg_sync_detect <= '0';
- IF nxt_dbg_sync_detect = '1' THEN
- dbg_sync_detect <= '1';
- END IF;
- END PROCESS;
-END str;
+END rtl;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index fb30c07cefe887e04dd57290e1cca086b4bee8d3..e997850df3698990fdbd06a4a0badc7598ac386b 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -60,7 +60,7 @@ ENTITY tb_st_histogram IS
g_nof_data : NATURAL := 200;
--g_str : STRING := "freq.density";
g_valid_gap : BOOLEAN := TRUE;
- g_snk_in_data_sim_type : STRING := "mix" -- "counter" or "toggle" or "mix"
+ g_snk_in_data_sim_type : STRING := "counter" -- "counter" or "toggle" or "same rw" or "mix"
);
END tb_st_histogram;
@@ -81,6 +81,16 @@ ARCHITECTURE tb OF tb_st_histogram IS
SIGNAL toggle_start : STD_LOGIC := '0';
+ ----------------------------------------------------------------------------
+ -- Same read write test stimuli
+ ----------------------------------------------------------------------------
+ TYPE t_srw_arr IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+ CONSTANT c_srw_arr : t_srw_arr := (0,0,1,1,0,0,1,2,3, 1, 2, 3, 0, 3, 3, 0, 3);
+ -- 1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17
+
+ SIGNAL srw_index_cnt : NATURAL := 0;
+
+
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
@@ -149,6 +159,18 @@ BEGIN
END IF;
END IF;
+ ELSIF g_snk_in_data_sim_type = "same rw" THEN
+ IF dp_rst='1' THEN
+ st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
+ ELSIF rising_edge(dp_clk) AND pre_valid='1' THEN -- AND init_phase='0' didn't work
+ st_histogram_snk_in.data(g_data_w-1 DOWNTO c_adr_low) <= TO_UVEC(c_srw_arr(srw_index_cnt), c_adr_w); --placeholder !
+ IF srw_index_cnt = c_srw_arr'LENGTH -1 THEN
+ srw_index_cnt <= 0;
+ ELSE
+ srw_index_cnt <= srw_index_cnt+1;
+ END IF;
+ END IF;
+
ELSIF g_snk_in_data_sim_type = "mix" THEN
IF toggle_start = '1' THEN
-- toggle part