diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 893ab100f77ed319405490aa93d2a20ccec3ef4f..63e45046f638594a25f35eb2bb9e44c522d000a4 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -48,7 +48,7 @@ ENTITY tb_io_ddr IS
     g_tech_ddr3             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
     g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
     g_tb_end                : BOOLEAN := TRUE;   -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-    g_sim                   : BOOLEAN := TRUE;   -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
+    g_sim                   : BOOLEAN := FALSE;   -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
     g_cross_domain_dvr_ctlr : BOOLEAN := FALSE;  -- when TRUE insert clock cross domain logic
     g_ctlr_ref_clk_period   : TIME := 5000 ps;   -- 200 MHz
     g_dvr_clk_period        : TIME := 5000 ps;   -- 50 MHz
@@ -447,6 +447,7 @@ BEGIN
   external_ddr_memory_model : IF g_sim=FALSE GENERATE
     u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
     GENERIC MAP (
+      g_sim      => TRUE,
       g_tech_ddr => c_tech_ddr
     )
     PORT MAP (