From 6962042b45f6dbb9979fadcbe4f7785ef71712b9 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 12 Jun 2018 06:54:02 +0000
Subject: [PATCH] Change comment simulation end.
---
.../tb_apertif_unb1_correlator_full.vhd | 4 +++-
.../tb_apertif_unb1_fn_beamformer_trans.vhd | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/tb_apertif_unb1_correlator_full.vhd b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/tb_apertif_unb1_correlator_full.vhd
index 7fac3f0c0c..93a081eaec 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/tb_apertif_unb1_correlator_full.vhd
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/tb_apertif_unb1_correlator_full.vhd
@@ -162,7 +162,9 @@ BEGIN
FN_BN_3_TX => fn_bn_3_tx
);
- -- Check that design can simulate some us without error
+ ------------------------------------------------------------------------------
+ -- Simulation end
+ ------------------------------------------------------------------------------
sim_done <= '0', '1' AFTER 1 us;
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/tb_apertif_unb1_fn_beamformer_trans.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/tb_apertif_unb1_fn_beamformer_trans.vhd
index 4794877cbd..e288e6fd36 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/tb_apertif_unb1_fn_beamformer_trans.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/tb_apertif_unb1_fn_beamformer_trans.vhd
@@ -180,7 +180,7 @@ BEGIN
);
------------------------------------------------------------------------------
- -- Check that design can simulate some us without error
+ -- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' AFTER 1 us;
--
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