From 688908ca8074031954a78b7f8d2d3172c1684e5d Mon Sep 17 00:00:00 2001
From: Gijs <schoonderbeek@astron.nl>
Date: Thu, 9 Feb 2023 14:46:22 +0100
Subject: [PATCH] First version, have to double check on HW.
---
boards/uniboard2c/lattice_jtag/Strategy1.sty | 205 +++++++++++++++
.../lattice_jtag/UNB2_JTAG_SCANBRIDGE.ldf | 23 ++
.../lattice_jtag/UNB2_JTAG_SCANBRIDGE.lpf | 2 +
.../UNB2_JTAG_SCANBRIDGE/JTAG.lpf | 114 +++++++++
.../UNB2_JTAG_SCANBRIDGE/UNB2_JTAG.ddt | 18 ++
.../UNB2_JTAG_SCANBRIDGE.xcf | 48 ++++
.../UNB2_JTAG_SCANBRIDGE/JTAG.lpf | 114 +++++++++
.../source/.jtag_top(str).vhd.swp | Bin 0 -> 16384 bytes
.../source/bscan2_8port_top.vhd | 134 ++++++++++
.../source/jtag_top - Copy.vhd | 28 ++
.../source/jtag_top(str) - Copy.vhd | 242 ++++++++++++++++++
.../source/jtag_top(str).vhd | 154 +++++++++++
.../UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd | 28 ++
.../UNB2_JTAG_SCANBRIDGE/top_linker.ngo | Bin 0 -> 69022 bytes
.../source/.jtag_top(str).vhd.swp | Bin 0 -> 16384 bytes
.../source/bscan2_8port_top.vhd | 134 ++++++++++
.../source/jtag_top - Copy.vhd | 28 ++
.../source/jtag_top(str) - Copy.vhd | 242 ++++++++++++++++++
.../source/jtag_top(str).vhd | 154 +++++++++++
.../UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd | 28 ++
.../UNB2_JTAG_SCANBRIDGE/top_linker.ngo | Bin 0 -> 69022 bytes
boards/uniboard2c/lattice_jtag/readme.txt | 44 ++++
boards/uniboard2c/lettuce_jtag/readme.txt | 1 -
23 files changed, 1740 insertions(+), 1 deletion(-)
create mode 100644 boards/uniboard2c/lattice_jtag/Strategy1.sty
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE.ldf
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE.lpf
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/JTAG.lpf
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG.ddt
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE.xcf
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/JTAG.lpf
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/.jtag_top(str).vhd.swp
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top - Copy.vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str) - Copy.vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/top_linker.ngo
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/.jtag_top(str).vhd.swp
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top - Copy.vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str) - Copy.vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
create mode 100644 boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/top_linker.ngo
create mode 100644 boards/uniboard2c/lattice_jtag/readme.txt
delete mode 100644 boards/uniboard2c/lettuce_jtag/readme.txt
diff --git a/boards/uniboard2c/lattice_jtag/Strategy1.sty b/boards/uniboard2c/lattice_jtag/Strategy1.sty
new file mode 100644
index 0000000000..feec63c1a5
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/Strategy1.sty
@@ -0,0 +1,205 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+ <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
+ <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+ <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+ <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+ <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+ <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+ <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
+ <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+ <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+ <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
+ <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+ <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+ <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+ <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
+ <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+ <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+ <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+ <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+ <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+ <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+ <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+ <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+ <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+ <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+ <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+ <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+ <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+ <Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
+ <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+ <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
+ <Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
+ <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+ <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+ <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+ <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+ <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+ <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+ <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+ <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
+ <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+ <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+ <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+ <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
+ <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
+ <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
+ <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
+ <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+ <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+ <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+ <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+ <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+ <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+ <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
+ <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+ <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+ <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+ <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
+ <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
+ <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+ <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+ <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+ <Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
+ <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+ <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+ <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+ <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+ <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+ <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
+ <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
+ <Property name="PROP_LST_UseLPF" value="True" time="0"/>
+ <Property name="PROP_LST_VHDL2008" value="False" time="0"/>
+ <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+ <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+ <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
+ <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+ <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
+ <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+ <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+ <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+ <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
+ <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
+ <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+ <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+ <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
+ <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+ <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+ <Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
+ <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+ <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
+ <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
+ <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
+ <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+ <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+ <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+ <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+ <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+ <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+ <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
+ <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+ <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+ <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+ <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+ <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+ <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+ <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
+ <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+ <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+ <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
+ <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+ <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+ <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+ <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+ <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+ <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
+ <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+ <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+ <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+ <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+ <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+ <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+ <Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
+ <Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
+ <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+ <Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
+ <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+ <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+ <Property name="PROP_PAR_parHold" value="On" time="0"/>
+ <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+ <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+ <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+ <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+ <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+ <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+ <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+ <Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
+ <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+ <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+ <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+ <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+ <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+ <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+ <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+ <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
+ <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+ <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+ <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+ <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+ <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+ <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+ <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
+ <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+ <Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+ <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+ <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
+ <Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
+ <Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
+ <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
+ <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
+ <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+ <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
+ <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
+ <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+ <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+ <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
+ <Property name="PROP_SYN_LibPath" value="" time="0"/>
+ <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
+ <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+ <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
+ <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+ <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
+ <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+ <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+ <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+ <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+ <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+ <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+ <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+ <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
+ <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+ <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
+ <Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
+</Strategy>
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE.ldf b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE.ldf
new file mode 100644
index 0000000000..2209c754d8
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE.ldf
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="UNB2_JTAG_SCANBRIDGE" device="LCMXO2-640HC-5TG100C" default_implementation="UNB2_JTAG_SCANBRIDGE">
+ <Options/>
+ <Implementation title="UNB2_JTAG_SCANBRIDGE" dir="UNB2_JTAG_SCANBRIDGE" description="UNB2_JTAG_SCANBRIDGE" synthesis="synplify" default_strategy="Strategy1">
+ <Options def_top="jtag_top"/>
+ <Source name="UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="jtag_top"/>
+ </Source>
+ <Source name="UNB2_JTAG_SCANBRIDGE/JTAG.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+ <Source name="UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE.xcf" type="Programming Project File" type_short="Programming">
+ <Options/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="Strategy1.sty"/>
+</BaliProject>
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE.lpf b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE.lpf
new file mode 100644
index 0000000000..325063a977
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE.lpf
@@ -0,0 +1,2 @@
+BLOCK RESETPATHS;
+BLOCK ASYNCPATHS;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/JTAG.lpf b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/JTAG.lpf
new file mode 100644
index 0000000000..6a7b606cfb
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/JTAG.lpf
@@ -0,0 +1,114 @@
+LOCATE COMP "CTRL_0" SITE "10" ;
+LOCATE COMP "CTRL_1" SITE "9" ;
+LOCATE COMP "ENABLE_MSP" SITE "8" ;
+LOCATE COMP "IDN_0" SITE "99" ;
+LOCATE COMP "IDN_1" SITE "98" ;
+LOCATE COMP "IDN_2" SITE "97" ;
+LOCATE COMP "IDN_3" SITE "96" ;
+LOCATE COMP "LPSEL_0" SITE "18" ;
+LOCATE COMP "LPSEL_1" SITE "17" ;
+LOCATE COMP "LPSEL_2" SITE "16" ;
+LOCATE COMP "LPSEL_3" SITE "15" ;
+LOCATE COMP "LPSEL_4" SITE "14" ;
+LOCATE COMP "MSPTCK_0" SITE "75" ;
+LOCATE COMP "MSPTCK_1" SITE "68" ;
+LOCATE COMP "MSPTCK_2" SITE "63" ;
+LOCATE COMP "MSPTCK_3" SITE "57" ;
+LOCATE COMP "MSPTCK_4" SITE "48" ;
+LOCATE COMP "MSPTDI_0" SITE "74" ;
+LOCATE COMP "MSPTDI_1" SITE "67" ;
+LOCATE COMP "MSPTDI_2" SITE "62" ;
+LOCATE COMP "MSPTDI_3" SITE "54" ;
+LOCATE COMP "MSPTDI_4" SITE "47" ;
+LOCATE COMP "MSPTDO_0" SITE "71" ;
+LOCATE COMP "MSPTDO_1" SITE "66" ;
+LOCATE COMP "MSPTDO_2" SITE "60" ;
+LOCATE COMP "MSPTDO_3" SITE "53" ;
+LOCATE COMP "MSPTDO_4" SITE "45" ;
+LOCATE COMP "MSPTMS_0" SITE "70" ;
+LOCATE COMP "MSPTMS_1" SITE "65" ;
+LOCATE COMP "MSPTMS_2" SITE "59" ;
+LOCATE COMP "MSPTMS_3" SITE "52" ;
+LOCATE COMP "MSPTMS_4" SITE "43" ;
+LOCATE COMP "MSPTRST_0" SITE "69" ;
+LOCATE COMP "MSPTRST_1" SITE "64" ;
+LOCATE COMP "MSPTRST_2" SITE "58" ;
+LOCATE COMP "MSPTRST_3" SITE "51" ;
+LOCATE COMP "MSPTRST_4" SITE "42" ;
+LOCATE COMP "TCK" SITE "85" ;
+LOCATE COMP "TDI" SITE "84" ;
+LOCATE COMP "TDO" SITE "83" ;
+LOCATE COMP "TMS" SITE "82" ;
+LOCATE COMP "TRST" SITE "78" ;
+LOCATE COMP "CTRL_0" SITE "10" ;
+LOCATE COMP "CTRL_1" SITE "9" ;
+LOCATE COMP "IDN_0" SITE "99" ;
+LOCATE COMP "IDN_1" SITE "98" ;
+LOCATE COMP "IDN_2" SITE "97" ;
+LOCATE COMP "IDN_3" SITE "96" ;
+LOCATE COMP "LPSEL_0" SITE "18" ;
+LOCATE COMP "LPSEL_1" SITE "17" ;
+LOCATE COMP "LPSEL_2" SITE "16" ;
+LOCATE COMP "LPSEL_3" SITE "15" ;
+LOCATE COMP "LPSEL_4" SITE "14" ;
+LOCATE COMP "MSPTCK_0" SITE "75" ;
+LOCATE COMP "MSPTCK_1" SITE "68" ;
+LOCATE COMP "MSPTCK_2" SITE "63" ;
+LOCATE COMP "MSPTCK_3" SITE "57" ;
+LOCATE COMP "MSPTCK_4" SITE "48" ;
+LOCATE COMP "MSPTDI_0" SITE "74" ;
+LOCATE COMP "MSPTDI_1" SITE "67" ;
+LOCATE COMP "MSPTDI_2" SITE "62" ;
+LOCATE COMP "MSPTDI_3" SITE "54" ;
+LOCATE COMP "MSPTDI_4" SITE "47" ;
+LOCATE COMP "MSPTDO_0" SITE "71" ;
+LOCATE COMP "MSPTDO_1" SITE "66" ;
+LOCATE COMP "MSPTDO_2" SITE "60" ;
+LOCATE COMP "MSPTDO_3" SITE "53" ;
+LOCATE COMP "MSPTDO_4" SITE "45" ;
+LOCATE COMP "MSPTMS_0" SITE "70" ;
+LOCATE COMP "MSPTMS_1" SITE "65" ;
+LOCATE COMP "MSPTMS_2" SITE "59" ;
+LOCATE COMP "MSPTMS_3" SITE "52" ;
+LOCATE COMP "MSPTMS_4" SITE "43" ;
+LOCATE COMP "MSPTRST_0" SITE "69" ;
+LOCATE COMP "MSPTRST_1" SITE "64" ;
+LOCATE COMP "MSPTRST_2" SITE "58" ;
+LOCATE COMP "MSPTRST_3" SITE "51" ;
+LOCATE COMP "MSPTRST_4" SITE "42" ;
+LOCATE COMP "CTRL_0" SITE "10" ;
+LOCATE COMP "CTRL_1" SITE "9" ;
+LOCATE COMP "IDN_0" SITE "99" ;
+LOCATE COMP "IDN_1" SITE "98" ;
+LOCATE COMP "IDN_2" SITE "97" ;
+LOCATE COMP "IDN_3" SITE "96" ;
+LOCATE COMP "LPSEL_0" SITE "18" ;
+LOCATE COMP "LPSEL_1" SITE "17" ;
+LOCATE COMP "LPSEL_2" SITE "16" ;
+LOCATE COMP "LPSEL_3" SITE "15" ;
+LOCATE COMP "LPSEL_4" SITE "14" ;
+LOCATE COMP "MSPTCK_0" SITE "75" ;
+LOCATE COMP "MSPTCK_1" SITE "68" ;
+LOCATE COMP "MSPTCK_2" SITE "63" ;
+LOCATE COMP "MSPTCK_3" SITE "57" ;
+LOCATE COMP "MSPTCK_4" SITE "48" ;
+LOCATE COMP "MSPTDI_0" SITE "74" ;
+LOCATE COMP "MSPTDI_1" SITE "67" ;
+LOCATE COMP "MSPTDI_2" SITE "62" ;
+LOCATE COMP "MSPTDI_3" SITE "54" ;
+LOCATE COMP "MSPTDI_4" SITE "47" ;
+LOCATE COMP "MSPTDO_0" SITE "71" ;
+LOCATE COMP "MSPTDO_1" SITE "66" ;
+LOCATE COMP "MSPTDO_2" SITE "60" ;
+LOCATE COMP "MSPTDO_3" SITE "53" ;
+LOCATE COMP "MSPTDO_4" SITE "45" ;
+LOCATE COMP "MSPTMS_0" SITE "70" ;
+LOCATE COMP "MSPTMS_1" SITE "65" ;
+LOCATE COMP "MSPTMS_2" SITE "59" ;
+LOCATE COMP "MSPTMS_3" SITE "52" ;
+LOCATE COMP "MSPTMS_4" SITE "43" ;
+LOCATE COMP "MSPTRST_0" SITE "69" ;
+LOCATE COMP "MSPTRST_1" SITE "64" ;
+LOCATE COMP "MSPTRST_2" SITE "58" ;
+LOCATE COMP "MSPTRST_3" SITE "51" ;
+LOCATE COMP "MSPTRST_4" SITE "42" ;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG.ddt b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG.ddt
new file mode 100644
index 0000000000..b61b461069
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG.ddt
@@ -0,0 +1,18 @@
+[Deployment Project]
+version=Lattice Diamond 3.3.0.109
+EncryptionVer=1.0
+functionIdx=0
+typeIdx=1
+isRequiredXCFFile=0
+xcfFileName=
+optionList=Convert Bi-directional I/O's to Input and Output
+valueList=On
+
+[Input File Info]
+inputFileList=M:/VIEWlogic/Projects/Quinten/UniBoard2/rev1/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE_UNB2_JTAG_SCANBRIDGE.jed;M:/VIEWlogic/Projects/Quinten/UniBoard2/rev1/JTAG/BSDL/bsdllcmxo2-640hctqfp100.BSM
+familyList=MachXO2;MachXO2
+deviceList=LCMXO2-640HC;LCMXO2-640HC
+outputFileList=M:/VIEWlogic/Projects/Quinten/UniBoard2/rev1/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE.bsm
+
+[Command Line]
+Command="C:/lscc/diamond/3.3/bin/nt/ddtcmd" -oft -bsm -ifd "M:/VIEWlogic/Projects/Quinten/UniBoard2/rev1/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE_UNB2_JTAG_SCANBRIDGE.jed" -ifb "M:/VIEWlogic/Projects/Quinten/UniBoard2/rev1/JTAG/BSDL/bsdllcmxo2-640hctqfp100.BSM" -dev LCMXO2-640HC -convertbidi -of "M:/VIEWlogic/Projects/Quinten/UniBoard2/rev1/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE.bsm"
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE.xcf b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE.xcf
new file mode 100644
index 0000000000..8297100801
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE.xcf
@@ -0,0 +1,48 @@
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="3.3.0">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>1</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>MachXO2</Family>
+ <Name>LCMXO2-640HC</Name>
+ <IDCode>0x012b9043</IDCode>
+ <Package>All</Package>
+ <PON>LCMXO2-640HC</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>M:/VIEWlogic/Projects/Quinten/UniBoard2/rev1/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE_UNB2_JTAG_SCANBRIDGE.jed</File>
+ <FileTime>01/05/15 09:22:49</FileTime>
+ <JedecChecksum>0xDEF5</JedecChecksum>
+ <Operation>FLASH Erase,Program,Verify</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>152</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>FLASH</AccessMode>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <VerifyUsercode value="FALSE"/>
+ </ProjectOptions>
+ <CableOptions>
+ <CableName>USB</CableName>
+ <PortAdd>EzUSB-0</PortAdd>
+ </CableOptions>
+</ispXCF>
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/JTAG.lpf b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/JTAG.lpf
new file mode 100644
index 0000000000..6a7b606cfb
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/JTAG.lpf
@@ -0,0 +1,114 @@
+LOCATE COMP "CTRL_0" SITE "10" ;
+LOCATE COMP "CTRL_1" SITE "9" ;
+LOCATE COMP "ENABLE_MSP" SITE "8" ;
+LOCATE COMP "IDN_0" SITE "99" ;
+LOCATE COMP "IDN_1" SITE "98" ;
+LOCATE COMP "IDN_2" SITE "97" ;
+LOCATE COMP "IDN_3" SITE "96" ;
+LOCATE COMP "LPSEL_0" SITE "18" ;
+LOCATE COMP "LPSEL_1" SITE "17" ;
+LOCATE COMP "LPSEL_2" SITE "16" ;
+LOCATE COMP "LPSEL_3" SITE "15" ;
+LOCATE COMP "LPSEL_4" SITE "14" ;
+LOCATE COMP "MSPTCK_0" SITE "75" ;
+LOCATE COMP "MSPTCK_1" SITE "68" ;
+LOCATE COMP "MSPTCK_2" SITE "63" ;
+LOCATE COMP "MSPTCK_3" SITE "57" ;
+LOCATE COMP "MSPTCK_4" SITE "48" ;
+LOCATE COMP "MSPTDI_0" SITE "74" ;
+LOCATE COMP "MSPTDI_1" SITE "67" ;
+LOCATE COMP "MSPTDI_2" SITE "62" ;
+LOCATE COMP "MSPTDI_3" SITE "54" ;
+LOCATE COMP "MSPTDI_4" SITE "47" ;
+LOCATE COMP "MSPTDO_0" SITE "71" ;
+LOCATE COMP "MSPTDO_1" SITE "66" ;
+LOCATE COMP "MSPTDO_2" SITE "60" ;
+LOCATE COMP "MSPTDO_3" SITE "53" ;
+LOCATE COMP "MSPTDO_4" SITE "45" ;
+LOCATE COMP "MSPTMS_0" SITE "70" ;
+LOCATE COMP "MSPTMS_1" SITE "65" ;
+LOCATE COMP "MSPTMS_2" SITE "59" ;
+LOCATE COMP "MSPTMS_3" SITE "52" ;
+LOCATE COMP "MSPTMS_4" SITE "43" ;
+LOCATE COMP "MSPTRST_0" SITE "69" ;
+LOCATE COMP "MSPTRST_1" SITE "64" ;
+LOCATE COMP "MSPTRST_2" SITE "58" ;
+LOCATE COMP "MSPTRST_3" SITE "51" ;
+LOCATE COMP "MSPTRST_4" SITE "42" ;
+LOCATE COMP "TCK" SITE "85" ;
+LOCATE COMP "TDI" SITE "84" ;
+LOCATE COMP "TDO" SITE "83" ;
+LOCATE COMP "TMS" SITE "82" ;
+LOCATE COMP "TRST" SITE "78" ;
+LOCATE COMP "CTRL_0" SITE "10" ;
+LOCATE COMP "CTRL_1" SITE "9" ;
+LOCATE COMP "IDN_0" SITE "99" ;
+LOCATE COMP "IDN_1" SITE "98" ;
+LOCATE COMP "IDN_2" SITE "97" ;
+LOCATE COMP "IDN_3" SITE "96" ;
+LOCATE COMP "LPSEL_0" SITE "18" ;
+LOCATE COMP "LPSEL_1" SITE "17" ;
+LOCATE COMP "LPSEL_2" SITE "16" ;
+LOCATE COMP "LPSEL_3" SITE "15" ;
+LOCATE COMP "LPSEL_4" SITE "14" ;
+LOCATE COMP "MSPTCK_0" SITE "75" ;
+LOCATE COMP "MSPTCK_1" SITE "68" ;
+LOCATE COMP "MSPTCK_2" SITE "63" ;
+LOCATE COMP "MSPTCK_3" SITE "57" ;
+LOCATE COMP "MSPTCK_4" SITE "48" ;
+LOCATE COMP "MSPTDI_0" SITE "74" ;
+LOCATE COMP "MSPTDI_1" SITE "67" ;
+LOCATE COMP "MSPTDI_2" SITE "62" ;
+LOCATE COMP "MSPTDI_3" SITE "54" ;
+LOCATE COMP "MSPTDI_4" SITE "47" ;
+LOCATE COMP "MSPTDO_0" SITE "71" ;
+LOCATE COMP "MSPTDO_1" SITE "66" ;
+LOCATE COMP "MSPTDO_2" SITE "60" ;
+LOCATE COMP "MSPTDO_3" SITE "53" ;
+LOCATE COMP "MSPTDO_4" SITE "45" ;
+LOCATE COMP "MSPTMS_0" SITE "70" ;
+LOCATE COMP "MSPTMS_1" SITE "65" ;
+LOCATE COMP "MSPTMS_2" SITE "59" ;
+LOCATE COMP "MSPTMS_3" SITE "52" ;
+LOCATE COMP "MSPTMS_4" SITE "43" ;
+LOCATE COMP "MSPTRST_0" SITE "69" ;
+LOCATE COMP "MSPTRST_1" SITE "64" ;
+LOCATE COMP "MSPTRST_2" SITE "58" ;
+LOCATE COMP "MSPTRST_3" SITE "51" ;
+LOCATE COMP "MSPTRST_4" SITE "42" ;
+LOCATE COMP "CTRL_0" SITE "10" ;
+LOCATE COMP "CTRL_1" SITE "9" ;
+LOCATE COMP "IDN_0" SITE "99" ;
+LOCATE COMP "IDN_1" SITE "98" ;
+LOCATE COMP "IDN_2" SITE "97" ;
+LOCATE COMP "IDN_3" SITE "96" ;
+LOCATE COMP "LPSEL_0" SITE "18" ;
+LOCATE COMP "LPSEL_1" SITE "17" ;
+LOCATE COMP "LPSEL_2" SITE "16" ;
+LOCATE COMP "LPSEL_3" SITE "15" ;
+LOCATE COMP "LPSEL_4" SITE "14" ;
+LOCATE COMP "MSPTCK_0" SITE "75" ;
+LOCATE COMP "MSPTCK_1" SITE "68" ;
+LOCATE COMP "MSPTCK_2" SITE "63" ;
+LOCATE COMP "MSPTCK_3" SITE "57" ;
+LOCATE COMP "MSPTCK_4" SITE "48" ;
+LOCATE COMP "MSPTDI_0" SITE "74" ;
+LOCATE COMP "MSPTDI_1" SITE "67" ;
+LOCATE COMP "MSPTDI_2" SITE "62" ;
+LOCATE COMP "MSPTDI_3" SITE "54" ;
+LOCATE COMP "MSPTDI_4" SITE "47" ;
+LOCATE COMP "MSPTDO_0" SITE "71" ;
+LOCATE COMP "MSPTDO_1" SITE "66" ;
+LOCATE COMP "MSPTDO_2" SITE "60" ;
+LOCATE COMP "MSPTDO_3" SITE "53" ;
+LOCATE COMP "MSPTDO_4" SITE "45" ;
+LOCATE COMP "MSPTMS_0" SITE "70" ;
+LOCATE COMP "MSPTMS_1" SITE "65" ;
+LOCATE COMP "MSPTMS_2" SITE "59" ;
+LOCATE COMP "MSPTMS_3" SITE "52" ;
+LOCATE COMP "MSPTMS_4" SITE "43" ;
+LOCATE COMP "MSPTRST_0" SITE "69" ;
+LOCATE COMP "MSPTRST_1" SITE "64" ;
+LOCATE COMP "MSPTRST_2" SITE "58" ;
+LOCATE COMP "MSPTRST_3" SITE "51" ;
+LOCATE COMP "MSPTRST_4" SITE "42" ;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/.jtag_top(str).vhd.swp b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/.jtag_top(str).vhd.swp
new file mode 100644
index 0000000000000000000000000000000000000000..9c5478a7319920d309819ce95ca9d797b1c0ae95
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zOd+0mQfa>_%#R0}Nj%l9w0Izt#4}SUi3dVy@xW9P&kU)wUuI^<Gd`9?sZkMKsxN3I
zjy;wwEu}F4(U^f)bY+%k%tI_%oasTrMopdS=fpTJo~{ok<G46?9FJ@W^NbR;Z}#vV
z5H5yqT95J(F{P%a+l2zm-bYHG%`7r2F`JTEQ}g5U%-%Vh3%o?fkv)L!EY2&-rPH*h
Tvp!LbXY}To%<|qJ?acoIbF=mS
literal 0
HcmV?d00001
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
new file mode 100644
index 0000000000..262b7dcb68
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
@@ -0,0 +1,134 @@
+-- --------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+-- --------------------------------------------------------------------
+-- Copyright (c) 2001 - 2008 by Lattice Semiconductor Corporation
+-- --------------------------------------------------------------------
+--
+-- Permission:
+--
+-- Lattice Semiconductor grants permission to use this code for use
+-- in synthesis for any Lattice programmable logic product. Other
+-- use of this code, including the selling or duplication of any
+-- portion is strictly prohibited.
+--
+-- Disclaimer:
+--
+-- This VHDL or Verilog source code is intended as a design reference
+-- which illustrates how these types of functions can be implemented.
+-- It is the user's responsibility to verify their design for
+-- consistency and functionality through the use of formal
+-- verification methods. Lattice Semiconductor provides no warranty
+-- regarding the use or functionality of this code.
+--
+-- --------------------------------------------------------------------
+--
+-- Lattice Semiconductor Corporation
+-- 5555 NE Moore Court
+-- Hillsboro, OR 97214
+-- U.S.A
+--
+-- TEL: 1-800-Lattice (USA and Canada)
+-- 503-268-8001 (other locations)
+--
+-- web: http://www.latticesemi.com/
+-- email: techsupport@latticesemi.com
+--
+-- --------------------------------------------------------------------
+-- Code Revision History :
+-- --------------------------------------------------------------------
+-- Ver: | Author |Mod. Date |Changes Made:
+-- V1.0 | J.O. |11/10/08 |Initial Version
+-- --------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity bscan2 is
+ -- enter the number of BSCAN2 blocks to create. This is the only place that
+ -- needs to be modified to control the number of local scan ports created.
+ generic ( bscan_ports : positive := 2 );
+ PORT( TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- Turn on slow slew in fitter for output signals
+ TDO : out std_logic;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : in std_logic;
+ MSPTCK : out std_logic_vector(4*bscan_ports-1 downto 0);
+ MSPTDI : in std_logic_vector(4*bscan_ports-1 downto 0);
+ MSPTDO : out std_logic_vector(4*bscan_ports-1 downto 0);
+ MSPTMS : out std_logic_vector(4*bscan_ports-1 downto 0);
+ MSPTRST : out std_logic_vector(4*bscan_ports-1 downto 0);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(3 downto 0)
+ );
+end;
+
+architecture behave of bscan2 is
+
+ component top_linker is
+ -- do not use the generic map to prevent the synthesis tool from
+ -- appending the number of ports to the components name.
+ port(TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- enable logic for TDO pins.
+ TDO_enable : out std_logic;
+ TDO : out std_logic;
+ MSPCLK : out std_logic_vector(4*bscan_ports downto 1);
+ MSPTDI : in std_logic_vector(4*bscan_ports downto 1);
+ MSPTDO : out std_logic_vector(4*bscan_ports downto 1);
+ MSPTMS : out std_logic_vector(4*bscan_ports downto 1);
+ MSPTRST : out std_logic_vector(4*bscan_ports downto 1);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(4 downto 1)
+ );
+end component top_linker;
+-- synthesis FILE="top_linker.ngo"
+
+-- logic to enable TDO pins
+signal ENABLE_TDO : std_logic;
+-- signal from tap controler that enables all TDOs.
+signal tdoENABLE : std_logic;
+-- logic to generate tdo_sp and tdo_hdr
+signal LSPTMS : std_logic_vector(4*bscan_ports-1 downto 0);
+signal LSPTCK : std_logic_vector(4*bscan_ports-1 downto 0);
+signal LSPTDO : std_logic_vector(4*bscan_ports-1 downto 0);
+signal LSPTRST : std_logic_vector(4*bscan_ports-1 downto 0);
+-- output of Port Mux
+signal TDO_int : std_logic;
+
+begin
+ -- Wire up all of the tri-state controlled lines automatically
+ tri_state_lines : for lvar1 in 0 to (4*bscan_ports-1) generate
+ MSPTCK(lvar1) <= LSPTCK(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTMS(lvar1) <= LSPTMS(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTRST(lvar1) <= LSPTRST(lvar1) when ENABLE_MSP = '1' else 'Z';
+ -- enable MSPTDOs for 1149.1
+ MSPTDO(lvar1) <= LSPTDO(lvar1) when ENABLE_TDO = '1' else 'Z';
+ end generate tri_state_lines;
+
+ -- MSP Port enable controls
+ -- enable logic for all TDO pins
+ ENABLE_TDO <= ENABLE_MSP and tdoENABLE;
+
+ TDO <= TDO_int when tdoENABLE = '1' else 'Z';
+
+ TopLinkerModule : component top_linker
+ port map(
+ TDO => TDO_int,
+ TMS => TMS,
+ TCK => TCK,
+ TRST => TRST,
+ TDI => TDI,
+ TDO_enable => tdoENABLE,
+ MSPTDI => MSPTDI,
+ MSPTDO => LSPTDO,
+ MSPTMS => LSPTMS,
+ MSPCLK => LSPTCK,
+ MSPTRST => LSPTRST,
+ IDN => IDN
+ );
+
+end behave;
+
+--------------------------------- E O F --------------------------------------
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top - Copy.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top - Copy.vhd
new file mode 100644
index 0000000000..55f1991e7d
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top - Copy.vhd
@@ -0,0 +1,28 @@
+---------------------------------------------------------------------------------
+--
+-- Vhdl file created by I/O Designer
+-- Fri Feb 28 17:51:25 2014
+--
+---------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity jtag_top is
+ port (
+ CTRL : in std_logic_vector (1 downto 0);
+ ENABLE_MSP : in std_logic;
+ IDN : in std_logic_vector (3 downto 0);
+ LPSEL : in std_logic_vector (4 downto 0);
+ MSPTCK : out std_logic_vector (4 downto 0);
+ MSPTDI : in std_logic_vector (4 downto 0);
+ MSPTDO : out std_logic_vector (4 downto 0);
+ MSPTMS : out std_logic_vector (4 downto 0);
+ MSPTRST : out std_logic_vector (4 downto 0);
+ TCK : in std_logic;
+ TDI : in std_logic;
+ TDO : out std_logic;
+ TMS : in std_logic;
+ TRST : in std_logic
+ );
+end jtag_top;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str) - Copy.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str) - Copy.vhd
new file mode 100644
index 0000000000..e0280135d7
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str) - Copy.vhd
@@ -0,0 +1,242 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+
+
+ARCHITECTURE str OF jtag_top IS
+
+ COMPONENT bscan2 IS
+ -- enter the number of BSCAN2 blocks to create. This is the only place that
+ -- needs to be modified to control the number of local scan ports created.
+ GENERIC (
+ bscan_ports : POSITIVE := 2
+
+ );
+ PORT (
+ TDI, TCK, TMS : IN STD_LOGIC;
+ TRST : IN STD_LOGIC;
+ -- Turn on slow slew in fitter for output signals
+ TDO : OUT STD_LOGIC;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : IN STD_LOGIC;
+ MSPTCK : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTDI : IN STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTDO : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTMS : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTRST : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ -- one set of addresses to check for device
+ IDN : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
+ );
+ END COMPONENT bscan2;
+
+-- internal enable signal for tri-stating the scanbridge
+ CONSTANT jtag_chains : NATURAL := 5;
+ SIGNAL ENABLE_SB : STD_LOGIC;
+ SIGNAL TDO_BSCAN : STD_LOGIC;
+ SIGNAL TDA : STD_LOGIC;
+ SIGNAL TDB : STD_LOGIC;
+ SIGNAL TDC : STD_LOGIC;
+ SIGNAL MSPTDO_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTCK_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTMS_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTRST_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+
+ BEGIN
+ bscan : COMPONENT bscan2
+ PORT MAP (
+ TDI => TDI,
+ TCK => TCK,
+ TMS => TMS,
+ TRST => TRST,
+ TDO => TDO_BSCAN,
+ ENABLE_MSP => ENABLE_SB,
+ MSPTCK(jtag_chains-1 DOWNTO 0) => MSPTCK_BSCAN,
+ MSPTDI(jtag_chains-1 DOWNTO 0) => MSPTDI,
+ MSPTDO(jtag_chains-1 DOWNTO 0) => MSPTDO_BSCAN,
+ MSPTMS(jtag_chains-1 DOWNTO 0) => MSPTMS_BSCAN,
+ MSPTRST(jtag_chains-1 DOWNTO 0) => MSPTRST_BSCAN,
+ IDN => IDN
+ );
+
+
+ p_jtagselect: PROCESS(TDI,MSPTDI(jtag_chains-1 DOWNTO 0),TCK,TMS,TRST)
+ BEGIN
+ ENABLE_SB <= '0';
+ MSPTDO(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTCK(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTMS(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTRST(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+
+ IF LPSEL(4) = '0' THEN
+ ENABLE_SB <= ENABLE_MSP;
+ MSPTDO <= MSPTDO_BSCAN;
+ TDO <= TDO_BSCAN;
+ MSPTCK <= MSPTCK_BSCAN;
+ MSPTMS <= MSPTMS_BSCAN;
+ MSPTRST <= MSPTRST_BSCAN;
+ else
+ IF LPSEL(0) = '0' THEN
+ MSPTDO(0) <= TDI;
+ TDA <= MSPTDI(0);
+ MSPTCK(0) <= TCK;
+ MSPTMS(0) <= TMS;
+ MSPTRST(0) <= TRST;
+ ELSE
+ TDA <= TDI;
+ END IF;
+
+ IF LPSEL(1) = '0' THEN
+ MSPTDO(1) <= TDA;
+ TDB <= MSPTDI(1);
+ MSPTCK(1) <= TCK;
+ MSPTMS(1) <= TMS;
+ MSPTRST(1) <= TRST;
+ ELSE
+ TDB <= TDA;
+ END IF;
+
+ IF LPSEL(2) = '0' THEN
+ MSPTDO(2) <= TDB;
+ TDC <= MSPTDI(2);
+ MSPTCK(2) <= TCK;
+ MSPTMS(2) <= TMS;
+ MSPTRST(2) <= TRST;
+ ELSE
+ TDC <= TDB;
+ END IF;
+
+ IF LPSEL(3) = '0' THEN
+ MSPTDO(3) <= TDC;
+ TDO <= MSPTDI(3);
+ MSPTCK(3) <= TCK;
+ MSPTMS(3) <= TMS;
+ MSPTRST(3) <= TRST;
+ ELSE
+ TDO <= TDC;
+ END IF;
+ END IF;
+
+-- old
+-- CASE LPSEL IS
+-- WHEN "00000" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(0) <= TDI;
+-- MSPTDO(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
+-- TDO <= MSPTDI(0);
+-- MSPTCK(0) <= TCK;
+-- MSPTCK(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
+-- MSPTMS(0) <= TMS;
+-- MSPTMS(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
+-- MSPTRST(0) <= TRST;
+-- MSPTRST(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
+-- WHEN "00001" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(1) <= TDI;
+-- MSPTDO(jtag_chains-1 DOWNTO 2) <= "ZZZ";
+-- MSPTDO(0) <= 'Z';
+-- TDO <= MSPTDI(1);
+-- MSPTCK(1) <= TCK;
+-- MSPTCK(jtag_chains-1 DOWNTO 2) <= "ZZZ";
+-- MSPTMS(1) <= TMS;
+-- MSPTMS(jtag_chains-1 DOWNTO 2) <= "ZZZ";
+-- MSPTRST(1) <= TRST;
+-- MSPTRST(jtag_chains-1 DOWNTO 2) <= "ZZZ";
+-- WHEN "00010" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(2) <= TDI;
+-- MSPTDO(jtag_chains-1 DOWNTO 3) <= "ZZ";
+-- MSPTDO(1 DOWNTO 0) <= "ZZ";
+-- TDO <= MSPTDI(2);
+-- MSPTCK(2) <= TCK;
+-- MSPTCK(jtag_chains-1 DOWNTO 3) <= "ZZ";
+-- MSPTMS(2) <= TMS;
+-- MSPTMS(jtag_chains-1 DOWNTO 3) <= "ZZ";
+-- MSPTRST(2) <= TRST;
+-- MSPTRST(jtag_chains-1 DOWNTO 3) <= "ZZ";
+-- WHEN "00011" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(3) <= TDI;
+-- MSPTDO(4) <= 'Z';
+-- MSPTDO(2 DOWNTO 0) <= "ZZZ";
+-- TDO <= MSPTDI(3);
+-- MSPTCK(3) <= TCK;
+-- MSPTCK(2 DOWNTO 0) <= "ZZZ";
+-- MSPTMS(3) <= TMS;
+-- MSPTMS(2 DOWNTO 0) <= "ZZZ";
+-- MSPTRST(3) <= TRST;
+-- MSPTRST(2 DOWNTO 0) <= "ZZZ";
+-- WHEN "00100" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(4) <= TDI;
+-- MSPTDO(3 DOWNTO 0) <= "ZZZZ";
+-- TDO <= MSPTDI(4);
+-- MSPTCK(4) <= TCK;
+-- MSPTCK(3 DOWNTO 0) <= "ZZZZ";
+-- MSPTMS(4) <= TMS;
+-- MSPTMS(3 DOWNTO 0) <= "ZZZZ";
+-- MSPTRST(4) <= TRST;
+-- MSPTRST(3 DOWNTO 0) <= "ZZZZ";
+-- WHEN "00101" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(0) <= TDI;
+-- MSPTDO(1) <= MSPTDI(0);
+-- MSPTDO(2) <= MSPTDI(1);
+-- MSPTDO(3) <= MSPTDI(2);
+-- TDO <= MSPTDI(3);
+-- MSPTDO(jtag_chains-1 DOWNTO 4) <= "Z";
+-- MSPTCK(0) <= TCK;
+-- MSPTCK(1) <= TCK;
+-- MSPTCK(2) <= TCK;
+-- MSPTCK(3) <= TCK;
+-- MSPTCK(jtag_chains-1 DOWNTO 4) <= "Z";
+-- MSPTMS(0) <= TMS;
+-- MSPTMS(1) <= TMS;
+-- MSPTMS(2) <= TMS;
+-- MSPTMS(3) <= TMS;
+-- MSPTMS(jtag_chains-1 DOWNTO 4) <= "Z";
+-- MSPTRST(0) <= TRST;
+-- MSPTRST(1) <= TRST;
+-- MSPTRST(2) <= TRST;
+-- MSPTRST(3) <= TRST;
+-- MSPTRST(jtag_chains-1 DOWNTO 4) <= "Z";
+-- WHEN "00111" =>
+-- ENABLE_SB <= 'Z';
+-- MSPTDO(4 DOWNTO 0) <= "ZZZZZ";
+-- TDO <= 'Z';
+-- MSPTCK(4 DOWNTO 0) <= "ZZZZZ";
+-- MSPTMS(4 DOWNTO 0) <= "ZZZZZ";
+-- MSPTRST(4 DOWNTO 0) <= "ZZZZZ";
+-- WHEN OTHERS =>
+-- ENABLE_SB <= ENABLE_MSP;
+-- MSPTDO <= MSPTDO_BSCAN;
+-- TDO <= TDO_BSCAN;
+-- MSPTCK <= MSPTCK_BSCAN;
+-- MSPTMS <= MSPTMS_BSCAN;
+-- MSPTRST <= MSPTRST_BSCAN;
+-- END CASE;
+
+ END PROCESS;
+END str;
+
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
new file mode 100644
index 0000000000..91f0933040
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
@@ -0,0 +1,154 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+
+
+ARCHITECTURE str OF jtag_top IS
+
+ COMPONENT bscan2 IS
+ -- enter the number of BSCAN2 blocks to create. This is the only place that
+ -- needs to be modified to control the number of local scan ports created.
+ GENERIC (
+ bscan_ports : POSITIVE := 2
+
+ );
+ PORT (
+ TDI, TCK, TMS : IN STD_LOGIC;
+ TRST : IN STD_LOGIC;
+ -- Turn on slow slew in fitter for output signals
+ TDO : OUT STD_LOGIC;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : IN STD_LOGIC;
+ MSPTCK : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTDI : IN STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTDO : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTMS : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTRST : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ -- one set of addresses to check for device
+ IDN : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
+ );
+ END COMPONENT bscan2;
+
+-- internal enable signal for tri-stating the scanbridge
+ CONSTANT jtag_chains : NATURAL := 5;
+ SIGNAL ENABLE_SB : STD_LOGIC;
+ SIGNAL TDO_BSCAN : STD_LOGIC;
+ SIGNAL TDA : STD_LOGIC;
+ SIGNAL TDB : STD_LOGIC;
+ SIGNAL TDC : STD_LOGIC;
+ SIGNAL TDD : STD_LOGIC;
+ SIGNAL MSPTDO_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTCK_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTMS_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTRST_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+
+ BEGIN
+ bscan : COMPONENT bscan2
+ PORT MAP (
+ TDI => TDI,
+ TCK => TCK,
+ TMS => TMS,
+ TRST => TRST,
+ TDO => TDO_BSCAN,
+ ENABLE_MSP => ENABLE_SB,
+ MSPTCK(jtag_chains-1 DOWNTO 0) => MSPTCK_BSCAN,
+ MSPTDI(jtag_chains-1 DOWNTO 0) => MSPTDI,
+ MSPTDO(jtag_chains-1 DOWNTO 0) => MSPTDO_BSCAN,
+ MSPTMS(jtag_chains-1 DOWNTO 0) => MSPTMS_BSCAN,
+ MSPTRST(jtag_chains-1 DOWNTO 0) => MSPTRST_BSCAN,
+ IDN => "0000"
+ );
+
+
+ p_jtagselect: PROCESS(TDI,MSPTDI(jtag_chains-1 DOWNTO 0),TCK,TMS,TRST)
+ BEGIN
+ ENABLE_SB <= '0';
+ MSPTDO(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTCK(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTMS(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTRST(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+
+ IF CTRL(1) = '1' THEN
+ ENABLE_SB <= '1';
+ MSPTDO <= MSPTDO_BSCAN;
+ TDO <= TDO_BSCAN;
+ MSPTCK <= MSPTCK_BSCAN;
+ MSPTMS <= MSPTMS_BSCAN;
+ MSPTRST <= MSPTRST_BSCAN;
+ ELSE
+ IF LPSEL(0) = '0' THEN
+ MSPTDO(0) <= TDI;
+ TDA <= MSPTDI(0);
+ MSPTCK(0) <= TCK;
+ MSPTMS(0) <= TMS;
+ MSPTRST(0) <= TRST;
+ ELSE
+ TDA <= TDI;
+ END IF;
+
+ IF LPSEL(1) = '0' THEN
+ MSPTDO(1) <= TDA;
+ TDB <= MSPTDI(1);
+ MSPTCK(1) <= TCK;
+ MSPTMS(1) <= TMS;
+ MSPTRST(1) <= TRST;
+ ELSE
+ TDB <= TDA;
+ END IF;
+
+ IF LPSEL(2) = '0' THEN
+ MSPTDO(2) <= TDB;
+ TDC <= MSPTDI(2);
+ MSPTCK(2) <= TCK;
+ MSPTMS(2) <= TMS;
+ MSPTRST(2) <= TRST;
+ ELSE
+ TDC <= TDB;
+ END IF;
+
+ IF LPSEL(3) = '0' THEN
+ MSPTDO(3) <= TDC;
+ TDD <= MSPTDI(3);
+ MSPTCK(3) <= TCK;
+ MSPTMS(3) <= TMS;
+ MSPTRST(3) <= TRST;
+ ELSE
+ TDD <= TDC;
+ END IF;
+
+ IF LPSEL(4) = '0' THEN
+ MSPTDO(4) <= TDD;
+ TDO <= MSPTDI(4);
+ MSPTCK(4) <= TCK;
+ MSPTMS(4) <= TMS;
+ MSPTRST(4) <= TRST;
+ ELSE
+ TDO <= TDD;
+ END IF;
+ END IF;
+
+ END PROCESS;
+END str;
+
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
new file mode 100644
index 0000000000..55f1991e7d
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
@@ -0,0 +1,28 @@
+---------------------------------------------------------------------------------
+--
+-- Vhdl file created by I/O Designer
+-- Fri Feb 28 17:51:25 2014
+--
+---------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity jtag_top is
+ port (
+ CTRL : in std_logic_vector (1 downto 0);
+ ENABLE_MSP : in std_logic;
+ IDN : in std_logic_vector (3 downto 0);
+ LPSEL : in std_logic_vector (4 downto 0);
+ MSPTCK : out std_logic_vector (4 downto 0);
+ MSPTDI : in std_logic_vector (4 downto 0);
+ MSPTDO : out std_logic_vector (4 downto 0);
+ MSPTMS : out std_logic_vector (4 downto 0);
+ MSPTRST : out std_logic_vector (4 downto 0);
+ TCK : in std_logic;
+ TDI : in std_logic;
+ TDO : out std_logic;
+ TMS : in std_logic;
+ TRST : in std_logic
+ );
+end jtag_top;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/top_linker.ngo b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/top_linker.ngo
new file mode 100644
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diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
new file mode 100644
index 0000000000..262b7dcb68
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
@@ -0,0 +1,134 @@
+-- --------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+-- --------------------------------------------------------------------
+-- Copyright (c) 2001 - 2008 by Lattice Semiconductor Corporation
+-- --------------------------------------------------------------------
+--
+-- Permission:
+--
+-- Lattice Semiconductor grants permission to use this code for use
+-- in synthesis for any Lattice programmable logic product. Other
+-- use of this code, including the selling or duplication of any
+-- portion is strictly prohibited.
+--
+-- Disclaimer:
+--
+-- This VHDL or Verilog source code is intended as a design reference
+-- which illustrates how these types of functions can be implemented.
+-- It is the user's responsibility to verify their design for
+-- consistency and functionality through the use of formal
+-- verification methods. Lattice Semiconductor provides no warranty
+-- regarding the use or functionality of this code.
+--
+-- --------------------------------------------------------------------
+--
+-- Lattice Semiconductor Corporation
+-- 5555 NE Moore Court
+-- Hillsboro, OR 97214
+-- U.S.A
+--
+-- TEL: 1-800-Lattice (USA and Canada)
+-- 503-268-8001 (other locations)
+--
+-- web: http://www.latticesemi.com/
+-- email: techsupport@latticesemi.com
+--
+-- --------------------------------------------------------------------
+-- Code Revision History :
+-- --------------------------------------------------------------------
+-- Ver: | Author |Mod. Date |Changes Made:
+-- V1.0 | J.O. |11/10/08 |Initial Version
+-- --------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity bscan2 is
+ -- enter the number of BSCAN2 blocks to create. This is the only place that
+ -- needs to be modified to control the number of local scan ports created.
+ generic ( bscan_ports : positive := 2 );
+ PORT( TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- Turn on slow slew in fitter for output signals
+ TDO : out std_logic;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : in std_logic;
+ MSPTCK : out std_logic_vector(4*bscan_ports-1 downto 0);
+ MSPTDI : in std_logic_vector(4*bscan_ports-1 downto 0);
+ MSPTDO : out std_logic_vector(4*bscan_ports-1 downto 0);
+ MSPTMS : out std_logic_vector(4*bscan_ports-1 downto 0);
+ MSPTRST : out std_logic_vector(4*bscan_ports-1 downto 0);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(3 downto 0)
+ );
+end;
+
+architecture behave of bscan2 is
+
+ component top_linker is
+ -- do not use the generic map to prevent the synthesis tool from
+ -- appending the number of ports to the components name.
+ port(TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- enable logic for TDO pins.
+ TDO_enable : out std_logic;
+ TDO : out std_logic;
+ MSPCLK : out std_logic_vector(4*bscan_ports downto 1);
+ MSPTDI : in std_logic_vector(4*bscan_ports downto 1);
+ MSPTDO : out std_logic_vector(4*bscan_ports downto 1);
+ MSPTMS : out std_logic_vector(4*bscan_ports downto 1);
+ MSPTRST : out std_logic_vector(4*bscan_ports downto 1);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(4 downto 1)
+ );
+end component top_linker;
+-- synthesis FILE="top_linker.ngo"
+
+-- logic to enable TDO pins
+signal ENABLE_TDO : std_logic;
+-- signal from tap controler that enables all TDOs.
+signal tdoENABLE : std_logic;
+-- logic to generate tdo_sp and tdo_hdr
+signal LSPTMS : std_logic_vector(4*bscan_ports-1 downto 0);
+signal LSPTCK : std_logic_vector(4*bscan_ports-1 downto 0);
+signal LSPTDO : std_logic_vector(4*bscan_ports-1 downto 0);
+signal LSPTRST : std_logic_vector(4*bscan_ports-1 downto 0);
+-- output of Port Mux
+signal TDO_int : std_logic;
+
+begin
+ -- Wire up all of the tri-state controlled lines automatically
+ tri_state_lines : for lvar1 in 0 to (4*bscan_ports-1) generate
+ MSPTCK(lvar1) <= LSPTCK(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTMS(lvar1) <= LSPTMS(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTRST(lvar1) <= LSPTRST(lvar1) when ENABLE_MSP = '1' else 'Z';
+ -- enable MSPTDOs for 1149.1
+ MSPTDO(lvar1) <= LSPTDO(lvar1) when ENABLE_TDO = '1' else 'Z';
+ end generate tri_state_lines;
+
+ -- MSP Port enable controls
+ -- enable logic for all TDO pins
+ ENABLE_TDO <= ENABLE_MSP and tdoENABLE;
+
+ TDO <= TDO_int when tdoENABLE = '1' else 'Z';
+
+ TopLinkerModule : component top_linker
+ port map(
+ TDO => TDO_int,
+ TMS => TMS,
+ TCK => TCK,
+ TRST => TRST,
+ TDI => TDI,
+ TDO_enable => tdoENABLE,
+ MSPTDI => MSPTDI,
+ MSPTDO => LSPTDO,
+ MSPTMS => LSPTMS,
+ MSPCLK => LSPTCK,
+ MSPTRST => LSPTRST,
+ IDN => IDN
+ );
+
+end behave;
+
+--------------------------------- E O F --------------------------------------
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top - Copy.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top - Copy.vhd
new file mode 100644
index 0000000000..55f1991e7d
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top - Copy.vhd
@@ -0,0 +1,28 @@
+---------------------------------------------------------------------------------
+--
+-- Vhdl file created by I/O Designer
+-- Fri Feb 28 17:51:25 2014
+--
+---------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity jtag_top is
+ port (
+ CTRL : in std_logic_vector (1 downto 0);
+ ENABLE_MSP : in std_logic;
+ IDN : in std_logic_vector (3 downto 0);
+ LPSEL : in std_logic_vector (4 downto 0);
+ MSPTCK : out std_logic_vector (4 downto 0);
+ MSPTDI : in std_logic_vector (4 downto 0);
+ MSPTDO : out std_logic_vector (4 downto 0);
+ MSPTMS : out std_logic_vector (4 downto 0);
+ MSPTRST : out std_logic_vector (4 downto 0);
+ TCK : in std_logic;
+ TDI : in std_logic;
+ TDO : out std_logic;
+ TMS : in std_logic;
+ TRST : in std_logic
+ );
+end jtag_top;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str) - Copy.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str) - Copy.vhd
new file mode 100644
index 0000000000..e0280135d7
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str) - Copy.vhd
@@ -0,0 +1,242 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+
+
+ARCHITECTURE str OF jtag_top IS
+
+ COMPONENT bscan2 IS
+ -- enter the number of BSCAN2 blocks to create. This is the only place that
+ -- needs to be modified to control the number of local scan ports created.
+ GENERIC (
+ bscan_ports : POSITIVE := 2
+
+ );
+ PORT (
+ TDI, TCK, TMS : IN STD_LOGIC;
+ TRST : IN STD_LOGIC;
+ -- Turn on slow slew in fitter for output signals
+ TDO : OUT STD_LOGIC;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : IN STD_LOGIC;
+ MSPTCK : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTDI : IN STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTDO : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTMS : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTRST : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ -- one set of addresses to check for device
+ IDN : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
+ );
+ END COMPONENT bscan2;
+
+-- internal enable signal for tri-stating the scanbridge
+ CONSTANT jtag_chains : NATURAL := 5;
+ SIGNAL ENABLE_SB : STD_LOGIC;
+ SIGNAL TDO_BSCAN : STD_LOGIC;
+ SIGNAL TDA : STD_LOGIC;
+ SIGNAL TDB : STD_LOGIC;
+ SIGNAL TDC : STD_LOGIC;
+ SIGNAL MSPTDO_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTCK_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTMS_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTRST_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+
+ BEGIN
+ bscan : COMPONENT bscan2
+ PORT MAP (
+ TDI => TDI,
+ TCK => TCK,
+ TMS => TMS,
+ TRST => TRST,
+ TDO => TDO_BSCAN,
+ ENABLE_MSP => ENABLE_SB,
+ MSPTCK(jtag_chains-1 DOWNTO 0) => MSPTCK_BSCAN,
+ MSPTDI(jtag_chains-1 DOWNTO 0) => MSPTDI,
+ MSPTDO(jtag_chains-1 DOWNTO 0) => MSPTDO_BSCAN,
+ MSPTMS(jtag_chains-1 DOWNTO 0) => MSPTMS_BSCAN,
+ MSPTRST(jtag_chains-1 DOWNTO 0) => MSPTRST_BSCAN,
+ IDN => IDN
+ );
+
+
+ p_jtagselect: PROCESS(TDI,MSPTDI(jtag_chains-1 DOWNTO 0),TCK,TMS,TRST)
+ BEGIN
+ ENABLE_SB <= '0';
+ MSPTDO(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTCK(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTMS(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTRST(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+
+ IF LPSEL(4) = '0' THEN
+ ENABLE_SB <= ENABLE_MSP;
+ MSPTDO <= MSPTDO_BSCAN;
+ TDO <= TDO_BSCAN;
+ MSPTCK <= MSPTCK_BSCAN;
+ MSPTMS <= MSPTMS_BSCAN;
+ MSPTRST <= MSPTRST_BSCAN;
+ else
+ IF LPSEL(0) = '0' THEN
+ MSPTDO(0) <= TDI;
+ TDA <= MSPTDI(0);
+ MSPTCK(0) <= TCK;
+ MSPTMS(0) <= TMS;
+ MSPTRST(0) <= TRST;
+ ELSE
+ TDA <= TDI;
+ END IF;
+
+ IF LPSEL(1) = '0' THEN
+ MSPTDO(1) <= TDA;
+ TDB <= MSPTDI(1);
+ MSPTCK(1) <= TCK;
+ MSPTMS(1) <= TMS;
+ MSPTRST(1) <= TRST;
+ ELSE
+ TDB <= TDA;
+ END IF;
+
+ IF LPSEL(2) = '0' THEN
+ MSPTDO(2) <= TDB;
+ TDC <= MSPTDI(2);
+ MSPTCK(2) <= TCK;
+ MSPTMS(2) <= TMS;
+ MSPTRST(2) <= TRST;
+ ELSE
+ TDC <= TDB;
+ END IF;
+
+ IF LPSEL(3) = '0' THEN
+ MSPTDO(3) <= TDC;
+ TDO <= MSPTDI(3);
+ MSPTCK(3) <= TCK;
+ MSPTMS(3) <= TMS;
+ MSPTRST(3) <= TRST;
+ ELSE
+ TDO <= TDC;
+ END IF;
+ END IF;
+
+-- old
+-- CASE LPSEL IS
+-- WHEN "00000" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(0) <= TDI;
+-- MSPTDO(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
+-- TDO <= MSPTDI(0);
+-- MSPTCK(0) <= TCK;
+-- MSPTCK(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
+-- MSPTMS(0) <= TMS;
+-- MSPTMS(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
+-- MSPTRST(0) <= TRST;
+-- MSPTRST(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
+-- WHEN "00001" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(1) <= TDI;
+-- MSPTDO(jtag_chains-1 DOWNTO 2) <= "ZZZ";
+-- MSPTDO(0) <= 'Z';
+-- TDO <= MSPTDI(1);
+-- MSPTCK(1) <= TCK;
+-- MSPTCK(jtag_chains-1 DOWNTO 2) <= "ZZZ";
+-- MSPTMS(1) <= TMS;
+-- MSPTMS(jtag_chains-1 DOWNTO 2) <= "ZZZ";
+-- MSPTRST(1) <= TRST;
+-- MSPTRST(jtag_chains-1 DOWNTO 2) <= "ZZZ";
+-- WHEN "00010" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(2) <= TDI;
+-- MSPTDO(jtag_chains-1 DOWNTO 3) <= "ZZ";
+-- MSPTDO(1 DOWNTO 0) <= "ZZ";
+-- TDO <= MSPTDI(2);
+-- MSPTCK(2) <= TCK;
+-- MSPTCK(jtag_chains-1 DOWNTO 3) <= "ZZ";
+-- MSPTMS(2) <= TMS;
+-- MSPTMS(jtag_chains-1 DOWNTO 3) <= "ZZ";
+-- MSPTRST(2) <= TRST;
+-- MSPTRST(jtag_chains-1 DOWNTO 3) <= "ZZ";
+-- WHEN "00011" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(3) <= TDI;
+-- MSPTDO(4) <= 'Z';
+-- MSPTDO(2 DOWNTO 0) <= "ZZZ";
+-- TDO <= MSPTDI(3);
+-- MSPTCK(3) <= TCK;
+-- MSPTCK(2 DOWNTO 0) <= "ZZZ";
+-- MSPTMS(3) <= TMS;
+-- MSPTMS(2 DOWNTO 0) <= "ZZZ";
+-- MSPTRST(3) <= TRST;
+-- MSPTRST(2 DOWNTO 0) <= "ZZZ";
+-- WHEN "00100" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(4) <= TDI;
+-- MSPTDO(3 DOWNTO 0) <= "ZZZZ";
+-- TDO <= MSPTDI(4);
+-- MSPTCK(4) <= TCK;
+-- MSPTCK(3 DOWNTO 0) <= "ZZZZ";
+-- MSPTMS(4) <= TMS;
+-- MSPTMS(3 DOWNTO 0) <= "ZZZZ";
+-- MSPTRST(4) <= TRST;
+-- MSPTRST(3 DOWNTO 0) <= "ZZZZ";
+-- WHEN "00101" =>
+-- ENABLE_SB <= '0';
+-- MSPTDO(0) <= TDI;
+-- MSPTDO(1) <= MSPTDI(0);
+-- MSPTDO(2) <= MSPTDI(1);
+-- MSPTDO(3) <= MSPTDI(2);
+-- TDO <= MSPTDI(3);
+-- MSPTDO(jtag_chains-1 DOWNTO 4) <= "Z";
+-- MSPTCK(0) <= TCK;
+-- MSPTCK(1) <= TCK;
+-- MSPTCK(2) <= TCK;
+-- MSPTCK(3) <= TCK;
+-- MSPTCK(jtag_chains-1 DOWNTO 4) <= "Z";
+-- MSPTMS(0) <= TMS;
+-- MSPTMS(1) <= TMS;
+-- MSPTMS(2) <= TMS;
+-- MSPTMS(3) <= TMS;
+-- MSPTMS(jtag_chains-1 DOWNTO 4) <= "Z";
+-- MSPTRST(0) <= TRST;
+-- MSPTRST(1) <= TRST;
+-- MSPTRST(2) <= TRST;
+-- MSPTRST(3) <= TRST;
+-- MSPTRST(jtag_chains-1 DOWNTO 4) <= "Z";
+-- WHEN "00111" =>
+-- ENABLE_SB <= 'Z';
+-- MSPTDO(4 DOWNTO 0) <= "ZZZZZ";
+-- TDO <= 'Z';
+-- MSPTCK(4 DOWNTO 0) <= "ZZZZZ";
+-- MSPTMS(4 DOWNTO 0) <= "ZZZZZ";
+-- MSPTRST(4 DOWNTO 0) <= "ZZZZZ";
+-- WHEN OTHERS =>
+-- ENABLE_SB <= ENABLE_MSP;
+-- MSPTDO <= MSPTDO_BSCAN;
+-- TDO <= TDO_BSCAN;
+-- MSPTCK <= MSPTCK_BSCAN;
+-- MSPTMS <= MSPTMS_BSCAN;
+-- MSPTRST <= MSPTRST_BSCAN;
+-- END CASE;
+
+ END PROCESS;
+END str;
+
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
new file mode 100644
index 0000000000..91f0933040
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
@@ -0,0 +1,154 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+
+
+ARCHITECTURE str OF jtag_top IS
+
+ COMPONENT bscan2 IS
+ -- enter the number of BSCAN2 blocks to create. This is the only place that
+ -- needs to be modified to control the number of local scan ports created.
+ GENERIC (
+ bscan_ports : POSITIVE := 2
+
+ );
+ PORT (
+ TDI, TCK, TMS : IN STD_LOGIC;
+ TRST : IN STD_LOGIC;
+ -- Turn on slow slew in fitter for output signals
+ TDO : OUT STD_LOGIC;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : IN STD_LOGIC;
+ MSPTCK : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTDI : IN STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTDO : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTMS : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ MSPTRST : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
+ -- one set of addresses to check for device
+ IDN : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
+ );
+ END COMPONENT bscan2;
+
+-- internal enable signal for tri-stating the scanbridge
+ CONSTANT jtag_chains : NATURAL := 5;
+ SIGNAL ENABLE_SB : STD_LOGIC;
+ SIGNAL TDO_BSCAN : STD_LOGIC;
+ SIGNAL TDA : STD_LOGIC;
+ SIGNAL TDB : STD_LOGIC;
+ SIGNAL TDC : STD_LOGIC;
+ SIGNAL TDD : STD_LOGIC;
+ SIGNAL MSPTDO_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTCK_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTMS_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+ SIGNAL MSPTRST_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
+
+ BEGIN
+ bscan : COMPONENT bscan2
+ PORT MAP (
+ TDI => TDI,
+ TCK => TCK,
+ TMS => TMS,
+ TRST => TRST,
+ TDO => TDO_BSCAN,
+ ENABLE_MSP => ENABLE_SB,
+ MSPTCK(jtag_chains-1 DOWNTO 0) => MSPTCK_BSCAN,
+ MSPTDI(jtag_chains-1 DOWNTO 0) => MSPTDI,
+ MSPTDO(jtag_chains-1 DOWNTO 0) => MSPTDO_BSCAN,
+ MSPTMS(jtag_chains-1 DOWNTO 0) => MSPTMS_BSCAN,
+ MSPTRST(jtag_chains-1 DOWNTO 0) => MSPTRST_BSCAN,
+ IDN => "0000"
+ );
+
+
+ p_jtagselect: PROCESS(TDI,MSPTDI(jtag_chains-1 DOWNTO 0),TCK,TMS,TRST)
+ BEGIN
+ ENABLE_SB <= '0';
+ MSPTDO(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTCK(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTMS(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+ MSPTRST(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
+
+ IF CTRL(1) = '1' THEN
+ ENABLE_SB <= '1';
+ MSPTDO <= MSPTDO_BSCAN;
+ TDO <= TDO_BSCAN;
+ MSPTCK <= MSPTCK_BSCAN;
+ MSPTMS <= MSPTMS_BSCAN;
+ MSPTRST <= MSPTRST_BSCAN;
+ ELSE
+ IF LPSEL(0) = '0' THEN
+ MSPTDO(0) <= TDI;
+ TDA <= MSPTDI(0);
+ MSPTCK(0) <= TCK;
+ MSPTMS(0) <= TMS;
+ MSPTRST(0) <= TRST;
+ ELSE
+ TDA <= TDI;
+ END IF;
+
+ IF LPSEL(1) = '0' THEN
+ MSPTDO(1) <= TDA;
+ TDB <= MSPTDI(1);
+ MSPTCK(1) <= TCK;
+ MSPTMS(1) <= TMS;
+ MSPTRST(1) <= TRST;
+ ELSE
+ TDB <= TDA;
+ END IF;
+
+ IF LPSEL(2) = '0' THEN
+ MSPTDO(2) <= TDB;
+ TDC <= MSPTDI(2);
+ MSPTCK(2) <= TCK;
+ MSPTMS(2) <= TMS;
+ MSPTRST(2) <= TRST;
+ ELSE
+ TDC <= TDB;
+ END IF;
+
+ IF LPSEL(3) = '0' THEN
+ MSPTDO(3) <= TDC;
+ TDD <= MSPTDI(3);
+ MSPTCK(3) <= TCK;
+ MSPTMS(3) <= TMS;
+ MSPTRST(3) <= TRST;
+ ELSE
+ TDD <= TDC;
+ END IF;
+
+ IF LPSEL(4) = '0' THEN
+ MSPTDO(4) <= TDD;
+ TDO <= MSPTDI(4);
+ MSPTCK(4) <= TCK;
+ MSPTMS(4) <= TMS;
+ MSPTRST(4) <= TRST;
+ ELSE
+ TDO <= TDD;
+ END IF;
+ END IF;
+
+ END PROCESS;
+END str;
+
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
new file mode 100644
index 0000000000..55f1991e7d
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
@@ -0,0 +1,28 @@
+---------------------------------------------------------------------------------
+--
+-- Vhdl file created by I/O Designer
+-- Fri Feb 28 17:51:25 2014
+--
+---------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity jtag_top is
+ port (
+ CTRL : in std_logic_vector (1 downto 0);
+ ENABLE_MSP : in std_logic;
+ IDN : in std_logic_vector (3 downto 0);
+ LPSEL : in std_logic_vector (4 downto 0);
+ MSPTCK : out std_logic_vector (4 downto 0);
+ MSPTDI : in std_logic_vector (4 downto 0);
+ MSPTDO : out std_logic_vector (4 downto 0);
+ MSPTMS : out std_logic_vector (4 downto 0);
+ MSPTRST : out std_logic_vector (4 downto 0);
+ TCK : in std_logic;
+ TDI : in std_logic;
+ TDO : out std_logic;
+ TMS : in std_logic;
+ TRST : in std_logic
+ );
+end jtag_top;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/top_linker.ngo b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/top_linker.ngo
new file mode 100644
index 0000000000000000000000000000000000000000..d06e4838db9f85b95da806848950a2adf8036425
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diff --git a/boards/uniboard2c/lattice_jtag/readme.txt b/boards/uniboard2c/lattice_jtag/readme.txt
new file mode 100644
index 0000000000..6470067819
--- /dev/null
+++ b/boards/uniboard2c/lattice_jtag/readme.txt
@@ -0,0 +1,44 @@
+---------------------------------------------------------------------------
+Background
+---------------------------------------------------------------------------
+The Lattice ECP3 FPGA is used to implement a JTAG scanbrid, the interface between the JTAG Test Access Point on UNB2c and the FPGA's and Ethernet PHY. With dipswitches the bridge can be set in mode:
+- Bridge mode, all FPGA's and Ethernet phy can be accessed using JTAG boundary scan software
+- stitch mode, a selection of parts (like all 4 FPGA) can be stitched in one JTAG chain. This is used for most of our applications
+
+FPGA: LCMXO2-640HC-5TG100C
+
+---------------------------------------------------------------------------
+Tools needed to build JTAG Scanbridge image
+---------------------------------------------------------------------------
+- Diamond Diamond 3.12
+ https://www.latticesemi.com/latticediamond#windows
+- A license is needed. This license is free for 1 year
+ https://www.latticesemi.com/Support/Licensing/DiamondAndiCEcube2SoftwareLicensing/DiamondFree
+
+---------------------------------------------------------------------------
+How to build an Lattice JTAG image
+---------------------------------------------------------------------------
+- Open UNB2_JTAG_SCANBRIDGE.ldf project file with Lattice Diamond.
+- In Process tab, tick "JEDEC File" to make bit file
+- Double click "Export Files"
+
+---------------------------------------------------------------------------
+Make SVF file (used in JTAG Provision to configure the FPGA)
+---------------------------------------------------------------------------
+- Start Programmer
+- Design -> Utilities -> Deployment Tool
+- Function: Files Conversion, Output File Type IEEE 1532 ISC Data File --> OK
+- Click on "SVF" button
+- Add the jed file (hdl/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE_UNB2_JTAG_SCANBRIDGE.jed)
+- Click Next
+- Set:
+ - Flash Erase, Program, Verify
+ - Write Header and Comments
+- Click Next
+- Click Generate
+
+
+
+
+
+
diff --git a/boards/uniboard2c/lettuce_jtag/readme.txt b/boards/uniboard2c/lettuce_jtag/readme.txt
deleted file mode 100644
index 0db68d75ec..0000000000
--- a/boards/uniboard2c/lettuce_jtag/readme.txt
+++ /dev/null
@@ -1 +0,0 @@
-Todo
--
GitLab