From 6887b7889d06ebd805a42d8cef7ed20f52280883 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Wed, 24 Mar 2021 19:54:53 +0100
Subject: [PATCH] modelsim IP models
---
libraries/technology/10gbase_r/hdllib.cfg | 24 +--
.../10gbase_r/tech_10gbase_r_arria10_e2sg.vhd | 24 +--
libraries/technology/clkbuf/hdllib.cfg | 2 +-
libraries/technology/clkbuf/tech_clkbuf.vhd | 2 +-
libraries/technology/ddr/hdllib.cfg | 6 +-
.../technology/ddr/tech_ddr_arria10_e2sg.vhd | 4 +-
libraries/technology/flash/hdllib.cfg | 4 +-
.../flash/tech_flash_asmi_parallel.vhd | 1 +
.../flash/tech_flash_remote_update.vhd | 2 +-
.../technology/fpga_temp_sens/hdllib.cfg | 2 +-
.../fpga_temp_sens/tech_fpga_temp_sens.vhd | 2 +-
.../technology/fpga_voltage_sens/hdllib.cfg | 2 +-
.../tech_fpga_voltage_sens.vhd | 2 +-
.../technology/fractional_pll/hdllib.cfg | 4 +-
.../tech_fractional_pll_clk125.vhd | 2 +-
.../tech_fractional_pll_clk200.vhd | 2 +-
.../alt_em10g32_1930/compile_ip.tcl | 149 ++++++++++++++++
.../hdllib.cfg | 6 +-
.../alt_em10g32_194/compile_ip.tcl | 149 ----------------
.../compile_ip.tcl | 4 +-
.../alt_mem_if_jtag_master_191/hdllib.cfg | 17 ++
.../alt_mem_if_jtag_master_194/hdllib.cfg | 17 --
.../compile_ip.tcl | 5 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 9 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 4 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 4 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 4 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 4 +-
.../hdllib.cfg | 0
.../altera_emif_191/compile_ip.tcl | 152 +++++++++++++++++
.../hdllib.cfg | 8 +-
.../altera_emif_194/compile_ip.tcl | 161 ------------------
.../altera_emif_arch_nf_191/compile_ip.tcl | 97 +++++++++++
.../hdllib.cfg | 6 +-
.../altera_emif_arch_nf_194/compile_ip.tcl | 97 -----------
.../compile_ip.tcl | 16 +-
.../hdllib.cfg | 6 +-
.../altera_eth_tse_1940/hdllib.cfg | 18 +-
.../compile_ip.tcl | 4 +-
.../hdllib.cfg | 6 +-
.../altera_eth_tse_mac_194/compile_ip.tcl | 148 ----------------
.../altera_eth_tse_mac_1940/compile_ip.tcl | 148 ++++++++++++++++
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 14 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 4 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 114 -------------
.../compile_ip.tcl | 114 +++++++++++++
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 116 -------------
.../compile_ip.tcl | 116 +++++++++++++
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 4 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 22 +--
.../altera_jtag_dc_streaming_191/hdllib.cfg | 16 ++
.../altera_jtag_dc_streaming_194/hdllib.cfg | 16 --
.../compile_ip.tcl | 6 +-
.../hdllib.cfg | 8 +-
.../compile_ip.tcl | 16 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 7 +-
.../hdllib.cfg | 6 +-
.../compile_ip.tcl | 23 ++-
.../hdllib.cfg | 8 +-
.../altera_mm_interconnect_194/compile_ip.tcl | 45 -----
.../altera_remote_update_1910/hdllib.cfg | 3 +-
.../altera_remote_update_core_1910/hdllib.cfg | 6 +-
.../compile_ip.tcl | 8 +-
.../altera_reset_controller_191/hdllib.cfg | 16 ++
.../altera_reset_controller_194/hdllib.cfg | 16 --
.../compile_ip.tcl | 38 ++---
.../hdllib.cfg | 6 +-
.../altera_xcvr_native_a10_191/compile_ip.tcl | 108 ++++++++++++
.../altera_xcvr_native_a10_191/hdllib.cfg | 16 ++
.../altera_xcvr_native_a10_194/compile_ip.tcl | 108 ------------
.../altera_xcvr_native_a10_194/hdllib.cfg | 16 --
.../compile_ip.tcl | 18 +-
.../altera_xcvr_reset_control_191/hdllib.cfg | 16 ++
.../altera_xcvr_reset_control_194/hdllib.cfg | 16 --
.../compile_ip.tcl | 6 +-
.../hdllib.cfg | 6 +-
.../hdllib.cfg | 16 --
.../compile_ip.tcl | 4 +-
.../hdllib.cfg | 6 +-
.../complex_mult/compile_ip.tcl | 6 +-
.../ip_arria10_e2sg/complex_mult/hdllib.cfg | 2 +-
.../ip_arria10_e2sg/ddio/compile_ip.tcl | 16 +-
.../ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg | 4 +-
.../ip_arria10_e2sg/mac_10g/hdllib.cfg | 4 +-
.../ip_arria10_e2sg/mult_add4/compile_ip.tcl | 4 +-
.../ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg | 4 +-
.../phy_10gbase_r_12/hdllib.cfg | 4 +-
.../phy_10gbase_r_24/hdllib.cfg | 4 +-
.../phy_10gbase_r_3/hdllib.cfg | 4 +-
.../phy_10gbase_r_4/hdllib.cfg | 4 +-
.../phy_10gbase_r_48/hdllib.cfg | 4 +-
.../ip_arria10_e2sg/temp_sense/compile_ip.tcl | 4 +-
.../ip_arria10_e2sg/temp_sense/hdllib.cfg | 2 +-
.../transceiver_pll_10g/hdllib.cfg | 4 +-
.../transceiver_reset_controller_1/hdllib.cfg | 4 +-
.../hdllib.cfg | 4 +-
.../hdllib.cfg | 4 +-
.../transceiver_reset_controller_3/hdllib.cfg | 4 +-
.../transceiver_reset_controller_4/hdllib.cfg | 4 +-
.../hdllib.cfg | 4 +-
.../voltage_sense/compile_ip.tcl | 20 +--
libraries/technology/jesd204b/hdllib.cfg | 2 +-
libraries/technology/mac_10g/hdllib.cfg | 2 +-
.../mac_10g/tech_mac_10g_arria10_e2sg.vhd | 2 +-
libraries/technology/mult/hdllib.cfg | 2 +-
.../technology/mult/tech_complex_mult.vhd | 2 +-
libraries/technology/pll/hdllib.cfg | 8 +-
libraries/technology/pll/tech_pll_clk125.vhd | 2 +-
libraries/technology/pll/tech_pll_clk200.vhd | 2 +-
libraries/technology/pll/tech_pll_clk25.vhd | 2 +-
.../pll/tech_pll_xgmii_mac_clocks.vhd | 2 +-
libraries/technology/tse/hdllib.cfg | 4 +-
.../technology/tse/tech_tse_arria10_e2sg.vhd | 4 +-
125 files changed, 1280 insertions(+), 1348 deletions(-)
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{alt_em10g32_194 => alt_em10g32_1930}/hdllib.cfg (78%)
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/compile_ip.tcl
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{alt_mem_if_jtag_master_194 => alt_mem_if_jtag_master_191}/compile_ip.tcl (88%)
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/hdllib.cfg
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_mm_bridge_194 => altera_avalon_mm_bridge_191}/compile_ip.tcl (79%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_mm_bridge_194 => altera_avalon_mm_bridge_191}/hdllib.cfg (76%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{e2sg_altera_merlin_master_translator_194 => altera_avalon_onchip_memory2_1920}/compile_ip.tcl (83%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_onchip_memory2_194 => altera_avalon_onchip_memory2_1920}/hdllib.cfg (56%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_packets_to_master_194 => altera_avalon_packets_to_master_1910}/compile_ip.tcl (89%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_packets_to_master_194 => altera_avalon_packets_to_master_1910}/hdllib.cfg (70%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_sc_fifo_194 => altera_avalon_sc_fifo_191}/compile_ip.tcl (90%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_sc_fifo_194 => altera_avalon_sc_fifo_191}/hdllib.cfg (60%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_st_bytes_to_packets_194 => altera_avalon_st_bytes_to_packets_1910}/compile_ip.tcl (89%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_st_bytes_to_packets_194 => altera_avalon_st_bytes_to_packets_1910}/hdllib.cfg (69%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_st_packets_to_bytes_194 => altera_avalon_st_packets_to_bytes_1910}/compile_ip.tcl (89%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_st_packets_to_bytes_194 => altera_avalon_st_packets_to_bytes_1910}/hdllib.cfg (100%)
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/compile_ip.tcl
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_emif_194 => altera_emif_191}/hdllib.cfg (60%)
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/compile_ip.tcl
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_emif_arch_nf_194 => altera_emif_arch_nf_191}/hdllib.cfg (75%)
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/compile_ip.tcl
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_emif_cal_slave_nf_194 => altera_emif_cal_slave_nf_191}/compile_ip.tcl (62%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_emif_cal_slave_nf_194 => altera_emif_cal_slave_nf_191}/hdllib.cfg (58%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_eth_tse_avalon_arbiter_194 => altera_eth_tse_avalon_arbiter_1940}/compile_ip.tcl (87%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_eth_tse_avalon_arbiter_194 => altera_eth_tse_avalon_arbiter_1940}/hdllib.cfg (71%)
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/compile_ip.tcl
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_eth_tse_mac_194 => altera_eth_tse_mac_1940}/hdllib.cfg (60%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_eth_tse_nf_lvds_terminator_194 => altera_eth_tse_nf_lvds_terminator_1940}/compile_ip.tcl (62%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_eth_tse_nf_lvds_terminator_194 => altera_eth_tse_nf_lvds_terminator_1940}/hdllib.cfg (69%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_eth_tse_nf_phyip_terminator_194 => altera_eth_tse_nf_phyip_terminator_1940}/compile_ip.tcl (86%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_eth_tse_nf_phyip_terminator_194 => altera_eth_tse_nf_phyip_terminator_1940}/hdllib.cfg (83%)
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/compile_ip.tcl
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_eth_tse_pcs_pma_nf_lvds_194 => altera_eth_tse_pcs_pma_nf_lvds_1940}/hdllib.cfg (70%)
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/compile_ip.tcl
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_eth_tse_pcs_pma_nf_phyip_194 => altera_eth_tse_pcs_pma_nf_phyip_1940}/hdllib.cfg (70%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_ip_col_if_194 => altera_ip_col_if_191}/compile_ip.tcl (90%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_ip_col_if_194 => altera_ip_col_if_191}/hdllib.cfg (62%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_jtag_dc_streaming_194 => altera_jtag_dc_streaming_191}/compile_ip.tcl (65%)
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/hdllib.cfg
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_lvds_194 => altera_lvds_1930}/compile_ip.tcl (83%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_lvds_194 => altera_lvds_1930}/hdllib.cfg (53%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_lvds_core20_194 => altera_lvds_core20_191}/compile_ip.tcl (66%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_lvds_core20_194 => altera_lvds_core20_191}/hdllib.cfg (61%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_merlin_slave_translator_194 => altera_merlin_slave_translator_191}/compile_ip.tcl (86%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_merlin_slave_translator_194 => altera_merlin_slave_translator_191}/hdllib.cfg (71%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_avalon_onchip_memory2_194 => altera_mm_interconnect_191}/compile_ip.tcl (55%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_mm_interconnect_194 => altera_mm_interconnect_191}/hdllib.cfg (56%)
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/compile_ip.tcl
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_reset_controller_194 => altera_reset_controller_191}/compile_ip.tcl (85%)
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/hdllib.cfg
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_xcvr_atx_pll_a10_194 => altera_xcvr_atx_pll_a10_191}/compile_ip.tcl (75%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_xcvr_atx_pll_a10_194 => altera_xcvr_atx_pll_a10_191}/hdllib.cfg (59%)
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/hdllib.cfg
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_xcvr_reset_control_194 => altera_xcvr_reset_control_191}/compile_ip.tcl (75%)
create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/hdllib.cfg
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{channel_adapter_194 => channel_adapter_191}/compile_ip.tcl (82%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{channel_adapter_194 => channel_adapter_191}/hdllib.cfg (62%)
delete mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/hdllib.cfg
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{timing_adapter_194 => timing_adapter_191}/compile_ip.tcl (90%)
rename libraries/technology/ip_arria10_e2sg/altera_libraries/{timing_adapter_194 => timing_adapter_191}/hdllib.cfg (63%)
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 46c9db4f40..a47d986b91 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -53,18 +53,18 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
ip_arria10_e2sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
- ip_arria10_e2sg_phy_10gbase_r ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_194
- ip_arria10_e2sg_phy_10gbase_r_3 ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_194
- ip_arria10_e2sg_phy_10gbase_r_4 ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_194
- ip_arria10_e2sg_phy_10gbase_r_12 ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_194
- ip_arria10_e2sg_phy_10gbase_r_24 ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_194
- ip_arria10_e2sg_phy_10gbase_r_48 ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_194
- ip_arria10_e2sg_transceiver_pll_10g ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194
- ip_arria10_e2sg_transceiver_reset_controller_1 ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_194
- ip_arria10_e2sg_transceiver_reset_controller_3 ip_arria10_e2sg_transceiver_reset_controller_3_altera_xcvr_reset_control_194
- ip_arria10_e2sg_transceiver_reset_controller_4 ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_194
- ip_arria10_e2sg_transceiver_reset_controller_12 ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_194
- ip_arria10_e2sg_transceiver_reset_controller_24 ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_194
+ ip_arria10_e2sg_phy_10gbase_r ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191
+ ip_arria10_e2sg_phy_10gbase_r_3 ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_191
+ ip_arria10_e2sg_phy_10gbase_r_4 ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_191
+ ip_arria10_e2sg_phy_10gbase_r_12 ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_191
+ ip_arria10_e2sg_phy_10gbase_r_24 ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_191
+ ip_arria10_e2sg_phy_10gbase_r_48 ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_191
+ ip_arria10_e2sg_transceiver_pll_10g ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_191
+ ip_arria10_e2sg_transceiver_reset_controller_1 ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_191
+ ip_arria10_e2sg_transceiver_reset_controller_3 ip_arria10_e2sg_transceiver_reset_controller_3_altera_xcvr_reset_control_191
+ ip_arria10_e2sg_transceiver_reset_controller_4 ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_191
+ ip_arria10_e2sg_transceiver_reset_controller_12 ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_191
+ ip_arria10_e2sg_transceiver_reset_controller_24 ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_191
synth_files =
sim_10gbase_r.vhd
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
index 04ece135be..4f31d0974f 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
@@ -21,18 +21,18 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_194;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_194;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_194;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_194;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_194;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_194;
-LIBRARY ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_194;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_194;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_194;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_194;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_194;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_191;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_191;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_191;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_191;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_191;
+LIBRARY ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_191;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_191;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_191;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_191;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_191;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_191;
LIBRARY IEEE, tech_pll_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index c5e8d11c97..cd94b1cb4b 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -8,7 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_180
- ip_arria10_e2sg_clkbuf_global ip_arria10_e2sg_clkbuf_global_altclkctrl_194
+ ip_arria10_e2sg_clkbuf_global ip_arria10_e2sg_clkbuf_global_altclkctrl_191
synth_files =
tech_clkbuf_component_pkg.vhd
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index e7215bbb25..817998a412 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_180;
-LIBRARY ip_arria10_e2sg_clkbuf_global_altclkctrl_194;
+LIBRARY ip_arria10_e2sg_clkbuf_global_altclkctrl_191;
ENTITY tech_clkbuf IS
GENERIC (
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index 730e3de813..27d142f6aa 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -19,7 +19,7 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master
ip_arria10_e1sg_ddr4_4g_2000
ip_arria10_e1sg_ddr4_8g_2400
ip_arria10_e2sg_ddr4_8g_1600
- ip_arria10_e2sg_ddr4_8g_2400
+# ip_arria10_e2sg_ddr4_8g_2400
hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model
ip_arria10_ddr4_mem_model_141
hdl_lib_technology =
@@ -43,8 +43,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
- ip_arria10_e2sg_ddr4_8g_1600 ip_arria10_e2sg_ddr4_8g_1600_altera_emif_194
- ip_arria10_e2sg_ddr4_8g_2400 ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194
+ ip_arria10_e2sg_ddr4_8g_1600 ip_arria10_e2sg_ddr4_8g_1600_altera_emif_191
+# ip_arria10_e2sg_ddr4_8g_2400 ip_arria10_e2sg_ddr4_8g_2400_altera_emif_191
synth_files =
tech_ddr_pkg.vhd
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
index 7d5becab3b..7f91e1c9d8 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
@@ -34,8 +34,8 @@
-- DDR interface monitoring purposes.
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e2sg_ddr4_8g_1600_altera_emif_194;
-LIBRARY ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194;
+LIBRARY ip_arria10_e2sg_ddr4_8g_1600_altera_emif_191;
+--LIBRARY ip_arria10_e2sg_ddr4_8g_2400_altera_emif_191;
LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index 8c7d702d6c..e3bf434a4c 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -20,8 +20,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180
ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_180
- ip_arria10_e2sg_asmi_parallel ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_194
- ip_arria10_e2sg_remote_update ip_arria10_e2sg_remote_update_altera_remote_update_194
+ ip_arria10_e2sg_asmi_parallel ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_1910
+ ip_arria10_e2sg_remote_update ip_arria10_e2sg_remote_update_altera_remote_update_1910
synth_files =
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index a6ed43c72f..b6979cc495 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -32,6 +32,7 @@ LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
--LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180;
+LIBRARY ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_1910;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 3933fc69e2..5d668f11b5 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -32,7 +32,7 @@ LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
-LIBRARY ip_arria10_e2sg_remote_update_altera_remote_update_194;
+LIBRARY ip_arria10_e2sg_remote_update_altera_remote_update_1910;
ENTITY tech_flash_remote_update IS
GENERIC (
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index c9708019d4..c5d580851e 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -8,7 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_temp_sense ip_arria10_temp_sense_altera_temp_sense_150
ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_180
- ip_arria10_e2sg_temp_sense ip_arria10_e2sg_temp_sense_altera_temp_sense_194
+ ip_arria10_e2sg_temp_sense ip_arria10_e2sg_temp_sense_altera_temp_sense_1910
synth_files =
tech_fpga_temp_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index f9e6e9d018..4708a81596 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -30,7 +30,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_180;
-LIBRARY ip_arria10_e2sg_temp_sense_altera_temp_sense_194;
+LIBRARY ip_arria10_e2sg_temp_sense_altera_temp_sense_1910;
ENTITY tech_fpga_temp_sens IS
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index 1e6af4d667..c4faf23f3d 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -8,7 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_voltage_sense ip_arria10_voltage_sense_altera_voltage_sense_150
ip_arria10_e3sge3_voltage_sense ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180
- ip_arria10_e2sg_voltage_sense ip_arria10_e2sg_voltage_sense_altera_voltage_sense_194
+ ip_arria10_e2sg_voltage_sense ip_arria10_e2sg_voltage_sense_altera_voltage_sense_1910
synth_files =
tech_fpga_voltage_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index efdfb2b45b..e67b45a399 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180;
-LIBRARY ip_arria10_e2sg_voltage_sense_altera_voltage_sense_194;
+LIBRARY ip_arria10_e2sg_voltage_sense_altera_voltage_sense_1910;
ENTITY tech_fpga_voltage_sens IS
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index eeea28b0f5..389b5b32ad 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -14,8 +14,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180
ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180
- ip_arria10_e2sg_fractional_pll_clk200 ip_arria10_e2sg_fractional_pll_clk200_altera_xcvr_fpll_a10_194
- ip_arria10_e2sg_fractional_pll_clk125 ip_arria10_e2sg_fractional_pll_clk125_altera_xcvr_fpll_a10_194
+ ip_arria10_e2sg_fractional_pll_clk200 ip_arria10_e2sg_fractional_pll_clk200_altera_xcvr_fpll_a10_191
+ ip_arria10_e2sg_fractional_pll_clk125 ip_arria10_e2sg_fractional_pll_clk125_altera_xcvr_fpll_a10_191
synth_files =
tech_fractional_pll_component_pkg.vhd
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 1234aff5b8..416cfaad64 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180;
-LIBRARY ip_arria10_e2sg_fractional_pll_clk125_altera_xcvr_fpll_a10_194;
+LIBRARY ip_arria10_e2sg_fractional_pll_clk125_altera_xcvr_fpll_a10_191;
ENTITY tech_fractional_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 5ad3783021..93a08d7957 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180;
-LIBRARY ip_arria10_e2sg_fractional_pll_clk200_altera_xcvr_fpll_a10_194;
+LIBRARY ip_arria10_e2sg_fractional_pll_clk200_altera_xcvr_fpll_a10_191;
ENTITY tech_fractional_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
new file mode 100644
index 0000000000..bbaaa7d7bd
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
@@ -0,0 +1,149 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
+
+vmap alt_em10g32_1930 ./work/
+
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/alt_em10g32.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/alt_em10g32unit.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_crc32.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_creg_map.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_creg_top.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_top.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rr_buffer.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_top.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/alt_em10g32_avalon_dc_fifo.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/alt_em10g32_dcfifo_synchronizer_bundle.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/alt_em10g32_std_synchronizer.v" -work alt_em10g32_1930
+ vlog "$IP_DIR/../alt_em10g32_1930/sim/altera_std_synchronizer_nocut.v" -work alt_em10g32_1930
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg
similarity index 78%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg
index afa218082e..4f6dac9d70 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_alt_em10g32_194
-hdl_library_clause_name = alt_em10g32_194
+hdl_lib_name = ip_arria10_e2sg_alt_em10g32_1930
+hdl_library_clause_name = alt_em10g32_1930
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -14,7 +14,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/compile_ip.tcl
deleted file mode 100644
index f2cbafc14d..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/compile_ip.tcl
+++ /dev/null
@@ -1,149 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
-
-vmap alt_em10g32_194 ./work/
-
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/alt_em10g32.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/alt_em10g32unit.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc32.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_creg_map.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_creg_top.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_top.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rr_buffer.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_top.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/alt_em10g32_avalon_dc_fifo.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/alt_em10g32_dcfifo_synchronizer_bundle.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/alt_em10g32_std_synchronizer.v" -work alt_em10g32_194
- vlog "$IP_DIR/../alt_em10g32_194/sim/altera_std_synchronizer_nocut.v" -work alt_em10g32_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
similarity index 88%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
index bee3382d48..d536e4a4db 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
@@ -32,7 +32,7 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap alt_mem_if_jtag_master_194 ./work/
+vmap alt_mem_if_jtag_master_191 ./work/
- vcom "$IP_DIR/../alt_mem_if_jtag_master_194/sim/ip_arria10_e2sg_ddr4_8g_1600_alt_mem_if_jtag_master_194_5ftfrmy.vhd" -work alt_mem_if_jtag_master_194
+ vcom "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_8g_1600_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
new file mode 100644
index 0000000000..ce9e3f19d8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_alt_mem_if_jtag_master_191
+hdl_library_clause_name = alt_mem_if_jtag_master_191
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_timing_adapter_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_altera_reset_controller_191
+
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/hdllib.cfg
deleted file mode 100644
index 0095249141..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e2sg_alt_mem_if_jtag_master_194
-hdl_library_clause_name = alt_mem_if_jtag_master_194
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_jtag_dc_streaming_194 ip_arria10_e2sg_timing_adapter_194 ip_arria10_e2sg_altera_avalon_sc_fifo_194 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_194 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_194 ip_arria10_e2sg_altera_avalon_packets_to_master_194 ip_arria10_e2sg_channel_adapter_194 ip_arria10_e2sg_altera_reset_controller_194
-
-hdl_lib_technology = ip_arria10_e2sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
similarity index 79%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
index a307e87a54..e1408439bc 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
@@ -30,6 +30,7 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
-vmap altera_avalon_mm_bridge_194 ./work/
+vmap altera_avalon_mm_bridge_191 ./work/
- vlog "$IP_DIR/../altera_avalon_mm_bridge_194/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_194
+# vlog "$IP_DIR/../altera_avalon_mm_bridge_191/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_191
+ vlog "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v" -work altera_avalon_mm_bridge_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg
similarity index 76%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg
index bb5bf29a49..a61c85e5fd 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_avalon_mm_bridge_194
-hdl_library_clause_name = altera_avalon_mm_bridge_194
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_mm_bridge_191
+hdl_library_clause_name = altera_avalon_mm_bridge_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -14,7 +14,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
similarity index 83%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
index 7561dff1be..ca1baf3877 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
@@ -28,9 +28,10 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+vmap altera_avalon_onchip_memory2_1920 ./work/
-vmap altera_merlin_master_translator_194 ./work/
-
- vlog -sv "$IP_DIR/../altera_merlin_master_translator_194/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_194
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
+
+# copy previous 'set' and 'vcom' lines to include more ddr4 variants
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg
similarity index 56%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg
index 67c433f39b..ef094f0caf 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_avalon_onchip_memory2_194
-hdl_library_clause_name = altera_avalon_onchip_memory2_194
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_onchip_memory2_1920
+hdl_library_clause_name = altera_avalon_onchip_memory2_1920
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
similarity index 89%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
index 11f0931fdb..e66734a9be 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
@@ -32,6 +32,6 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap altera_avalon_packets_to_master_194 ./work/
+vmap altera_avalon_packets_to_master_1910 ./work/
- vlog "$IP_DIR/../altera_avalon_packets_to_master_194/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_194
+ vlog "$IP_DIR/../altera_avalon_packets_to_master_1910/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg
similarity index 70%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg
index eb49528555..94aa088939 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_avalon_packets_to_master_194
-hdl_library_clause_name = altera_avalon_packets_to_master_194
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_packets_to_master_1910
+hdl_library_clause_name = altera_avalon_packets_to_master_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
similarity index 90%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
index 0bfd4ac5df..092a26e155 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
@@ -32,8 +32,8 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap altera_avalon_sc_fifo_194 ./work/
- vlog "$IP_DIR/../altera_avalon_sc_fifo_194/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_194
+vmap altera_avalon_sc_fifo_191 ./work/
+ vlog "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_sc_fifo_191_e5eqkcq.v" -work altera_avalon_sc_fifo_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg
similarity index 60%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg
index 53ab04b9e2..431d59b521 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_avalon_sc_fifo_194
-hdl_library_clause_name = altera_avalon_sc_fifo_194
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_sc_fifo_191
+hdl_library_clause_name = altera_avalon_sc_fifo_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
similarity index 89%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
index d5c7116116..0e6cdc7f45 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
@@ -32,6 +32,6 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap altera_avalon_st_bytes_to_packets_194 ./work/
+vmap altera_avalon_st_bytes_to_packets_1910 ./work/
- vlog "$IP_DIR/../altera_avalon_st_bytes_to_packets_194/sim/altera_avalon_st_bytes_to_packets.v" -work altera_avalon_st_bytes_to_packets_194
+ vlog "$IP_DIR/../altera_avalon_st_bytes_to_packets_1910/sim/altera_avalon_st_bytes_to_packets.v" -work altera_avalon_st_bytes_to_packets_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg
similarity index 69%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg
index 739e6e61ea..963c12636c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_194
-hdl_library_clause_name = altera_avalon_st_bytes_to_packets_194
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910
+hdl_library_clause_name = altera_avalon_st_bytes_to_packets_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
similarity index 89%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
index 3102573ba0..98ea21838a 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
@@ -31,9 +31,9 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap altera_avalon_st_packets_to_bytes_194 ./work/
+vmap altera_avalon_st_packets_to_bytes_1910 ./work/
- vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_194/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_194
+ vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_1910/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
similarity index 100%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/compile_ip.tcl
new file mode 100644
index 0000000000..297065a0ab
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/compile_ip.tcl
@@ -0,0 +1,152 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+#
+vmap altera_emif_1910 ./work/
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+# vlog "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_194_dzobyri.v" -work altera_emif_194
+
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000sim"
+# vlog "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_194_lwknerq.v" -work altera_emif_194
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+ vlog "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910_jhcj6zy.vhd" -work altera_emif_1910
+
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+# vlog "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194_nz3mdxa.v" -work altera_emif_194
+
+vmap altera_emif_arch_nf_191 ./work/
+# ddr4_4g_1600
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+#
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_top.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y.sv" -work altera_emif_arch_nf_194
+
+# ddr4_4g_2000
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+#
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_top.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy.sv" -work altera_emif_arch_nf_194
+
+# ddr4_8g_1600
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_top.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_io_aux.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq.vhd" -work altera_emif_arch_nf_191
+
+# ddr4_8g_2400
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+#
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_top.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i.sv" -work altera_emif_arch_nf_194
+
+# common dependencies
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_oct.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_191
+ vlog "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_191
+
+vmap altera_emif_cal_slave_nf_191 ./work/
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+# vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
+
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+# vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+ vlog "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
+
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+# vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
+
+vmap altera_reset_controller_191 ./work/
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+ vlog "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_191
+ vlog "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_191
+
+vmap altera_mm_interconnect_191 ./work/
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+ vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_3yb4cia.vhd" -work altera_mm_interconnect_191
+ vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd" -work altera_mm_interconnect_191
+ vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd" -work altera_mm_interconnect_191
+
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+# vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
+
+vmap altera_avalon_onchip_memory2_1920 ./work/
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
+
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+# vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+# vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+
+vmap altera_avalon_mm_bridge_191 ./work/
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+ vlog "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v" -work altera_avalon_mm_bridge_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/hdllib.cfg
similarity index 60%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/hdllib.cfg
index 7cd50e438d..b61691a814 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/hdllib.cfg
@@ -1,7 +1,7 @@
-hdl_lib_name = ip_arria10_e2sg_altera_emif_194
-hdl_library_clause_name = altera_emif_194
+hdl_lib_name = ip_arria10_e2sg_altera_emif_191
+hdl_library_clause_name = altera_emif_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_194 ip_arria10_e2sg_altera_merlin_slave_translator_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_merlin_slave_translator_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/compile_ip.tcl
deleted file mode 100644
index 23ab9cbfdd..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/compile_ip.tcl
+++ /dev/null
@@ -1,161 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-vmap altera_emif_194 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
- vlog "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_194_dzobyri.v" -work altera_emif_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000sim"
- vlog "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_194_lwknerq.v" -work altera_emif_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
- vlog "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_194_ebfu2ha.v" -work altera_emif_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
- vlog "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194_nz3mdxa.v" -work altera_emif_194
-
-vmap altera_emif_arch_nf_194 ./work/
-# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_top.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y.sv" -work altera_emif_arch_nf_194
-
-# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_top.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy.sv" -work altera_emif_arch_nf_194
-
-# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi_top.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi_io_aux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi.sv" -work altera_emif_arch_nf_194
-
-# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_top.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i.sv" -work altera_emif_arch_nf_194
-
-# common dependencies
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_oct.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_194
- vlog "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_194
-
-vmap altera_emif_cal_slave_nf_194 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
-
-vmap altera_reset_controller_194 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
- vlog "$IP_DIR/../altera_reset_controller_194/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_194
- vlog "$IP_DIR/../altera_reset_controller_194/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_194
-
-vmap altera_mm_interconnect_194 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_ibrpcbq.vhd" -work altera_mm_interconnect_194
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_mtvmp4i.vhd" -work altera_mm_interconnect_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
-
-vmap altera_avalon_onchip_memory2_194 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
-
-
-vmap altera_avalon_mm_bridge_194 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
- vlog "$IP_DIR/../altera_avalon_mm_bridge_194/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
new file mode 100644
index 0000000000..e3828ad679
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
@@ -0,0 +1,97 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+vmap altera_emif_arch_nf_191 ./work/
+# ddr4_4g_1600
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+#
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_top.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y.sv" -work altera_emif_arch_nf_194
+
+# ddr4_4g_2000
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+#
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_top.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy.sv" -work altera_emif_arch_nf_194
+
+# ddr4_8g_1600
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_top.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_io_aux.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq.vhd" -work altera_emif_arch_nf_191
+
+# ddr4_8g_2400
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+#
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_top.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_194
+# vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i.sv" -work altera_emif_arch_nf_194
+
+# common dependencies
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_oct.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_191
+ vlog "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg
similarity index 75%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg
index d491e596f2..64324b44d8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_emif_arch_nf_194
-hdl_library_clause_name = altera_emif_arch_nf_194
+hdl_lib_name = ip_arria10_e2sg_altera_emif_arch_nf_191
+hdl_library_clause_name = altera_emif_arch_nf_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -14,7 +14,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/compile_ip.tcl
deleted file mode 100644
index ff633035c4..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/compile_ip.tcl
+++ /dev/null
@@ -1,97 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_emif_arch_nf_194 ./work/
-# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_top.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y.sv" -work altera_emif_arch_nf_194
-
-# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_top.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy.sv" -work altera_emif_arch_nf_194
-
-# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi_top.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi_io_aux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi.sv" -work altera_emif_arch_nf_194
-
-# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_top.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i.sv" -work altera_emif_arch_nf_194
-
-# common dependencies
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_oct.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_194
- vlog "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_194
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_194/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
similarity index 62%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
index 9d9d4760dc..6d30c9b1f8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
@@ -29,17 +29,17 @@
#vlib ./work/ ;# Assume library work already exist
#
-vmap altera_emif_cal_slave_nf_194 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
+vmap altera_emif_cal_slave_nf_191 ./work/
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+# vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+# vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
+ vlog "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+# vlog "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_cal_slave_nf_194_efslyyq.v" -work altera_emif_cal_slave_nf_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
similarity index 58%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
index 907d0bce85..a26e9d4fef 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_emif_cal_slave_nf_194
-hdl_library_clause_name = altera_emif_cal_slave_nf_194
+hdl_lib_name = ip_arria10_e2sg_altera_emif_cal_slave_nf_191
+hdl_library_clause_name = altera_emif_cal_slave_nf_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg
index 826694211e..4b557fb62b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg
@@ -2,15 +2,15 @@ hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_1940
hdl_library_clause_name = altera_eth_tse_1940
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-ip_arria10_e2sg_altera_eth_tse_mac_194
-ip_arria10_e2sg_altera_eth_tse_avalon_arbiter_194
-ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_phyip_194
-ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_lvds_194
-ip_arria10_e2sg_altera_xcvr_native_a10_194
-ip_arria10_e2sg_altera_eth_tse_nf_phyip_terminator_194
-ip_arria10_e2sg_altera_eth_tse_nf_lvds_terminator_194
-ip_arria10_e2sg_altera_lvds_194
-ip_arria10_e2sg_altera_reset_controller_194
+ip_arria10_e2sg_altera_eth_tse_mac_1940
+ip_arria10_e2sg_altera_eth_tse_avalon_arbiter_1940
+ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_phyip_1940
+ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_lvds_1940
+ip_arria10_e2sg_altera_xcvr_native_a10_191
+ip_arria10_e2sg_altera_eth_tse_nf_phyip_terminator_1940
+ip_arria10_e2sg_altera_eth_tse_nf_lvds_terminator_1940
+ip_arria10_e2sg_altera_lvds_1930
+ip_arria10_e2sg_altera_reset_controller_191
hdl_lib_technology = ip_arria10_e2sg
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
similarity index 87%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
index d33aee121e..9e546e6e0f 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
@@ -29,5 +29,5 @@
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
-vmap altera_eth_tse_avalon_arbiter_194 ./work/
- vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_194/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_194
+vmap altera_eth_tse_avalon_arbiter_1940 ./work/
+ vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_1940/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_1940
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg
similarity index 71%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg
index eae52be1ef..049eaf9ba4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_avalon_arbiter_194
-hdl_library_clause_name = altera_eth_tse_avalon_arbiter_194
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_avalon_arbiter_1940
+hdl_library_clause_name = altera_eth_tse_avalon_arbiter_1940
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/compile_ip.tcl
deleted file mode 100644
index 661bfc95de..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/compile_ip.tcl
+++ /dev/null
@@ -1,148 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
-
-vmap altera_eth_tse_mac_194 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_eth_tse_mac.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_clk_cntl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_crc328checker.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_crc328generator.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_crc32ctl8.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_crc32galois8.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_gmii_io.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_lb_read_cntl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_lb_wrt_cntl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_hashing.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_host_control.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_host_control_small.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mac_control.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_register_map.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_register_map_small.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_counter_cntl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_shared_mac_control.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_shared_register_map.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_counter_cntl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_lfsr_10.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_loopback_ff.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_altshifttaps.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_fifoless_mac_rx.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mac_rx.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_fifoless_mac_tx.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mac_tx.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_magic_detection.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mdio.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mdio_clk_gen.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mdio_cntl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_mdio.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mii_rx_if.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mii_tx_if.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_pipeline_base.v" -work altera_eth_tse_mac_194
- vlog -sv "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_pipeline_stage.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_dpram_16x32.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_dpram_8x32.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_dpram_ecc_16x32.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_fifoless_retransmit_cntl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_retransmit_cntl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_in1.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_in4.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_nf_rgmii_module.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_module.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_out1.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_out4.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_min_ff.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff_cntrl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff_cntrl_32.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff_length.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_stat_extract.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_timing_adapter32.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_timing_adapter8.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_timing_adapter_fifo32.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_timing_adapter_fifo8.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_1geth.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_fifoless_1geth.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_w_fifo.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_wo_fifo.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_gen_host.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_min_ff.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_cntrl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_cntrl_32.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_length.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_read_cntl.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_stat_extract.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_mac_194
- vlog -sv "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_mac_194
- vlog "$IP_DIR/../altera_eth_tse_mac_194/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_mac_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
new file mode 100644
index 0000000000..7a862ebf8a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
@@ -0,0 +1,148 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+
+vmap altera_eth_tse_mac_1940 ./work/
+
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_1940/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_eth_tse_mac.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_clk_cntl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_crc328checker.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_crc328generator.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_crc32ctl8.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_crc32galois8.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_gmii_io.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_lb_read_cntl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_lb_wrt_cntl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_hashing.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_host_control.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_host_control_small.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_mac_control.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_register_map.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_register_map_small.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rx_counter_cntl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_shared_mac_control.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_shared_register_map.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_tx_counter_cntl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_lfsr_10.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_loopback_ff.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_altshifttaps.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_fifoless_mac_rx.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_mac_rx.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_fifoless_mac_tx.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_mac_tx.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_magic_detection.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_mdio.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_mdio_clk_gen.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_mdio_cntl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_top_mdio.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_mii_rx_if.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_mii_tx_if.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_pipeline_base.v" -work altera_eth_tse_mac_1940
+ vlog -sv "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_pipeline_stage.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_dpram_16x32.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_dpram_8x32.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_dpram_ecc_16x32.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_fifoless_retransmit_cntl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_retransmit_cntl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rgmii_in1.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rgmii_in4.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_nf_rgmii_module.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rgmii_module.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rgmii_out1.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rgmii_out4.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rx_ff.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rx_min_ff.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rx_ff_cntrl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rx_ff_cntrl_32.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rx_ff_length.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_rx_stat_extract.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_timing_adapter32.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_timing_adapter8.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_timing_adapter_fifo32.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_timing_adapter_fifo8.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_top_1geth.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_top_fifoless_1geth.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_top_w_fifo.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_top_wo_fifo.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_top_gen_host.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_tx_ff.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_tx_min_ff.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_tx_ff_cntrl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_tx_ff_cntrl_32.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_tx_ff_length.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_tx_ff_read_cntl.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_tx_stat_extract.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_mac_1940
+ vlog -sv "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_mac_1940
+ vlog "$IP_DIR/../altera_eth_tse_mac_1940/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_mac_1940
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg
similarity index 60%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg
index a166248660..29fc00d681 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_mac_194
-hdl_library_clause_name = altera_eth_tse_mac_194
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_mac_1940
+hdl_library_clause_name = altera_eth_tse_mac_1940
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
similarity index 62%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
index 200fb828e3..f22ce117ca 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
@@ -29,12 +29,12 @@
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
-vmap altera_eth_tse_nf_lvds_terminator_194 ./work/
+vmap altera_eth_tse_nf_lvds_terminator_1940 ./work/
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_194
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_eth_tse_nf_lvds_terminator.v" -work altera_eth_tse_nf_lvds_terminator_194
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_194
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_tse_nf_lvds_channel_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_194
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_tse_nf_lvds_common_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_194
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_nf_lvds_terminator_194
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_1940/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_1940
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_1940/sim/mentor/altera_eth_tse_nf_lvds_terminator.v" -work altera_eth_tse_nf_lvds_terminator_1940
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_1940/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_1940
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_1940/sim/mentor/altera_tse_nf_lvds_channel_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_1940
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_1940/sim/mentor/altera_tse_nf_lvds_common_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_1940
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_1940/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_nf_lvds_terminator_1940
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg
similarity index 69%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg
index 730217235b..01efe26fe3 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_nf_lvds_terminator_194
-hdl_library_clause_name = altera_eth_tse_nf_lvds_terminator_194
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_nf_lvds_terminator_1940
+hdl_library_clause_name = altera_eth_tse_nf_lvds_terminator_1940
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
similarity index 86%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
index 43a5ebafda..a19f408746 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
@@ -30,6 +30,6 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
-vmap altera_eth_tse_nf_phyip_terminator_194 ./work/
+vmap altera_eth_tse_nf_phyip_terminator_1940 ./work/
- vlog "$IP_DIR/../altera_eth_tse_nf_phyip_terminator_194/sim/mentor/altera_eth_tse_nf_phyip_terminator.v" -work altera_eth_tse_nf_phyip_terminator_194
+ vlog "$IP_DIR/../altera_eth_tse_nf_phyip_terminator_1940/sim/mentor/altera_eth_tse_nf_phyip_terminator.v" -work altera_eth_tse_nf_phyip_terminator_1940
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg
similarity index 83%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg
index 3fcd13f653..6bc962ea4a 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_nf_phyip_terminator_194
-hdl_library_clause_name = altera_eth_tse_nf_phyip_terminator_194
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_nf_phyip_terminator_1940
+hdl_library_clause_name = altera_eth_tse_nf_phyip_terminator_1940
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/compile_ip.tcl
deleted file mode 100644
index eb4c61cbbe..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/compile_ip.tcl
+++ /dev/null
@@ -1,114 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
-
-vmap altera_eth_tse_pcs_pma_nf_lvds_194 ./work/
-
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_eth_tse_pcs_pma_nf_lvds.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- #vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_lvds_reset_sequencer.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_lvds_reverse_loopback.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pma_lvds_rx_av.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pma_lvds_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pma_lvds_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ph_calculator.sv" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_lvds_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
new file mode 100644
index 0000000000..0c0ed04c18
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
@@ -0,0 +1,114 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+
+vmap altera_eth_tse_pcs_pma_nf_lvds_1940 ./work/
+
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_eth_tse_pcs_pma_nf_lvds.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ #vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_lvds_reset_sequencer.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_lvds_reverse_loopback.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_pma_lvds_rx_av.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_pma_lvds_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_pma_lvds_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ph_calculator.sv" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_1940/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_lvds_1940
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg
similarity index 70%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg
index b9bd0d2607..15e2f2fc7c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_lvds_194
-hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_lvds_194
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_lvds_1940
+hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_lvds_1940
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/compile_ip.tcl
deleted file mode 100644
index 12c5615059..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/compile_ip.tcl
+++ /dev/null
@@ -1,116 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
-
-
-vmap altera_eth_tse_pcs_pma_nf_phyip_194 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
-
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- #vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_reset_sequencer.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_reset_ctrl_lego.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_xcvr_resync.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_gxb_aligned_rxsync.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_phyip_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
new file mode 100644
index 0000000000..38a3ac9e41
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
@@ -0,0 +1,116 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+
+
+vmap altera_eth_tse_pcs_pma_nf_phyip_1940 ./work/
+
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_1940/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ #vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_reset_sequencer.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_reset_ctrl_lego.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_xcvr_resync.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_gxb_aligned_rxsync.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_phyip_1940
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg
similarity index 70%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg
index 4de2cfd1bb..d2816a9060 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_phyip_194
-hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_phyip_194
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_phyip_1940
+hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_phyip_1940
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
similarity index 90%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
index 2d1c465c1f..ae1a4365be 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
@@ -32,6 +32,6 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap altera_ip_col_if_194 ./work/
+vmap altera_ip_col_if_191 ./work/
- vlog "$IP_DIR/../altera_ip_col_if_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_ip_col_if_194_jvd2zcq.v" -work altera_ip_col_if_194
+ vlog "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_ip_col_if_191_k6i7ubq.v" -work altera_ip_col_if_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
similarity index 62%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
index 3cf9a13ba8..2a1b8d1562 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_ip_col_if_194
-hdl_library_clause_name = altera_ip_col_if_194
+hdl_lib_name = ip_arria10_e2sg_altera_ip_col_if_191
+hdl_library_clause_name = altera_ip_col_if_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
similarity index 65%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
index 508ba5f73c..924628ab6f 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
@@ -32,14 +32,14 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap altera_jtag_dc_streaming_194 ./work/
- vlog "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_194
- vlog "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_jtag_dc_streaming.v" -work altera_jtag_dc_streaming_194
- vlog "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_jtag_sld_node.v" -work altera_jtag_dc_streaming_194
- vlog "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_jtag_streaming.v" -work altera_jtag_dc_streaming_194
- vlog "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_clock_crosser.v" -work altera_jtag_dc_streaming_194
- vlog "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_std_synchronizer_nocut.v" -work altera_jtag_dc_streaming_194
- vlog "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_pipeline_base.v" -work altera_jtag_dc_streaming_194
- vlog "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_idle_remover.v" -work altera_jtag_dc_streaming_194
- vlog "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_idle_inserter.v" -work altera_jtag_dc_streaming_194
- vlog -sv "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_pipeline_stage.sv" -work altera_jtag_dc_streaming_194
+vmap altera_jtag_dc_streaming_191 ./work/
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_191
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_jtag_dc_streaming.v" -work altera_jtag_dc_streaming_191
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_jtag_sld_node.v" -work altera_jtag_dc_streaming_191
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_jtag_streaming.v" -work altera_jtag_dc_streaming_191
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_avalon_st_clock_crosser.v" -work altera_jtag_dc_streaming_191
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_std_synchronizer_nocut.v" -work altera_jtag_dc_streaming_191
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_base.v" -work altera_jtag_dc_streaming_191
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_remover.v" -work altera_jtag_dc_streaming_191
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_inserter.v" -work altera_jtag_dc_streaming_191
+ vlog -sv "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_stage.sv" -work altera_jtag_dc_streaming_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg
new file mode 100644
index 0000000000..50e59bccc7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_jtag_dc_streaming_191
+hdl_library_clause_name = altera_jtag_dc_streaming_191
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/hdllib.cfg
deleted file mode 100644
index 342af0f1db..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e2sg_altera_jtag_dc_streaming_194
-hdl_library_clause_name = altera_jtag_dc_streaming_194
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e2sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
similarity index 83%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
index 281941337a..83823e0425 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
-vmap altera_lvds_194 ./work/
- vcom "$IP_DIR/../altera_lvds_194/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_194_og2byry.vhd" -work altera_lvds_194
- vcom "$IP_DIR/../altera_lvds_194/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_194_zfbfxeq.vhd" -work altera_lvds_194
+vmap altera_lvds_1930 ./work/
+ vcom "$IP_DIR/../altera_lvds_1930/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_1930_7egaewa.vhd" -work altera_lvds_1930
+ vcom "$IP_DIR/../altera_lvds_1930/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_1930_w33qkcq.vhd" -work altera_lvds_1930
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg
similarity index 53%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg
index c57f79da67..04e021c285 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg
@@ -1,7 +1,7 @@
-hdl_lib_name = ip_arria10_e2sg_altera_lvds_194
-hdl_library_clause_name = altera_lvds_194
+hdl_lib_name = ip_arria10_e2sg_altera_lvds_1930
+hdl_library_clause_name = altera_lvds_1930
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_lvds_core20_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_lvds_core20_1930
hdl_lib_technology = ip_arria10_e2sg
synth_files =
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
similarity index 66%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
index 5eab2a57c4..1979f7fe9c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
@@ -28,11 +28,13 @@
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
-vmap altera_lvds_core20_194 ./work/
+vmap altera_lvds_core20_191 ./work/
- vlog -sv "$IP_DIR/../altera_lvds_core20_194/sim/altera_lvds_core20.sv" -work altera_lvds_core20_194
- vlog "$IP_DIR/../altera_lvds_core20_194/sim/altera_lvds_core20_pll.v" -work altera_lvds_core20_194
- vcom "$IP_DIR/../altera_lvds_core20_194/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_194_5a5vzei.vhd" -work altera_lvds_core20_194
- vlog -sv "$IP_DIR/../altera_lvds_core20_194/sim/altera_lvds_core20.sv" -work altera_lvds_core20_194
- vlog "$IP_DIR/../altera_lvds_core20_194/sim/altera_lvds_core20_pll.v" -work altera_lvds_core20_194
- vcom "$IP_DIR/../altera_lvds_core20_194/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_194_kmpu4hy.vhd" -work altera_lvds_core20_194
+ vlog -sv "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20.sv" -work altera_lvds_core20_191
+ vlog "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20_pll.v" -work altera_lvds_core20_191
+# vcom "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_276h55y.vhd" -work altera_lvds_core20_191
+ vcom "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_276h55y.sv" -work altera_lvds_core20_191
+ vlog -sv "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20.sv" -work altera_lvds_core20_191
+ vlog "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20_pll.v" -work altera_lvds_core20_191
+# vcom "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_ag343xq.vhd" -work altera_lvds_core20_191
+ vcom "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_ag343xq.sv" -work altera_lvds_core20_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg
similarity index 61%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg
index 27c3b19850..475ac60eb4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_lvds_core20_194
-hdl_library_clause_name = altera_lvds_core20_194
+hdl_lib_name = ip_arria10_e2sg_altera_lvds_core20_191
+hdl_library_clause_name = altera_lvds_core20_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
similarity index 86%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
index 3003c89fc6..e9fb6118fa 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
@@ -29,8 +29,9 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap altera_merlin_slave_translator_194 ./work/
+vmap altera_merlin_slave_translator_191 ./work/
- vlog -sv "$IP_DIR/../altera_merlin_slave_translator_194/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_194
+ vcom "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_slave_translator_191_x56fcki.sv" -work altera_merlin_slave_translator_191
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg
similarity index 71%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg
index b09e8c6e63..c3f96d2542 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_merlin_slave_translator_194
-hdl_library_clause_name = altera_merlin_slave_translator_194
+hdl_lib_name = ip_arria10_e2sg_altera_merlin_slave_translator_191
+hdl_library_clause_name = altera_merlin_slave_translator_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
similarity index 55%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
index bb1ffeed0e..2a7891c90c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
@@ -28,19 +28,18 @@
#vlib ./work/ ;# Assume library work already exist
#
-vmap altera_avalon_onchip_memory2_194 ./work/
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+vmap altera_mm_interconnect_191 ./work/
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+# vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+# vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+ vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_3yb4cia.vhd" -work altera_mm_interconnect_191
+ vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd" -work altera_mm_interconnect_191
+ vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd" -work altera_mm_interconnect_191
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
-
-
-
+#set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+# vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
similarity index 56%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
index 2cfcd7b671..4ce1df3346 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
@@ -1,7 +1,7 @@
-hdl_lib_name = ip_arria10_e2sg_altera_mm_interconnect_194
-hdl_library_clause_name = altera_mm_interconnect_194
+hdl_lib_name = ip_arria10_e2sg_altera_mm_interconnect_191
+hdl_library_clause_name = altera_mm_interconnect_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_194 ip_arria10_e2sg_altera_merlin_slave_translator_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_merlin_slave_translator_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/compile_ip.tcl
deleted file mode 100644
index 5e96123ae6..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/compile_ip.tcl
+++ /dev/null
@@ -1,45 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-vmap altera_mm_interconnect_194 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_ibrpcbq.vhd" -work altera_mm_interconnect_194
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_mtvmp4i.vhd" -work altera_mm_interconnect_194
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_mm_interconnect_194_7km4trq.vhd" -work altera_mm_interconnect_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
index d9215e2dd7..a2f283a8ae 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
@@ -1,8 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_altera_remote_update_1910
hdl_library_clause_name = altera_remote_update_1910
hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-#ip_arria10_e2sg_altera_remote_update_core_1910
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_remote_update_core_1910
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg
index b48ddb73fa..8e1035e075 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_remote_update_core_194
-hdl_library_clause_name = altera_remote_update_core_194
+hdl_lib_name = ip_arria10_e2sg_altera_remote_update_core_1910
+hdl_library_clause_name = altera_remote_update_core_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -9,4 +9,4 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
similarity index 85%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
index 5f1c942eaf..1f4efd6bea 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
@@ -29,9 +29,9 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap altera_reset_controller_194 ./work/
+vmap altera_reset_controller_191 ./work/
- vlog "$IP_DIR/../altera_reset_controller_194/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_194
- vlog "$IP_DIR/../altera_reset_controller_194/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_194
+ vlog "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_191
+ vlog "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg
new file mode 100644
index 0000000000..fb7cfdeab2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_reset_controller_191
+hdl_library_clause_name = altera_reset_controller_191
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/hdllib.cfg
deleted file mode 100644
index eca40b53b9..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e2sg_altera_reset_controller_194
-hdl_library_clause_name = altera_reset_controller_194
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e2sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
similarity index 75%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
index 5b680d82bd..51a960a06b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
@@ -32,24 +32,24 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
vmap altera_common_sv_packages ./work/
-vmap altera_xcvr_atx_pll_a10_194 ./work/
+vmap altera_xcvr_atx_pll_a10_191 ./work/
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_atx_pll_rcfg_opt_logic_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_atx_pll_rcfg_opt_logic_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
similarity index 59%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
index 795fc5093e..86eaf4a404 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_xcvr_atx_pll_a10_194
-hdl_library_clause_name = altera_xcvr_atx_pll_a10_194
+hdl_lib_name = ip_arria10_e2sg_altera_xcvr_atx_pll_a10_191
+hdl_library_clause_name = altera_xcvr_atx_pll_a10_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
new file mode 100644
index 0000000000..5fc727249b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
@@ -0,0 +1,108 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+vmap altera_xcvr_native_a10_191 ./work/
+vmap altera_common_sv_packages ./work/
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
+
+# common dependencies
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+
+# phy_10gbase_r_48
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_191_x2zy5gq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_x2zy5gq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+
+# phy_10gbase_r_24
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_191_xj4rzbi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_xj4rzbi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+
+# phy_10gbase_r_12
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_191_vvjuhsq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_vvjuhsq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+
+# phy_10gbase_r_4
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_191_nx522la.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_nx522la.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+
+# phy_10gbase_r_3
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_191_ofoefcy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ofoefcy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+
+# phy_10gbase_r
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191_hsgyevq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_hsgyevq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+
+# tse_sgmii_gx
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_xcvr_native_a10_191_fbxkdmq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_fbxkdmq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+
+# jesd204b rx
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_rx_altera_xcvr_native_a10_191_pebno5q.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_pebno5q.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+
+# jesd204b tx
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_tx_altera_xcvr_native_a10_191_wjipjey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_wjipjey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg
new file mode 100644
index 0000000000..534c0be3c2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_xcvr_native_a10_191
+hdl_library_clause_name = altera_xcvr_native_a10_191
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/compile_ip.tcl
deleted file mode 100644
index 1c9e1d44e8..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/compile_ip.tcl
+++ /dev/null
@@ -1,108 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_xcvr_native_a10_194 ./work/
-vmap altera_common_sv_packages ./work/
-
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
-
-# common dependencies
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
-
-# phy_10gbase_r_48
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_194_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
-
-# phy_10gbase_r_24
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_194_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
-
-# phy_10gbase_r_12
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_194_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
-
-# phy_10gbase_r_4
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_194_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
-
-# phy_10gbase_r_3
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_194_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
-
-# phy_10gbase_r
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_194_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
-
-# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_xcvr_native_a10_194_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
-
-# jesd204b rx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_jesd204b_rx_altera_xcvr_native_a10_194_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
-
-# jesd204b tx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_jesd204b_tx_altera_xcvr_native_a10_194_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/hdllib.cfg
deleted file mode 100644
index 7fe974b390..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e2sg_altera_xcvr_native_a10_194
-hdl_library_clause_name = altera_xcvr_native_a10_194
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e2sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/compile_ip.tcl
-
-
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
similarity index 75%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
index ec9d9441cf..042ffaf536 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
@@ -31,14 +31,14 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
-vmap altera_xcvr_reset_control_194 ./work/
+vmap altera_xcvr_reset_control_191 ./work/
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_194/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_194
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_194/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_194
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_194/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_194
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_194/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_194
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_194/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_194
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_194/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_194
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_194/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_194
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_194/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_194
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_191/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_191
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_191/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_191
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_191/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_191
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_191/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_191
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_191/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_191
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_191/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_191
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_191/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_191
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_191/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg
new file mode 100644
index 0000000000..491e0f6336
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_xcvr_reset_control_191
+hdl_library_clause_name = altera_xcvr_reset_control_191
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/hdllib.cfg
deleted file mode 100644
index 7998387912..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e2sg_altera_xcvr_reset_control_194
-hdl_library_clause_name = altera_xcvr_reset_control_194
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e2sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/compile_ip.tcl
-
-
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
similarity index 82%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
index 98920860f3..9b1d2e39cb 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
@@ -32,9 +32,9 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap channel_adapter_194 ./work/
+vmap channel_adapter_191 ./work/
- vlog -sv "$IP_DIR/../channel_adapter_194/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_194_kn2anua.sv" -work channel_adapter_194
- vlog -sv "$IP_DIR/../channel_adapter_194/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_194_wjhhrui.sv" -work channel_adapter_194
+ vlog -sv "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_191_cco4x3a.sv" -work channel_adapter_191
+ vlog -sv "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_191_uc27kqq.sv" -work channel_adapter_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg
similarity index 62%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg
index c1c910d5b9..88a5792a4c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_channel_adapter_194
-hdl_library_clause_name = channel_adapter_194
+hdl_lib_name = ip_arria10_e2sg_channel_adapter_191
+hdl_library_clause_name = channel_adapter_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/hdllib.cfg
deleted file mode 100644
index 391076569b..0000000000
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e2sg_altera_merlin_master_translator_194
-hdl_library_clause_name = altera_merlin_master_translator_194
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e2sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_194/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
similarity index 90%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
index ef4fe65555..31a8e0ed3c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
@@ -32,8 +32,8 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-vmap timing_adapter_194 ./work/
+vmap timing_adapter_191 ./work/
- vlog -sv "$IP_DIR/../timing_adapter_194/sim/ip_arria10_e2sg_ddr4_8g_1600_timing_adapter_194_ewif6gi.sv" -work timing_adapter_194
+ vlog -sv "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_timing_adapter_191_rrgemwi.sv" -work timing_adapter_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg
similarity index 63%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg
index 0362ff7264..c9632755d6 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_timing_adapter_194
-hdl_library_clause_name = timing_adapter_194
+hdl_lib_name = ip_arria10_e2sg_timing_adapter_191
+hdl_library_clause_name = timing_adapter_191
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
index 0520d8cf77..caf20a2414 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
@@ -30,7 +30,5 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
-vmap altmult_complex_194 ./work/
-# vlog "$IP_DIR/../altmult_complex_194/synth/ip_arria10_e2sg_complex_mult_altmult_complex_194_nkpx3mi.v" -work altmult_complex_194
- vlog "$IP_DIR/../altmult_complex_1910/synth/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.v" -work altmult_complex_194
- #vlog "$IP_DIR/ip_arria10_e2sg_complex_mult_bb.v"
+vmap altmult_complex_1910 ./work/
+ vlog "$IP_DIR/../altmult_complex_1910/synth/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.v" -work altmult_complex_1910
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
index 03fcb206c2..2f0aca1710 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e2sg_complex_mult
-hdl_library_clause_name = ip_arria10_e2sg_complex_mult_altmult_complex_194
+hdl_library_clause_name = ip_arria10_e2sg_complex_mult_altmult_complex_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
index b5362e8f2e..47f7f739d8 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
@@ -37,24 +37,24 @@ if {$IPMODEL=="PHY"} {
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_in_1/sim"
#vlib ./work/ ;# Assume library work already exists
- vmap ip_arria10_ddio_in_1_altera_gpio_core_194 ./work/
- vmap ip_arria10_ddio_in_1_altera_gpio_194 ./work/
+ vmap ip_arria10_ddio_in_1_altera_gpio_core_191 ./work/
+ vmap ip_arria10_ddio_in_1_altera_gpio_1930 ./work/
- vlog -sv "$IP_DIR/../altera_gpio_core_194/sim/mentor/altera_gpio.sv" -work ip_arria10_ddio_in_1_altera_gpio_core_194
+ vlog -sv "$IP_DIR/../altera_gpio_core_191/sim/mentor/altera_gpio.sv" -work ip_arria10_ddio_in_1_altera_gpio_core_191
- vcom "$IP_DIR/../altera_gpio_194/sim/ip_arria10_ddio_in_1_altera_gpio_194_umwov7y.vhd" -work ip_arria10_ddio_in_1_altera_gpio_194
+ vcom "$IP_DIR/../altera_gpio_1930/sim/ip_arria10_ddio_in_1_altera_gpio_1930_aac2boi.vhd" -work ip_arria10_ddio_in_1_altera_gpio_1930
vcom "$IP_DIR/ip_arria10_ddio_in_1.vhd"
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_out_1/sim"
#vlib ./work/ ;# Assume library work already exists
- vmap ip_arria10_ddio_out_1_altera_gpio_core_194 ./work/
- vmap ip_arria10_ddio_out_1_altera_gpio_194 ./work/
+ vmap ip_arria10_ddio_out_1_altera_gpio_core_191 ./work/
+ vmap ip_arria10_ddio_out_1_altera_gpio_1930 ./work/
- vlog -sv "$IP_DIR/../altera_gpio_core_194/sim/mentor/altera_gpio.sv" -work ip_arria10_ddio_out_1_altera_gpio_core_194
+ vlog -sv "$IP_DIR/../altera_gpio_core_191/sim/mentor/altera_gpio.sv" -work ip_arria10_ddio_out_1_altera_gpio_core_191
- vcom "$IP_DIR/../altera_gpio_194/sim/ip_arria10_ddio_out_1_altera_gpio_194_c3jcq7i.vhd" -work ip_arria10_ddio_out_1_altera_gpio_194
+ vcom "$IP_DIR/../altera_gpio_1930/sim/ip_arria10_ddio_out_1_altera_gpio_1930_qdroiey.vhd" -work ip_arria10_ddio_out_1_altera_gpio_1930
vcom "$IP_DIR/ip_arria10_ddio_out_1.vhd"
} else {
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
index 3dbe4f379e..4bd7eed1ff 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_ddr4_8g_1600
-hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_1600_altera_emif_194
+hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_194 ip_arria10_e2sg_altera_emif_cal_slave_nf_194 ip_arria10_e2sg_altera_avalon_onchip_memory2_194 ip_arria10_e2sg_altera_mm_interconnect_194 ip_arria10_e2sg_altera_reset_controller_194 ip_arria10_e2sg_altera_emif_arch_nf_194 ip_arria10_e2sg_altera_emif_194 ip_arria10_e2sg_altera_avalon_mm_bridge_194 ip_arria10_e2sg_altera_merlin_slave_translator_194 ip_arria10_e2sg_altera_avalon_sc_fifo_194 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_194 ip_arria10_e2sg_altera_ip_col_if_194 ip_arria10_e2sg_altera_jtag_dc_streaming_194 ip_arria10_e2sg_alt_mem_if_jtag_master_194 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_194 ip_arria10_e2sg_altera_avalon_packets_to_master_194 ip_arria10_e2sg_channel_adapter_194 ip_arria10_e2sg_timing_adapter_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_emif_cal_slave_nf_191 ip_arria10_e2sg_altera_avalon_onchip_memory2_1920 ip_arria10_e2sg_altera_mm_interconnect_191 ip_arria10_e2sg_altera_reset_controller_191 ip_arria10_e2sg_altera_emif_arch_nf_191 ip_arria10_e2sg_altera_emif_1910 ip_arria10_e2sg_altera_avalon_mm_bridge_191 ip_arria10_e2sg_altera_merlin_slave_translator_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 ip_arria10_e2sg_altera_ip_col_if_191 ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_alt_mem_if_jtag_master_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_timing_adapter_191
hdl_lib_technology = ip_arria10_e2sg
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
index 44d2a4da4f..ed87d3019f 100644
--- a/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_mac_10g
-hdl_library_clause_name = ip_arria10_e2sg_mac_10g_alt_em10g32_194
+hdl_library_clause_name = ip_arria10_e2sg_mac_10g_alt_em10g32_1930
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_alt_em10g32_194
+hdl_lib_uses_sim = ip_arria10_e2sg_alt_em10g32_1930
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
index 79f44d7c2d..ea16fe38cf 100644
--- a/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
@@ -32,8 +32,8 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mult_add4/sim"
vmap ip_arria10_e2sg_mult_add4 ./work/
-vmap altera_mult_add_194 ./work/
+vmap altera_mult_add_1910 ./work/
- vcom "$IP_DIR/../altera_mult_add_194/sim/ip_arria10_e2sg_mult_add4_altera_mult_add_194_o5e3uui.vhd" -work altera_mult_add_194
+ vcom "$IP_DIR/../altera_mult_add_1910/sim/ip_arria10_e2sg_mult_add4_altera_mult_add_1910_sad25hq.vhd" -work altera_mult_add_1910
vcom "$IP_DIR/ip_arria10_e2sg_mult_add4.vhd" -work ip_arria10_e2sg_mult_add4
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
index 0117da3245..b6e2620a30 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_194
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
index c62b571620..b211cea285 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_12
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_194
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
index 3507c1a6bc..d3d9782e02 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_24
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_194
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
index e0f43ddd0f..4f381244ec 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_3
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_194
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
index 25b4449878..2f337692b2 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_4
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_194
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
index a4887f778e..0f7ce6dd7d 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_48
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_194
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
index a93714fcde..f7bf08e5ec 100644
--- a/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
@@ -31,7 +31,7 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_temp_sense/sim"
-vmap altera_temp_sense_194 ./work/
+vmap altera_temp_sense_1910 ./work/
- vlog "$IP_DIR/../altera_temp_sense_194/sim/altera_temp_sense.v" -work altera_temp_sense_194
+ vlog "$IP_DIR/../altera_temp_sense_1910/sim/altera_temp_sense.v" -work altera_temp_sense_1910
vcom "$IP_DIR/ip_arria10_e2sg_temp_sense.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
index 4d5f22f8e1..346ed99c79 100644
--- a/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e2sg_temp_sense
-hdl_library_clause_name = ip_arria10_e2sg_temp_sense_altera_temp_sense_194
+hdl_library_clause_name = ip_arria10_e2sg_temp_sense_altera_temp_sense_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
index b4ca19e5e6..3883ef2edc 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_transceiver_pll_10g
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_atx_pll_a10_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_atx_pll_a10_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
index ed25b279cd..6d04b9ceda 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_1
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_194
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
index 0dbe8b8ed0..de8a07ce6b 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_12
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_194
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
index a65a4c8f8a..1769ca01f5 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_24
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_194
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
index 38f5aed6be..a2612ca5c3 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_3
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_3_altera_xcvr_reset_control_194
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_3_altera_xcvr_reset_control_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
index 3d7ad98e6f..2854213ec4 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_4
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_194
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
index 87541f2107..4a07513526 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_48
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_194
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_191
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
index 574c7ff82e..1b8ecbf3fa 100644
--- a/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
@@ -32,16 +32,16 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_voltage_sense/sim"
vmap ip_arria10_e2sg_voltage_sense ./work/
-vmap altera_voltage_sensor_194 ./work/
-vmap altera_voltage_sensor_control_194 ./work/
-vmap altera_voltage_sensor_sample_store_194 ./work/
+vmap altera_voltage_sensor_1910 ./work/
+vmap altera_voltage_sensor_control_1910 ./work/
+vmap altera_voltage_sensor_sample_store_1910 ./work/
- vlog -sv "$IP_DIR/../altera_voltage_sensor_control_194/sim/mentor/altera_voltage_sensor_control.sv" -work altera_voltage_sensor_control_194
- vlog -sv "$IP_DIR/../altera_voltage_sensor_control_194/sim/mentor/voltage_sensor_avalon_controlr.sv" -work altera_voltage_sensor_control_194
- vlog -sv "$IP_DIR/../altera_voltage_sensor_control_194/sim/mentor/voltage_sensor_wrapper.sv" -work altera_voltage_sensor_control_194
- vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_194/sim/mentor/altera_voltage_sensor_sample_store.sv" -work altera_voltage_sensor_sample_store_194
- vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_194/sim/mentor/altera_voltage_sensor_sample_store_ram.sv" -work altera_voltage_sensor_sample_store_194
- vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_194/sim/mentor/altera_voltage_sensor_sample_store_register.sv" -work altera_voltage_sensor_sample_store_194
- vcom "$IP_DIR/../altera_voltage_sensor_194/sim/ip_arria10_e2sg_voltage_sense_altera_voltage_sensor_194_bqre2vy.vhd" -work altera_voltage_sensor_194
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_1910/sim/mentor/altera_voltage_sensor_control.sv" -work altera_voltage_sensor_control_1910
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_1910/sim/mentor/voltage_sensor_avalon_controlr.sv" -work altera_voltage_sensor_control_1910
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_1910/sim/mentor/voltage_sensor_wrapper.sv" -work altera_voltage_sensor_control_1910
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_1910/sim/mentor/altera_voltage_sensor_sample_store.sv" -work altera_voltage_sensor_sample_store_1910
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_1910/sim/mentor/altera_voltage_sensor_sample_store_ram.sv" -work altera_voltage_sensor_sample_store_1910
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_1910/sim/mentor/altera_voltage_sensor_sample_store_register.sv" -work altera_voltage_sensor_sample_store_1910
+ vcom "$IP_DIR/../altera_voltage_sensor_1910/sim/ip_arria10_e2sg_voltage_sense_altera_voltage_sensor_1910_a35wwnq.vhd" -work altera_voltage_sensor_1910
vcom "$IP_DIR/ip_arria10_e2sg_voltage_sense.vhd" -work ip_arria10_e2sg_voltage_sense
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index 7d1e767dfe..3defdbf578 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_jesd204b ip_arria10_e1sg_jesd204b_180
- ip_arria10_e2sg_jesd204b ip_arria10_e2sg_jesd204b_194
+ ip_arria10_e2sg_jesd204b ip_arria10_e2sg_jesd204b_191
synth_files =
tech_jesd204b_component_pkg.vhd
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index 6d2d975753..a8b2744aa3 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_mac_10g ip_arria10_mac_10g_alt_em10g32_150
ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_180
- ip_arria10_e2sg_mac_10g ip_arria10_e2sg_mac_10g_alt_em10g32_194
+ ip_arria10_e2sg_mac_10g ip_arria10_e2sg_mac_10g_alt_em10g32_1930
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
index c31fcb0a37..f7a598b09f 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e2sg_mac_10g_alt_em10g32_194;
+LIBRARY ip_arria10_e2sg_mac_10g_alt_em10g32_1930;
LIBRARY IEEE, technology_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 5fbea82b38..d845941a08 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -26,7 +26,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_mult_add2 ip_arria10_e1sg_mult_add2_lib
ip_arria10_e2sg_mult_add4 ip_arria10_e2sg_mult_add4_lib
ip_arria10_e2sg_mult_add2 ip_arria10_e2sg_mult_add2_lib
- ip_arria10_e2sg_complex_mult ip_arria10_e2sg_complex_mult_altmult_complex_194
+ ip_arria10_e2sg_complex_mult ip_arria10_e2sg_complex_mult_altmult_complex_1910
synth_files =
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 680f89fb2e..a7974a7977 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -32,7 +32,7 @@ LIBRARY ip_stratixiv_mult_lib;
--LIBRARY ip_arria10_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_altmult_complex_150;
LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_180;
-LIBRARY ip_arria10_e2sg_complex_mult_altmult_complex_194;
+LIBRARY ip_arria10_e2sg_complex_mult_altmult_complex_1910;
LIBRARY ip_arria10_complex_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_rtl_canonical_lib;
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index b91a8beeaf..613bc92894 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -23,10 +23,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_180
ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_180
ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180
- ip_arria10_e2sg_pll_clk200 ip_arria10_e2sg_pll_clk200_altera_iopll_194
- ip_arria10_e2sg_pll_clk25 ip_arria10_e2sg_pll_clk25_altera_iopll_194
- ip_arria10_e2sg_pll_clk125 ip_arria10_e2sg_pll_clk125_altera_iopll_194
- ip_arria10_e2sg_pll_xgmii_mac_clocks ip_arria10_e2sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_194
+ ip_arria10_e2sg_pll_clk200 ip_arria10_e2sg_pll_clk200_altera_iopll_1930
+ ip_arria10_e2sg_pll_clk25 ip_arria10_e2sg_pll_clk25_altera_iopll_1930
+ ip_arria10_e2sg_pll_clk125 ip_arria10_e2sg_pll_clk125_altera_iopll_1930
+ ip_arria10_e2sg_pll_xgmii_mac_clocks ip_arria10_e2sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_191
synth_files =
tech_pll_component_pkg.vhd
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index fab5e6259a..afe5ff658d 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_180;
-LIBRARY ip_arria10_e2sg_pll_clk125_altera_iopll_194;
+LIBRARY ip_arria10_e2sg_pll_clk125_altera_iopll_1930;
ENTITY tech_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index 1a38b8d778..ccff2fa603 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -30,7 +30,7 @@ LIBRARY ip_stratixiv_pll_lib;
LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_180;
-LIBRARY ip_arria10_e2sg_pll_clk200_altera_iopll_194;
+LIBRARY ip_arria10_e2sg_pll_clk200_altera_iopll_1930;
ENTITY tech_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index 68d5f876e3..1e2251793d 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -30,7 +30,7 @@ LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
LIBRARY ip_stratixiv_pll_clk25_lib;
LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_180;
-LIBRARY ip_arria10_e2sg_pll_clk25_altera_iopll_194;
+LIBRARY ip_arria10_e2sg_pll_clk25_altera_iopll_1930;
ENTITY tech_pll_clk25 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index 674cb5379b..9cee65f0b2 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -44,7 +44,7 @@ USE common_lib.common_pkg.ALL;
LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180;
-LIBRARY ip_arria10_e2sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_194;
+LIBRARY ip_arria10_e2sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_191;
ENTITY tech_pll_xgmii_mac_clocks IS
GENERIC (
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 16e4ca1d98..5b71fe5191 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -17,8 +17,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180
ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180
- ip_arria10_e2sg_tse_sgmii_lvds ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_180
- ip_arria10_e2sg_tse_sgmii_gx ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_180
+ ip_arria10_e2sg_tse_sgmii_lvds ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_1940
+ ip_arria10_e2sg_tse_sgmii_gx ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_1940
synth_files =
tech_tse_component_pkg.vhd
diff --git a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
index 81551c38d3..d3e5752dbc 100644
--- a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_194;
-LIBRARY ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_194;
+LIBRARY ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_1940;
+LIBRARY ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_1940;
ENTITY tech_tse_arria10_e2sg IS
GENERIC (
--
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