diff --git a/libraries/technology/eth_10g/hdllib.cfg b/libraries/technology/eth_10g/hdllib.cfg
index f481d799cb336c57b006e0e3d86f6cd649109113..27b2b3357bd3b1b93cfcfe4cd8b4078cf63074c9 100644
--- a/libraries/technology/eth_10g/hdllib.cfg
+++ b/libraries/technology/eth_10g/hdllib.cfg
@@ -1,10 +1,16 @@
hdl_lib_name = tech_eth_10g
hdl_library_clause_name = tech_eth_10g_lib
-hdl_lib_uses_synth = technology tech_pll tech_mac_10g tech_10gbase_r tech_xaui common dp
+hdl_lib_uses_synth = technology tech_pll tech_mac_10g common dp ip_stratixiv_eth_10g ip_arria10_eth_10g ip_arria10_e3sge3_eth_10g ip_arria10_e1sg_eth_10g
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_eth_10g ip_stratixiv_eth_10g_lib
+ ip_arria10_eth_10g ip_arria10_eth_10g_lib
+ ip_arria10_e3sge3_eth_10g ip_arria10_e3sge3_eth_10g_lib
+ ip_arria10_e1sg_eth_10g ip_arria10_e1sg_eth_10g_lib
synth_files =
+ tech_eth_10g_component_pkg.vhd
tech_eth_10g_stratixiv.vhd
tech_eth_10g_arria10.vhd
tech_eth_10g_arria10_e3sge3.vhd
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
index 96ccbd8db5c066bf176f94f4afdb511486b59d9b..ad241ac9c543c89b78b79bab675038a0bfb5dd80 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
@@ -83,7 +83,7 @@
-- [3:2] = xgmii_link_status_arr(I)
--
-LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_10gbase_r_lib, tech_mac_10g_lib;
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_mac_10g_lib, ip_arria10_eth_10g_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE common_lib.common_pkg.ALL;
@@ -91,6 +91,7 @@ USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
+USE work.tech_eth_10g_component_pkg.ALL;
ENTITY tech_eth_10g_arria10 IS
GENERIC (
@@ -134,181 +135,45 @@ END tech_eth_10g_arria10;
ARCHITECTURE str OF tech_eth_10g_arria10 IS
-
- -- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
- CONSTANT c_check_link_status : BOOLEAN := g_direction/="TX_ONLY";
- CONSTANT c_check_xgmii_tx_ready : BOOLEAN := g_direction/="RX_ONLY";
-
- SIGNAL i_tx_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- MAG_10G control status registers
- SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- XON control
- SIGNAL mac_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- XGMII
- SIGNAL xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels-1 DOWNTO 0); -- 2 bit, from MAC_10g
- SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, from PHY 10gbase_r
- SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
- SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
- SIGNAL xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
-
- -- Link status monitor
- CONSTANT c_mem_reg_eth10g_adr_w : NATURAL := 1;
- CONSTANT c_mem_reg_eth10g_dat_w : NATURAL := 32;
- CONSTANT c_mem_reg_eth10g_nof_data : NATURAL := 1;
- CONSTANT c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
-
- SIGNAL reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-
- SIGNAL mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels-1 DOWNTO 0);
BEGIN
- tx_snk_out_arr <= i_tx_snk_out_arr;
-
- gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
-
- i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
-
- p_xon_flow_control : PROCESS(clk_156)
- VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "00";
- VARIABLE v_xgmii_tx_ready : STD_LOGIC := '1';
- BEGIN
- IF rising_edge(clk_156) THEN
- i_tx_snk_out_arr(I).xon <= '0';
-
- -- First gather all conditions that are enabled to affect xon. The default value is such that it enables xon when the condition is not checked.
- IF c_check_link_status =TRUE THEN v_xgmii_link_status := xgmii_link_status_arr(I); END IF; -- check both remote fault [1] and local fault [0]
- IF c_check_xgmii_tx_ready=TRUE THEN v_xgmii_tx_ready := xgmii_tx_ready_arr(I); END IF;
-
- -- Now apply the conditions to xon
- IF v_xgmii_tx_ready='1' AND v_xgmii_link_status="00" THEN
- i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
- END IF;
- END IF;
- END PROCESS;
-
- u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
- GENERIC MAP (
- g_technology => c_tech_arria10,
- g_pre_header_padding => g_pre_header_padding
- )
- PORT MAP (
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- csr_mosi => mac_mosi_arr(I),
- csr_miso => mac_miso_arr(I),
-
- -- ST
- tx_clk_312 => clk_312,
- tx_clk_156 => clk_156,
- tx_rst => rst_156,
- tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
- tx_snk_out => mac_snk_out_arr(I),
-
- rx_clk_312 => clk_312,
- rx_clk_156 => clk_156,
- rx_rst => rst_156,
- rx_src_out => rx_src_out_arr(I), -- 64 bit data
- rx_src_in => rx_src_in_arr(I),
-
- -- XGMII
- xgmii_link_status => xgmii_link_status_arr(I),
- xgmii_tx_data => xgmii_tx_dc_arr(I),
- xgmii_rx_data => xgmii_internal_dc_arr(I)
- );
- END GENERATE;
-
- xgmii_internal_dc_arr <= xgmii_tx_dc_arr WHEN g_direction="TX_ONLY" ELSE xgmii_rx_dc_arr;
-
- u_tech_10gbase_r: ENTITY tech_10gbase_r_lib.tech_10gbase_r
- GENERIC MAP (
- g_technology => c_tech_arria10,
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_nof_channels => g_nof_channels
+ u_ip_arria10_eth_10g : ip_arria10_eth_10g
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels,
+ g_direction => g_direction,
+ g_pre_header_padding => g_pre_header_padding
)
- PORT MAP (
+ PORT MAP(
-- Transceiver PLL reference clock
- tr_ref_clk_644 => tr_ref_clk_644,
-
- -- XGMII clocks
- clk_156 => clk_156,
- rst_156 => rst_156,
+ tr_ref_clk_644 => tr_ref_clk_644,
- -- XGMII interface
- xgmii_tx_ready_arr => xgmii_tx_ready_arr,
- xgmii_rx_ready_arr => OPEN,
- xgmii_tx_dc_arr => xgmii_tx_dc_arr,
- xgmii_rx_dc_arr => xgmii_rx_dc_arr,
+ -- Data clocks
+ clk_312 => clk_312,
+ clk_156 => clk_156,
+ rst_156 => rst_156,
- -- PHY serial IO
- tx_serial_arr => serial_tx_arr,
- rx_serial_arr => serial_rx_arr
- );
-
-
- gen_reg_eth10g : FOR I IN 0 TO g_nof_channels-1 GENERATE
- mm_reg_eth10g_arr(I) <= RESIZE_UVEC(xgmii_link_status_arr(I) & xgmii_tx_ready_arr(I) & i_tx_snk_out_arr(I).xon, c_mem_reg_eth10g_dat_w);
-
- u_reg_map : ENTITY common_lib.common_reg_r_w_dc
- GENERIC MAP (
- g_cross_clock_domain => TRUE,
- g_in_new_latency => 0,
- g_readback => FALSE,
- g_reg => c_mem_reg_eth10g,
- g_init_reg => (OTHERS => '0')
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => rst_156,
- st_clk => clk_156,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_eth10g_mosi_arr(I),
- sla_out => reg_eth10g_miso_arr(I),
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => '1',
- in_reg => mm_reg_eth10g_arr(I),
- out_reg => OPEN
- );
- END GENERATE;
-
-
- -----------------------------------------------------------------------------
- -- MM bus mux
- -----------------------------------------------------------------------------
- u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => g_nof_channels,
- g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
- )
- PORT MAP (
- mosi => mac_mosi,
- miso => mac_miso,
- mosi_arr => mac_mosi_arr,
- miso_arr => mac_miso_arr
- );
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- u_common_mem_mux_eth10g : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => g_nof_channels,
- g_mult_addr_w => c_mem_reg_eth10g_adr_w
- )
- PORT MAP (
- mosi => reg_eth10g_mosi,
- miso => reg_eth10g_miso,
- mosi_arr => reg_eth10g_mosi_arr,
- miso_arr => reg_eth10g_miso_arr
- );
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
+
+ reg_eth10g_mosi => reg_eth10g_mosi,
+ reg_eth10g_miso => reg_eth10g_miso,
+
+ -- ST
+ tx_snk_in_arr => tx_snk_in_arr,
+ tx_snk_out_arr => tx_snk_out_arr,
+
+ rx_src_out_arr => rx_src_out_arr,
+ rx_src_in_arr => rx_src_in_arr,
+
+ -- Serial
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
+ );
END str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
index 992f4025968a6a107ff1ffda6143fd3895a2772d..d69f01970ec5fa76ae6e40caa81728f243813fa5 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
@@ -83,7 +83,7 @@
-- [3:2] = xgmii_link_status_arr(I)
--
-LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_10gbase_r_lib, tech_mac_10g_lib;
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_mac_10g_lib, ip_arria10_e1sg_eth_10g_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE common_lib.common_pkg.ALL;
@@ -91,6 +91,7 @@ USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
+USE work.tech_eth_10g_component_pkg.ALL;
ENTITY tech_eth_10g_arria10_e1sg IS
GENERIC (
@@ -137,187 +138,48 @@ END tech_eth_10g_arria10_e1sg;
ARCHITECTURE str OF tech_eth_10g_arria10_e1sg IS
-
- -- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
- CONSTANT c_check_link_status : BOOLEAN := TRUE; --g_direction/="TX_ONLY";
- CONSTANT c_check_xgmii_tx_ready : BOOLEAN := TRUE; --g_direction/="RX_ONLY";
-
- SIGNAL i_tx_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- MAG_10G control status registers
- SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- XON control
- SIGNAL mac_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- XGMII
- SIGNAL xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels-1 DOWNTO 0); -- 2 bit, from MAC_10g
- SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, from PHY 10gbase_r
- SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
- SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
- SIGNAL xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
-
- -- Link status monitor
- CONSTANT c_mem_reg_eth10g_adr_w : NATURAL := 1;
- CONSTANT c_mem_reg_eth10g_dat_w : NATURAL := 32;
- CONSTANT c_mem_reg_eth10g_nof_data : NATURAL := 1;
- CONSTANT c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
-
- SIGNAL reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-
- SIGNAL mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels-1 DOWNTO 0);
BEGIN
- tx_snk_out_arr <= i_tx_snk_out_arr;
-
- gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
-
- i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
-
- p_xon_flow_control : PROCESS(clk_156)
- VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "00";
- VARIABLE v_xgmii_tx_ready : STD_LOGIC := '1';
- BEGIN
- IF rising_edge(clk_156) THEN
- i_tx_snk_out_arr(I).xon <= '0';
-
- -- First gather all conditions that are enabled to affect xon. The default value is such that it enables xon when the condition is not checked.
- IF c_check_link_status =TRUE THEN v_xgmii_link_status := xgmii_link_status_arr(I); END IF; -- check both remote fault [1] and local fault [0]
- IF c_check_xgmii_tx_ready=TRUE THEN v_xgmii_tx_ready := xgmii_tx_ready_arr(I); END IF;
-
- -- Now apply the conditions to xon
- IF v_xgmii_tx_ready='1' AND v_xgmii_link_status="00" THEN
- i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
- END IF;
- END IF;
- END PROCESS;
-
- u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
- GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
- g_pre_header_padding => g_pre_header_padding
- )
- PORT MAP (
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- csr_mosi => mac_mosi_arr(I),
- csr_miso => mac_miso_arr(I),
-
- -- ST
- tx_clk_312 => clk_312,
- tx_clk_156 => clk_156,
- tx_rst => rst_156,
- tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
- tx_snk_out => mac_snk_out_arr(I),
-
- rx_clk_312 => clk_312,
- rx_clk_156 => clk_156,
- rx_rst => rst_156,
- rx_src_out => rx_src_out_arr(I), -- 64 bit data
- rx_src_in => rx_src_in_arr(I),
-
- -- XGMII
- xgmii_link_status => xgmii_link_status_arr(I),
- xgmii_tx_data => xgmii_tx_dc_arr(I),
- xgmii_rx_data => xgmii_internal_dc_arr(I)
- );
- END GENERATE;
-
- xgmii_internal_dc_arr <= xgmii_tx_dc_arr WHEN g_direction="TX_ONLY" ELSE xgmii_rx_dc_arr;
-
- u_tech_10gbase_r: ENTITY tech_10gbase_r_lib.tech_10gbase_r
- GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_nof_channels => g_nof_channels
+ u_ip_arria10_e1sg_eth_10g : ip_arria10_e1sg_eth_10g
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels,
+ g_direction => g_direction,
+ g_pre_header_padding => g_pre_header_padding
)
- PORT MAP (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ PORT MAP(
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => tr_ref_clk_644,
+
+ -- Data clocks
+ clk_312 => clk_312,
+ clk_156 => clk_156,
+ rst_156 => rst_156,
- reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi,
- reg_ip_arria10_e1sg_phy_10gbase_r_24_miso => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso,
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => tr_ref_clk_644,
-
- -- XGMII clocks
- clk_156 => clk_156,
- rst_156 => rst_156,
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
- -- XGMII interface
- xgmii_tx_ready_arr => xgmii_tx_ready_arr,
- xgmii_rx_ready_arr => OPEN,
- xgmii_tx_dc_arr => xgmii_tx_dc_arr,
- xgmii_rx_dc_arr => xgmii_rx_dc_arr,
+ reg_eth10g_mosi => reg_eth10g_mosi,
+ reg_eth10g_miso => reg_eth10g_miso,
+
+ reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi,
+ reg_ip_arria10_e1sg_phy_10gbase_r_24_miso => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso,
- -- PHY serial IO
- tx_serial_arr => serial_tx_arr,
- rx_serial_arr => serial_rx_arr
- );
-
-
- gen_reg_eth10g : FOR I IN 0 TO g_nof_channels-1 GENERATE
- mm_reg_eth10g_arr(I) <= RESIZE_UVEC(xgmii_link_status_arr(I) & xgmii_tx_ready_arr(I) & i_tx_snk_out_arr(I).xon, c_mem_reg_eth10g_dat_w);
-
- u_reg_map : ENTITY common_lib.common_reg_r_w_dc
- GENERIC MAP (
- g_cross_clock_domain => TRUE,
- g_in_new_latency => 0,
- g_readback => FALSE,
- g_reg => c_mem_reg_eth10g,
- g_init_reg => (OTHERS => '0')
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => rst_156,
- st_clk => clk_156,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_eth10g_mosi_arr(I),
- sla_out => reg_eth10g_miso_arr(I),
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => '1',
- in_reg => mm_reg_eth10g_arr(I),
- out_reg => OPEN
- );
- END GENERATE;
-
-
- -----------------------------------------------------------------------------
- -- MM bus mux
- -----------------------------------------------------------------------------
- u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => g_nof_channels,
- g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
- )
- PORT MAP (
- mosi => mac_mosi,
- miso => mac_miso,
- mosi_arr => mac_mosi_arr,
- miso_arr => mac_miso_arr
- );
+ -- ST
+ tx_snk_in_arr => tx_snk_in_arr,
+ tx_snk_out_arr => tx_snk_out_arr,
- u_common_mem_mux_eth10g : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => g_nof_channels,
- g_mult_addr_w => c_mem_reg_eth10g_adr_w
- )
- PORT MAP (
- mosi => reg_eth10g_mosi,
- miso => reg_eth10g_miso,
- mosi_arr => reg_eth10g_mosi_arr,
- miso_arr => reg_eth10g_miso_arr
- );
+ rx_src_out_arr => rx_src_out_arr,
+ rx_src_in_arr => rx_src_in_arr,
+
+ -- Serial
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
+ );
END str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
index 6c32d7e75d1af2ef1df31257bbb702e21de596be..81fa70a6d098ffa5ac9b7d8c26ca9a6d6e4147e7 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
@@ -83,7 +83,7 @@
-- [3:2] = xgmii_link_status_arr(I)
--
-LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_10gbase_r_lib, tech_mac_10g_lib;
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_mac_10g_lib, ip_arria10_e3sge3_eth_10g_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE common_lib.common_pkg.ALL;
@@ -91,6 +91,7 @@ USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
+USE work.tech_eth_10g_component_pkg.ALL;
ENTITY tech_eth_10g_arria10_e3sge3 IS
GENERIC (
@@ -137,187 +138,48 @@ END tech_eth_10g_arria10_e3sge3;
ARCHITECTURE str OF tech_eth_10g_arria10_e3sge3 IS
-
- -- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
- CONSTANT c_check_link_status : BOOLEAN := g_direction/="TX_ONLY";
- CONSTANT c_check_xgmii_tx_ready : BOOLEAN := g_direction/="RX_ONLY";
-
- SIGNAL i_tx_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- MAG_10G control status registers
- SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- XON control
- SIGNAL mac_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- XGMII
- SIGNAL xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels-1 DOWNTO 0); -- 2 bit, from MAC_10g
- SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, from PHY 10gbase_r
- SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
- SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
- SIGNAL xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
-
- -- Link status monitor
- CONSTANT c_mem_reg_eth10g_adr_w : NATURAL := 1;
- CONSTANT c_mem_reg_eth10g_dat_w : NATURAL := 32;
- CONSTANT c_mem_reg_eth10g_nof_data : NATURAL := 1;
- CONSTANT c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
-
- SIGNAL reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-
- SIGNAL mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels-1 DOWNTO 0);
BEGIN
- tx_snk_out_arr <= i_tx_snk_out_arr;
-
- gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
-
- i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
-
- p_xon_flow_control : PROCESS(clk_156)
- VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "00";
- VARIABLE v_xgmii_tx_ready : STD_LOGIC := '1';
- BEGIN
- IF rising_edge(clk_156) THEN
- i_tx_snk_out_arr(I).xon <= '0';
-
- -- First gather all conditions that are enabled to affect xon. The default value is such that it enables xon when the condition is not checked.
- IF c_check_link_status =TRUE THEN v_xgmii_link_status := xgmii_link_status_arr(I); END IF; -- check both remote fault [1] and local fault [0]
- IF c_check_xgmii_tx_ready=TRUE THEN v_xgmii_tx_ready := xgmii_tx_ready_arr(I); END IF;
-
- -- Now apply the conditions to xon
- IF v_xgmii_tx_ready='1' AND v_xgmii_link_status="00" THEN
- i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
- END IF;
- END IF;
- END PROCESS;
-
- u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
- GENERIC MAP (
- g_technology => c_tech_arria10_e3sge3,
- g_pre_header_padding => g_pre_header_padding
- )
- PORT MAP (
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- csr_mosi => mac_mosi_arr(I),
- csr_miso => mac_miso_arr(I),
-
- -- ST
- tx_clk_312 => clk_312,
- tx_clk_156 => clk_156,
- tx_rst => rst_156,
- tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
- tx_snk_out => mac_snk_out_arr(I),
-
- rx_clk_312 => clk_312,
- rx_clk_156 => clk_156,
- rx_rst => rst_156,
- rx_src_out => rx_src_out_arr(I), -- 64 bit data
- rx_src_in => rx_src_in_arr(I),
-
- -- XGMII
- xgmii_link_status => xgmii_link_status_arr(I),
- xgmii_tx_data => xgmii_tx_dc_arr(I),
- xgmii_rx_data => xgmii_internal_dc_arr(I)
- );
- END GENERATE;
-
- xgmii_internal_dc_arr <= xgmii_tx_dc_arr WHEN g_direction="TX_ONLY" ELSE xgmii_rx_dc_arr;
-
- u_tech_10gbase_r: ENTITY tech_10gbase_r_lib.tech_10gbase_r
- GENERIC MAP (
- g_technology => c_tech_arria10_e3sge3,
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_nof_channels => g_nof_channels
+ u_ip_arria10_e3sge3_eth_10g : ip_arria10_e3sge3_eth_10g
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels,
+ g_direction => g_direction,
+ g_pre_header_padding => g_pre_header_padding
)
- PORT MAP (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ PORT MAP(
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => tr_ref_clk_644,
- reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
- reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,
+ -- Data clocks
+ clk_312 => clk_312,
+ clk_156 => clk_156,
+ rst_156 => rst_156,
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => tr_ref_clk_644,
-
- -- XGMII clocks
- clk_156 => clk_156,
- rst_156 => rst_156,
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- -- XGMII interface
- xgmii_tx_ready_arr => xgmii_tx_ready_arr,
- xgmii_rx_ready_arr => OPEN,
- xgmii_tx_dc_arr => xgmii_tx_dc_arr,
- xgmii_rx_dc_arr => xgmii_rx_dc_arr,
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
- -- PHY serial IO
- tx_serial_arr => serial_tx_arr,
- rx_serial_arr => serial_rx_arr
- );
-
-
- gen_reg_eth10g : FOR I IN 0 TO g_nof_channels-1 GENERATE
- mm_reg_eth10g_arr(I) <= RESIZE_UVEC(xgmii_link_status_arr(I) & xgmii_tx_ready_arr(I) & i_tx_snk_out_arr(I).xon, c_mem_reg_eth10g_dat_w);
-
- u_reg_map : ENTITY common_lib.common_reg_r_w_dc
- GENERIC MAP (
- g_cross_clock_domain => TRUE,
- g_in_new_latency => 0,
- g_readback => FALSE,
- g_reg => c_mem_reg_eth10g,
- g_init_reg => (OTHERS => '0')
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => rst_156,
- st_clk => clk_156,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_eth10g_mosi_arr(I),
- sla_out => reg_eth10g_miso_arr(I),
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => '1',
- in_reg => mm_reg_eth10g_arr(I),
- out_reg => OPEN
- );
- END GENERATE;
-
-
- -----------------------------------------------------------------------------
- -- MM bus mux
- -----------------------------------------------------------------------------
- u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => g_nof_channels,
- g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
- )
- PORT MAP (
- mosi => mac_mosi,
- miso => mac_miso,
- mosi_arr => mac_mosi_arr,
- miso_arr => mac_miso_arr
- );
+ reg_eth10g_mosi => reg_eth10g_mosi,
+ reg_eth10g_miso => reg_eth10g_miso,
+
+ reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
+ reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,
- u_common_mem_mux_eth10g : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => g_nof_channels,
- g_mult_addr_w => c_mem_reg_eth10g_adr_w
- )
- PORT MAP (
- mosi => reg_eth10g_mosi,
- miso => reg_eth10g_miso,
- mosi_arr => reg_eth10g_mosi_arr,
- miso_arr => reg_eth10g_miso_arr
- );
+ -- ST
+ tx_snk_in_arr => tx_snk_in_arr,
+ tx_snk_out_arr => tx_snk_out_arr,
+
+ rx_src_out_arr => rx_src_out_arr,
+ rx_src_in_arr => rx_src_in_arr,
+
+ -- Serial
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
+ );
-END str;
+END str;
\ No newline at end of file
diff --git a/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd b/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e27377a639f20404f57bf2685197b70c19373a74
--- /dev/null
+++ b/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
@@ -0,0 +1,226 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: IP components declarations for various devices that get wrapped by the tech components
+
+LIBRARY IEEE, technology_lib, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+PACKAGE tech_eth_10g_component_pkg IS
+
+
+ ------------------------------------------------------------------------------
+ -- ip_stratixiv
+ ------------------------------------------------------------------------------
+ COMPONENT ip_stratixiv_eth_10g IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use XAUI IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_pre_header_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 : IN STD_LOGIC; -- 156.25 MHz for XAUI
+ tr_ref_rst_156 : IN STD_LOGIC;
+
+ -- Calibration & reconfig clock
+ cal_rec_clk : IN STD_LOGIC;
+
+ -- Data clocks
+ tx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr_in or connect rx_clk_arr to tx_clk_arr_in
+ tx_rst_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ rx_clk_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ rx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_rst_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
+
+ xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- XAUI control
+ xaui_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ 156 MHz tx_clk_arr_in
+ tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ 156 MHz rx_clk_arr_in
+ rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- XAUI serial IO
+ xaui_tx_arr : OUT t_xaui_arr(g_nof_channels-1 DOWNTO 0);
+ xaui_rx_arr : IN t_xaui_arr(g_nof_channels-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+
+ ------------------------------------------------------------------------------
+ -- ip_arria10
+ ------------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_eth_10g IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_pre_header_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
+
+ -- Data clocks
+ clk_312 : IN STD_LOGIC := '0';
+ clk_156 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
+
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
+
+ reg_eth10g_mosi : IN t_mem_mosi; -- ETH10G (link status register)
+ reg_eth10g_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- Serial
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e3sge3
+ ------------------------------------------------------------------------------
+ COMPONENT ip_arria10_e3sge3_eth_10g IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_pre_header_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
+
+ -- Data clocks
+ clk_312 : IN STD_LOGIC := '0';
+ clk_156 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
+
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
+
+ reg_eth10g_mosi : IN t_mem_mosi; -- ETH10G (link status register)
+ reg_eth10g_miso : OUT t_mem_miso;
+
+ reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- Serial
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+ END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ ------------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_eth_10g IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_pre_header_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
+
+ -- Data clocks
+ clk_312 : IN STD_LOGIC := '0';
+ clk_156 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
+
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
+
+ reg_eth10g_mosi : IN t_mem_mosi; -- ETH10G (link status register)
+ reg_eth10g_miso : OUT t_mem_miso;
+
+ reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- Serial
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+END tech_eth_10g_component_pkg;
+
+PACKAGE BODY tech_eth_10g_component_pkg IS
+
+END tech_eth_10g_component_pkg;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
index 74f7b2b5ee747f0e40daa4c0aa8d336bc37afb7c..c52a5b4d6591555cdf44002915bb2289f5d3b6d7 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
@@ -75,7 +75,7 @@
-- 4) Device A stops sending frames, continuously generates Idle.
--
-LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_xaui_lib, tech_mac_10g_lib;
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_mac_10g_lib, ip_stratixiv_eth_10g_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE common_lib.common_pkg.ALL;
@@ -83,6 +83,7 @@ USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
+USE work.tech_eth_10g_component_pkg.ALL;
ENTITY tech_eth_10g_stratixiv IS
GENERIC (
@@ -133,155 +134,51 @@ END tech_eth_10g_stratixiv;
ARCHITECTURE str OF tech_eth_10g_stratixiv IS
- -- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
- CONSTANT c_check_link_status : BOOLEAN := g_direction/="TX_ONLY";
- CONSTANT c_check_rx_channelaligned : BOOLEAN := g_direction/="TX_ONLY";
- CONSTANT c_check_xgmii_tx_ready : BOOLEAN := g_direction/="RX_ONLY";
-
- -- MAG_10G control status registers
- SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- ST
- SIGNAL i_tx_rst_arr_out : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL i_rx_rst_arr_out : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
-
- SIGNAL txc_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- tx_ready in tx_clk_arr_in domain, can be used for xon flow control
- SIGNAL rxc_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- rx_ready in rx_clk_arr domain, typically leave not connected
-
- SIGNAL txc_rx_channelaligned_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- rx_channelaligned in tx_clk_arr_in domain, from PHY XAUI, indicates
- -- that all 4 RX channels are aligned when asserted
-
- -- XON control
- SIGNAL mac_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- XGMII
- SIGNAL xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels-1 DOWNTO 0); -- 2 bit, from MAC_10g
- SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, from PHY XAUI
- SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
- SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
- SIGNAL xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
-
BEGIN
- -- Clocks and reset
- tx_rst_arr_out <= i_tx_rst_arr_out;
- rx_rst_arr_out <= i_rx_rst_arr_out;
-
- i_tx_rst_arr_out <= NOT txc_tx_ready_arr WHEN g_direction/="RX_ONLY" ELSE i_rx_rst_arr_out; -- in case of RX_ONLY use the rx rst also for tx to have an active rst release, clock domain crossing issues can be ignored
- i_rx_rst_arr_out <= NOT rxc_rx_ready_arr WHEN g_direction/="TX_ONLY" ELSE i_tx_rst_arr_out; -- in case of TX_ONLY use the tx rst also for rx to have an active rst release, clock domain crossing issues can be ignored
-
- xgmii_tx_ready_arr <= txc_tx_ready_arr;
-
- gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
-
- tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
-
- p_xon_flow_control : PROCESS(tx_clk_arr_in)
- VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "00";
- VARIABLE v_txc_rx_channelaligned : STD_LOGIC := '1';
- VARIABLE v_xgmii_tx_ready : STD_LOGIC := '1';
- BEGIN
- IF rising_edge(tx_clk_arr_in(I)) THEN
- tx_snk_out_arr(I).xon <= '0';
-
- -- First gather all conditions that are enabled to affect xon. The default value is such that it enables xon when the condition is not checked.
- IF c_check_link_status =TRUE THEN v_xgmii_link_status := xgmii_link_status_arr(I); END IF; -- check both remote fault [1] and local fault [0]
- IF c_check_rx_channelaligned=TRUE THEN v_txc_rx_channelaligned := txc_rx_channelaligned_arr(I); END IF; -- check that all 4 RX channels are aligned
- IF c_check_xgmii_tx_ready =TRUE THEN v_xgmii_tx_ready := xgmii_tx_ready_arr(I); END IF;
-
- -- Now apply the conditions to xon
- IF v_xgmii_tx_ready='1' AND v_txc_rx_channelaligned='1' AND v_xgmii_link_status="00" THEN
- tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
- END IF;
- END IF;
- END PROCESS;
-
- u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
- GENERIC MAP (
- g_technology => c_tech_stratixiv,
- g_pre_header_padding => g_pre_header_padding
- )
- PORT MAP (
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- csr_mosi => mac_mosi_arr(I),
- csr_miso => mac_miso_arr(I),
-
- -- ST
- tx_clk_156 => tx_clk_arr_in(I),
- tx_rst => i_tx_rst_arr_out(I),
- tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
- tx_snk_out => mac_snk_out_arr(I),
-
- rx_clk_156 => rx_clk_arr_in(I),
- rx_rst => i_rx_rst_arr_out(I),
- rx_src_out => rx_src_out_arr(I), -- 64 bit data
- rx_src_in => rx_src_in_arr(I),
-
- -- XGMII
- xgmii_link_status => xgmii_link_status_arr(I),
- xgmii_tx_data => xgmii_tx_dc_arr(I),
- xgmii_rx_data => xgmii_internal_dc_arr(I)
- );
- END GENERATE;
-
- xgmii_internal_dc_arr <= xgmii_tx_dc_arr WHEN g_direction="TX_ONLY" ELSE xgmii_rx_dc_arr;
-
- u_tech_xaui: ENTITY tech_xaui_lib.tech_xaui
- GENERIC MAP (
- g_technology => c_tech_stratixiv,
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_nof_xaui => g_nof_channels -- Up to 3 (hard XAUI only) supported
+ u_ip_stratixiv_eth_10g : ip_stratixiv_eth_10g
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels,
+ g_direction => g_direction,
+ g_pre_header_padding => g_pre_header_padding
)
- PORT MAP (
- -- Transceiver PLL reference clock
- tr_clk => tr_ref_clk_156,
- tr_rst => tr_ref_rst_156,
+ PORT MAP(
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
- -- Calibration & reconfig clock
- cal_rec_clk => cal_rec_clk,
+ -- Calibration & reconfig clock
+ cal_rec_clk => cal_rec_clk,
- -- MM interface
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ -- Data clocks
+ tx_clk_arr_in => tx_clk_arr_in,
+ tx_rst_arr_out => tx_rst_arr_out,
+ rx_clk_arr_out => rx_clk_arr_out,
+ rx_clk_arr_in => rx_clk_arr_in,
+ rx_rst_arr_out => rx_rst_arr_out,
- xaui_mosi => xaui_mosi,
- xaui_miso => xaui_miso,
-
- -- XGMII interface
- tx_clk_arr => tx_clk_arr_in,
- rx_clk_arr_out => rx_clk_arr_out,
- rx_clk_arr_in => rx_clk_arr_in,
-
- txc_tx_ready_arr => txc_tx_ready_arr, -- tx_ready in tx_clk_arr_in domain, can be used for xon flow control
- rxc_rx_ready_arr => rxc_rx_ready_arr, -- rx_ready in rx_clk_arr domain, typically leave not connected
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- txc_rx_channelaligned_arr => txc_rx_channelaligned_arr, -- rx_channelaligned in tx_clk_arr_in domain, indicates that all 4 RX channels are aligned when asserted
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
- xgmii_tx_dc_arr => xgmii_tx_dc_arr,
- xgmii_rx_dc_arr => xgmii_rx_dc_arr,
+ xaui_mosi => xaui_mosi,
+ xaui_miso => xaui_miso,
- -- XAUI serial IO
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr
+ -- ST
+ tx_snk_in_arr => tx_snk_in_arr,
+ tx_snk_out_arr => tx_snk_out_arr,
+
+ rx_src_out_arr => rx_src_out_arr,
+ rx_src_in_arr => rx_src_in_arr,
+
+ -- XAUI serial IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr
);
-
- -----------------------------------------------------------------------------
- -- MM bus mux
- -----------------------------------------------------------------------------
- u_common_mem_mux : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => g_nof_channels,
- g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_stratixiv)
- )
- PORT MAP (
- mosi => mac_mosi,
- miso => mac_miso,
- mosi_arr => mac_mosi_arr,
- miso_arr => mac_miso_arr
- );
END str;