diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 509125ec50daa4d37b6adc61a299461cad233b20..3c8d9c9106f3d963efd61d963344c0a20bdecf5d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -16,7 +16,7 @@ parameters:
- { name: c_Q_fft, value: 2 }
- { name: c_P_sq, value: 1 + c_N_pn_lb // 2 } # = 1 + 16 // 2 = 9, on revision xsub_one only first X_sq cell is used
- { name: c_X_sq, value: c_S_pn * c_S_pn } # = 144
- - { name: c_N_crosslets, value: 1 }
+ - { name: c_N_crosslets, value: 7 }
- { name: c_N_taps, value: 16 }
- { name: c_W_adc_jesd, value: 16 }
- { name: c_W_adc, value: 14 }
@@ -239,6 +239,10 @@ peripherals:
mm_port_names:
- REG_CROSSLETS_INFO
+ - peripheral_name: sdp/sdp_nof_crosslets
+ mm_port_names:
+ - REG_NOF_CROSSLETS
+
- peripheral_name: common/common_variable_delay
peripheral_group: xst
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
index f0239e54ab205cd43041c62ddad0f2a0cd40dcf0..c3443fc5a6c8e32b4ef5664acba5275d01ae9837 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
@@ -208,118 +208,24 @@ number_of_columns = 13
- - - - mon_output_sync_bsn 0x00050009 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x0005000a - - - b[31:0] b[63:32] - -
- - - - block_size 0x0005000b 1 RO uint32 b[31:0] - - -
- RAM_ST_XSQ 1 9 RAM data 0x00054000 144 RW cint64_ir b[31:0] b[31:0] - 1024
- - - - - - 0x00054001 - - - b[31:0] b[63:32] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x00058000 15 RW uint32 b[31:0] - - -
- - - - - step 0x0005800f 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x0005a000 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x0005c000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005c001 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x0005c002 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x0005c003 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x0005c004 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x0005c005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x0005c006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_xst_signal_input_b_index 0x0005c006 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_xst_signal_input_a_index 0x0005c006 1 RW uint32 b[15:8] - - -
- - - - - sdp_data_id_xst_subband_index 0x0005c006 1 RW uint32 b[24:16] - - -
- - - - - sdp_data_id_xst_reserved 0x0005c006 1 RW uint32 b[31:25] - - -
- - - - - sdp_integration_interval 0x0005c007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x0005c008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x0005c009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0005c00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0005c00b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0005c00c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0005c00d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0005c00e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0005c00f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0005c010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0005c011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0005c012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0005c013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0005c014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0005c015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0005c016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0005c017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0005c018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0005c019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0005c01a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0005c01b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0005c01c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0005c01d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0005c01e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0005c01f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0005c020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0005c021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0005c022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0005c023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0005c024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0005c025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0005c026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0005c027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005c028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0005c029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005c02a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0005c02b 1 RW uint32 b[15:0] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x0005e000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x00064000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x0006c000 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x0006c001 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x0006e000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x0006e001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x0006e002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x0006e003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x0006e004 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x0006e005 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x0006e006 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x0006e007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0006e008 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x0006e009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0006e00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0006e00b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0006e00c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0006e00d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0006e00e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0006e00f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0006e010 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0006e011 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0006e012 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0006e013 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0006e014 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0006e015 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0006e016 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0006e017 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0006e018 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0006e019 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0006e01a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0006e01b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0006e01c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0006e01d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0006e01e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0006e01f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0006e020 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0006e021 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0006e022 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0006e023 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0006e024 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0006e025 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0006e026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0006e027 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0006e028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0006e029 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x00070000 1 RW uint32 b[0:0] - 2 2
- RAM_ST_BST 2 1 RAM data 0x00072000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - - 0x00072001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x00074000 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00076000 1 RW uint64 b[31:0] b[31:0] 64 64
+ RAM_ST_XSQ 1 9 RAM data 0x00060000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
+ - - - - - 0x00060001 - - - b[31:0] b[63:32] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00070000 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0007000f 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00072000 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x00072001 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x00074000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00076000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00076001 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00076002 1 RW uint32 b[15:0] - - -
- - - - nof_statistics_per_packet 0x00076003 1 RW uint32 b[15:0] - - -
- - - - nof_bytes_per_statistic 0x00076004 1 RW uint32 b[7:0] - - -
- - - - nof_signal_inputs 0x00076005 1 RW uint32 b[7:0] - - -
- - - - sdp_data_id 0x00076006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x00076006 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x00076006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_data_id_xst_signal_input_b_index 0x00076006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_xst_signal_input_a_index 0x00076006 1 RW uint32 b[15:8] - - -
+ - - - - sdp_data_id_xst_subband_index 0x00076006 1 RW uint32 b[24:16] - - -
+ - - - - sdp_data_id_xst_reserved 0x00076006 1 RW uint32 b[31:25] - - -
- - - - sdp_integration_interval 0x00076007 1 RW uint32 b[23:0] - - -
- - - - sdp_reserved 0x00076008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00076009 1 RW uint32 b[4:0] - - -
@@ -357,182 +263,278 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00076029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0007602a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0007602b 1 RW uint32 b[15:0] - - -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00078000 1 RW uint32 b[0:0] - - -
- - - - - rx_transfer_status 0x00078001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x00078002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x00078040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x00078080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x000780c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000780c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x000780c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000780c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x00078100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x00078140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x00078800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x00078801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x00078802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x00078803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x00078804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x00078805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x00078806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x00078807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x00078808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x00078809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x0007880a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x0007880b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x00078818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x00078c00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x00078c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x00078c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x00078c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x00078c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x00078c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x00078c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x00078c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x00078c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x00078c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x00078c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x00078c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x00078c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x00078c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x00078c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x00078c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x00078c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x00078c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x00078c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x00078c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x00078c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x00078c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x00078c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x00078c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x00078c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x00078c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x00078c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x00078c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x00078c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x00078c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x00078c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x00079001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x00079040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x00079080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x000790c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000790c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x00079100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x00079140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x00079141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x00079142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x00079180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x00079181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x00079182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x00079183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x00079184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x00079185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x00079186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x00079187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x00079190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x00079191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x00079192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x00079193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x00079194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x00079195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x00079196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x00079197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x000791a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x00079200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x00079201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x00079202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x00079801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x00079c00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x00079c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x00079c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x00079c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x00079c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x00079c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x00079c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x00079c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x00079c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x00079c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x00079c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x00079c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x00079c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x00079c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x00079c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x00079c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x00079c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x00079c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x00079c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x00079c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x00079c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x00079c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x00079c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x00079c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x00079c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x00079c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x00079c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x00079c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x00079c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x00079c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x00079c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0007a000 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x0007a000 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x0007a000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ RAM_SS_SS_WIDE 2 6 RAM data 0x00078000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x0007c000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x00084000 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00084001 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00086000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00086001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00086002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00086003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00086004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00086005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00086006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00086007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00086008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00086009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0008600a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0008600b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0008600c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0008600d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0008600e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0008600f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00086010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00086011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00086012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00086013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00086014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00086015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00086016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00086017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00086018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00086019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0008601a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0008601b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0008601c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0008601d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0008601e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0008601f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00086020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00086021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00086022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00086023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00086024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00086025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00086026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00086027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00086028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00086029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x00088000 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x0008a000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x0008a001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x0008c000 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x0008e000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x0008e001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x0008e002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x0008e003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x0008e004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x0008e005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x0008e006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x0008e006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x0008e006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x0008e007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x0008e008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x0008e009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0008e00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0008e00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0008e00c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0008e00d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0008e00e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0008e00f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0008e010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0008e011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0008e012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0008e013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0008e014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0008e015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0008e016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0008e017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0008e018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0008e019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0008e01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0008e01b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0008e01c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0008e01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0008e01e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0008e01f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0008e020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0008e021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0008e022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0008e023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0008e024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0008e025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0008e026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0008e027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0008e028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0008e029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0008e02a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0008e02b 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00090000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00090001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00090002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00090040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00090080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000900c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000900c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000900c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000900c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00090100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00090140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00090800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00090801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00090802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00090803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00090804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00090805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00090806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00090807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00090808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00090809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0009080a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0009080b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00090818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00090c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00090c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00090c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00090c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00090c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00090c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00090c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00090c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00090c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00090c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00090c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00090c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00090c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00090c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00090c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00090c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00090c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00090c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00090c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00090c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00090c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00090c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00090c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00090c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00090c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00090c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00090c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00090c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00090c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00090c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00090c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00091001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00091040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00091080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000910c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000910c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00091100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00091140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00091141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00091142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00091180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00091181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00091182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00091183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00091184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00091185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00091186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00091187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00091190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00091191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00091192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00091193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00091194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00091195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00091196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00091197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000911a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00091200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00091201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00091202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00091801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00091c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00091c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00091c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00091c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00091c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00091c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00091c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00091c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00091c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00091c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00091c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00091c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00091c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00091c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00091c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00091c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00091c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00091c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00091c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00091c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00091c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00091c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00091c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00091c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00091c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00091c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00091c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00091c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00091c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00091c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00091c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00092000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00092000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00092000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
index bea7b3e1fda3b7297dc06601b7ba20ee2898fcbb..7c35bf580d03dbd550e66b4b88f626ec2a4e5913 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
@@ -36,88 +36,88 @@ number_of_columns = 13
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x0002f048 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0002f030 6 RO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x0003b048 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0003b030 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x0002f06c 1 RO uint32 b[29:0] - - -
- - - - - stable 0x0002f06c 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x0002f06c 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x0002f06d 1 RW uint32 b[27:0] - - -
- - - - - edge 0x0002f06d 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x0002f06e 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x0002f050 1 WO uint32 b[23:0] - - -
- - - - - rden 0x0002f051 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x0002f052 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x0002f053 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x0002f054 1 WO uint32 b[0:0] - - -
- - - - - busy 0x0002f055 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x0002f056 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x0002f082 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x0002f080 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x0002f07e 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x0002f07f 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x0002f07c 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x0002f058 1 WO uint32 b[31:0] - - -
- - - - - param 0x0002f059 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x0002f05a 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x0002f05b 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x0002f05c 1 RO uint32 b[23:0] - - -
- - - - - data_in 0x0002f05d 1 WO uint32 b[23:0] - - -
- - - - - busy 0x0002f05e 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG block_period 0x0002f020 1 RO uint32 b[15:0] - - -
- - - - - n_rn 0x0002f021 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x0002f022 1 RW uint32 b[7:0] - - -
- - - - - n_si 0x0002f023 1 RW uint32 b[7:0] - - -
- - - - - o_si 0x0002f024 1 RW uint32 b[7:0] - - -
- - - - - beam_repositioning_flag 0x0002f025 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x0002f026 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x0002f027 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x0002f028 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x0002f029 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x0002f02a 1 RO uint32 b[0:0] - - -
- - - - - station_id 0x0002f02b 1 RW uint32 b[15:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x0002f072 1 RW uint32 b[30:0] - - -
- - - - - reset 0x0002f072 1 RW uint32 b[31:31] - - -
- JESD204B 1 12 REG rx_dll_ctrl 0x0002e014 1 RW uint32 b[16:0] - - 256
- - - - - rx_syncn_sysref_ctrl 0x0002e015 1 RW uint32 b[24:0] - - -
- - - - - rx_csr_sysref_always_on 0x0002e015 1 RW uint32 b[1:1] - - -
- - - - - rx_csr_rbd_offset 0x0002e015 1 RW uint32 b[10:3] - - -
- - - - - rx_csr_lmfc_offset 0x0002e015 1 RW uint32 b[19:12] - - -
- - - - - rx_err0 0x0002e018 1 RW uint32 b[8:0] - - -
- - - - - rx_err1 0x0002e019 1 RW uint32 b[9:0] - - -
- - - - - csr_dev_syncn 0x0002e020 1 RO uint32 b[0:0] - - -
- - - - - csr_rbd_count 0x0002e020 1 RO uint32 b[10:3] - - -
- - - - - rx_status1 0x0002e021 1 RW uint32 b[23:0] - - -
- - - - - rx_status2 0x0002e022 1 RW uint32 b[23:0] - - -
- - - - - rx_status3 0x0002e023 1 RW uint32 b[7:0] - - -
- - - - - rx_ilas_csr_l 0x0002e025 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_f 0x0002e025 1 RW uint32 b[15:8] - - -
- - - - - rx_ilas_csr_k 0x0002e025 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_m 0x0002e025 1 RW uint32 b[31:24] - - -
- - - - - rx_ilas_csr_n 0x0002e026 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_cs 0x0002e026 1 RW uint32 b[7:6] - - -
- - - - - rx_ilas_csr_np 0x0002e026 1 RW uint32 b[12:8] - - -
- - - - - rx_ilas_csr_subclassv 0x0002e026 1 RW uint32 b[15:13] - - -
- - - - - rx_ilas_csr_s 0x0002e026 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_jesdv 0x0002e026 1 RW uint32 b[23:21] - - -
- - - - - rx_ilas_csr_cf 0x0002e026 1 RW uint32 b[28:24] - - -
- - - - - rx_ilas_csr_hd 0x0002e026 1 RW uint32 b[31:31] - - -
- - - - - rx_status4 0x0002e03c 1 RW uint32 b[15:0] - - -
- - - - - rx_status5 0x0002e03d 1 RW uint32 b[15:0] - - -
- - - - - rx_status6 0x0002e03e 1 RW uint32 b[23:0] - - -
- - - - - rx_status7 0x0002e03f 1 RO uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x0003b06c 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x0003b06c 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x0003b06c 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x0003b06d 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x0003b06d 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x0003b06e 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x0003b050 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x0003b051 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x0003b052 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x0003b053 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x0003b054 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x0003b055 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x0003b056 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x0003b084 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x0003b082 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x0003b080 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x0003b081 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x0003b07e 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0003b058 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0003b059 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0003b05a 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0003b05b 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0003b05c 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x0003b05d 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x0003b05e 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x0003b020 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x0003b021 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0003b022 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x0003b023 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x0003b024 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x0003b025 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x0003b026 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x0003b027 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x0003b028 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x0003b029 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x0003b02a 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x0003b02b 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0003b074 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0003b074 1 RW uint32 b[31:31] - - -
+ JESD204B 1 12 REG rx_dll_ctrl 0x0003a014 1 RW uint32 b[16:0] - - 256
+ - - - - rx_syncn_sysref_ctrl 0x0003a015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x0003a015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x0003a015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x0003a015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x0003a018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x0003a019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x0003a020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x0003a020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x0003a021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x0003a022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x0003a023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x0003a025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x0003a025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x0003a025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x0003a025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x0003a026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x0003a026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x0003a026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x0003a026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x0003a026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x0003a026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x0003a026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x0003a026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0003a03c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0003a03d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0003a03e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0003a03f 1 RO uint32 b[31:0] - - -
REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x0002f040 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x0002f040 1 RW uint32 b[1:1] - - -
- - - - - nof_clk_per_sync 0x0002f041 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x0002f042 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002f043 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x0002f044 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0002f078 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002f079 - - - b[31:0] b[63:32] - -
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x0003b040 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x0003b040 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x0003b041 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x0003b042 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0003b043 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x0003b044 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0003b07a 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0003b07b - - - b[31:0] b[63:32] - -
REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
@@ -134,7 +134,7 @@ number_of_columns = 13
- - - - phase 0x00000d01 1 RW uint32 b[15:0] - - -
- - - - freq 0x00000d02 1 RW uint32 b[30:0] - - -
- - - - ampl 0x00000d03 1 RW uint32 b[16:0] - - -
- RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - - 1024
+ RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - - 1024
RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d40 1 RO int64 b[31:0] b[31:0] - 4
- - - - - 0x00000d41 - - - b[31:0] b[63:32] - -
@@ -143,13 +143,13 @@ number_of_columns = 13
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - - 1024
- REG_SI 1 1 REG enable 0x0002f07a 1 RW uint32 b[0:0] - - -
- RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x0002c000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x0002f076 1 RW uint32 b[0:0] - - -
- RAM_ST_SST 1 6 RAM data 0x00028000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - - 0x00028001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x0002f070 1 RW uint32 b[0:0] - - -
+ REG_SI 1 1 REG enable 0x0003b07c 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00030000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00038000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x0003b078 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00034000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x00034001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x0003b072 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
@@ -196,23 +196,25 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
- REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x0002f000 1 RW uint32 b[0:0] - - -
- - - - - ctrl_interval_size 0x0002f001 1 RW uint32 b[30:0] - - -
- - - - - ctrl_start_bsn 0x0002f002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002f003 - - - b[31:0] b[63:32] - -
- - - - - mon_current_input_bsn 0x0002f004 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002f005 - - - b[31:0] b[63:32] - -
- - - - - mon_input_bsn_at_sync 0x0002f006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002f007 - - - b[31:0] b[63:32] - -
- - - - - mon_output_enable 0x0002f008 1 RO uint32 b[0:0] - - -
- - - - - mon_output_sync_bsn 0x0002f009 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002f00a - - - b[31:0] b[63:32] - -
- - - - - block_size 0x0002f00b 1 RO uint32 b[31:0] - - -
- RAM_ST_XSQ 1 9 RAM data 0x00018000 144 RW cint64_ir b[31:0] b[31:0] - 1024
- - - - - - 0x00018001 - - - b[31:0] b[63:32] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x0002f010 15 RW uint32 b[31:0] - - -
- - - - - step 0x0002f01f 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x00000c02 1 RW uint32 b[0:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x0003b000 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x0003b001 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x0003b002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0003b003 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x0003b004 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0003b005 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x0003b006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0003b007 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x0003b008 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x0003b009 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0003b00a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x0003b00b 1 RO uint32 b[31:0] - - -
+ RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
+ - - - - - 0x00010001 - - - b[31:0] b[63:32] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x0003b010 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0003b01f 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00000c02 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x00000c03 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x0003b070 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
@@ -261,10 +263,10 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0000006a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x0001c000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x00010000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x0002f068 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x0002f069 1 RW uint32 b[31:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x00028000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00020000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x0003b068 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x0003b069 1 RW uint32 b[31:0] - - -
REG_HDR_DAT 2 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00000c81 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c82 1 RW uint32 b[15:0] - - -
@@ -307,10 +309,10 @@ number_of_columns = 13
- - - - - 0x00000ca7 - - - b[15:0] b[47:32] - -
- - - - eth_destination_mac 0x00000ca8 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000ca9 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x0002f064 1 RW uint32 b[0:0] - 2 2
+ REG_DP_XONOFF 2 1 REG enable_stream 0x0003b064 1 RW uint32 b[0:0] - 2 2
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00001001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x0002f060 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x0003b060 1 RW uint32 b[0:0] - 2 2
REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00000081 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000082 1 RW uint32 b[15:0] - - -
@@ -533,6 +535,6 @@ number_of_columns = 13
- - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0002f074 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x0002f074 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x0002f074 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0003b076 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x0003b076 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x0003b076 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index 5ebf7fc59cf7c62788b277e3550eb49a528bfb26..0334ddb82c210830babdefb7bded22673e4d1dd3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xB0000' end='0xB8000' datawidth='32' /><slave name='jesd204b.mem' start='0xB8000' end='0xBC000' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xBC000' end='0xBC040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xBC040' end='0xBC080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xBC080' end='0xBC0C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xBC0C0' end='0xBC100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xBC100' end='0xBC120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xBC120' end='0xBC140' datawidth='32' /><slave name='reg_epcs.mem' start='0xBC140' end='0xBC160' datawidth='32' /><slave name='reg_remu.mem' start='0xBC160' end='0xBC180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xBC180' end='0xBC190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xBC190' end='0xBC1A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xBC1A0' end='0xBC1B0' datawidth='32' /><slave name='pio_pps.mem' start='0xBC1B0' end='0xBC1C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xBC1C0' end='0xBC1C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xBC1C8' end='0xBC1D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xBC1D0' end='0xBC1D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xBC1D8' end='0xBC1E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xBC1E0' end='0xBC1E8' datawidth='32' /><slave name='reg_si.mem' start='0xBC1E8' end='0xBC1F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xBC1F0' end='0xBC1F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xBC1F8' end='0xBC200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xBC200' end='0xBC208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xBC208' end='0xBC210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xBC210' end='0xBC218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xEC000' end='0xEC040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xEC040' end='0xEC080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xEC080' end='0xEC0C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xEC0C0' end='0xEC100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xEC100' end='0xEC120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xEC120' end='0xEC140' datawidth='32' /><slave name='reg_epcs.mem' start='0xEC140' end='0xEC160' datawidth='32' /><slave name='reg_remu.mem' start='0xEC160' end='0xEC180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xEC180' end='0xEC190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xEC190' end='0xEC1A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xEC1A0' end='0xEC1B0' datawidth='32' /><slave name='pio_pps.mem' start='0xEC1B0' end='0xEC1C0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xEC1C0' end='0xEC1C8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xEC1C8' end='0xEC1D0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xEC1D0' end='0xEC1D8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xEC1D8' end='0xEC1E0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xEC1E0' end='0xEC1E8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xEC1E8' end='0xEC1F0' datawidth='32' /><slave name='reg_si.mem' start='0xEC1F0' end='0xEC1F8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xEC1F8' end='0xEC200' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC200' end='0xEC208' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC208' end='0xEC210' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC210' end='0xEC218' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC218' end='0xEC220' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xB0000' end='0xB8000' datawidth='32' /><slave name='jesd204b.mem' start='0xB8000' end='0xBC000' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xBC000' end='0xBC040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xBC040' end='0xBC080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xBC080' end='0xBC0C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xBC0C0' end='0xBC100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xBC100' end='0xBC120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xBC120' end='0xBC140' datawidth='32' /><slave name='reg_epcs.mem' start='0xBC140' end='0xBC160' datawidth='32' /><slave name='reg_remu.mem' start='0xBC160' end='0xBC180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xBC180' end='0xBC190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xBC190' end='0xBC1A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xBC1A0' end='0xBC1B0' datawidth='32' /><slave name='pio_pps.mem' start='0xBC1B0' end='0xBC1C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xBC1C0' end='0xBC1C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xBC1C8' end='0xBC1D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xBC1D0' end='0xBC1D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xBC1D8' end='0xBC1E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xBC1E0' end='0xBC1E8' datawidth='32' /><slave name='reg_si.mem' start='0xBC1E8' end='0xBC1F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xBC1F0' end='0xBC1F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xBC1F8' end='0xBC200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xBC200' end='0xBC208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xBC208' end='0xBC210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xBC210' end='0xBC218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xEC000' end='0xEC040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xEC040' end='0xEC080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xEC080' end='0xEC0C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xEC0C0' end='0xEC100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xEC100' end='0xEC120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xEC120' end='0xEC140' datawidth='32' /><slave name='reg_epcs.mem' start='0xEC140' end='0xEC160' datawidth='32' /><slave name='reg_remu.mem' start='0xEC160' end='0xEC180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xEC180' end='0xEC190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xEC190' end='0xEC1A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xEC1A0' end='0xEC1B0' datawidth='32' /><slave name='pio_pps.mem' start='0xEC1B0' end='0xEC1C0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xEC1C0' end='0xEC1C8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xEC1C8' end='0xEC1D0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xEC1D0' end='0xEC1D8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xEC1D8' end='0xEC1E0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xEC1E0' end='0xEC1E8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xEC1E8' end='0xEC1F0' datawidth='32' /><slave name='reg_si.mem' start='0xEC1F0' end='0xEC1F8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xEC1F8' end='0xEC200' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC200' end='0xEC208' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC208' end='0xEC210' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC210' end='0xEC218' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC218' end='0xEC220' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
index 058e6e8b5e0d547b5ee4c124f36c45a1c76b2ec4..795b840fd971527aed9c532f0072f3cd2b2189e1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">65536</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">262144</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>13</spirit:right>
+ <spirit:right>15</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>13</spirit:right>
+ <spirit:right>15</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">14</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
new file mode 100644
index 0000000000000000000000000000000000000000..79f7f5c6f6bbf05638f961faacb608cc52e0be10
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
@@ -0,0 +1,1439 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index f5eeb361be880d8c3a74f8e7048713272ea6d137..1ed2d9fa0a388ee0aaade7021cf2fdef0bb25361 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "753664";
+ value = "950272";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "770576";
+ value = "967192";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "770504";
+ value = "967120";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "770480";
+ value = "967088";
type = "String";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "262144";
+ value = "524288";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "720896";
+ value = "917504";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "589824";
+ value = "786432";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "458752";
+ value = "655360";
type = "String";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "655360";
+ value = "851968";
type = "String";
}
}
@@ -362,7 +362,7 @@
{
datum baseAddress
{
- value = "393216";
+ value = "262144";
type = "String";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "720896";
type = "String";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "770464";
+ value = "967072";
type = "String";
}
}
@@ -442,7 +442,7 @@
{
datum baseAddress
{
- value = "770528";
+ value = "967144";
type = "String";
}
}
@@ -458,7 +458,7 @@
{
datum baseAddress
{
- value = "770304";
+ value = "966912";
type = "String";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "770048";
+ value = "966656";
type = "String";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "770112";
+ value = "966720";
type = "String";
}
}
@@ -522,7 +522,7 @@
{
datum baseAddress
{
- value = "770520";
+ value = "967136";
type = "String";
}
}
@@ -554,7 +554,7 @@
{
datum baseAddress
{
- value = "770448";
+ value = "967056";
type = "String";
}
}
@@ -575,7 +575,7 @@
{
datum baseAddress
{
- value = "770568";
+ value = "967184";
type = "String";
}
}
@@ -596,7 +596,7 @@
{
datum baseAddress
{
- value = "770560";
+ value = "967176";
type = "String";
}
}
@@ -617,7 +617,7 @@
{
datum baseAddress
{
- value = "770368";
+ value = "966976";
type = "String";
}
}
@@ -633,7 +633,7 @@
{
datum baseAddress
{
- value = "770336";
+ value = "966944";
type = "String";
}
}
@@ -654,7 +654,7 @@
{
datum baseAddress
{
- value = "770240";
+ value = "966848";
type = "String";
}
}
@@ -691,7 +691,7 @@
{
datum baseAddress
{
- value = "770552";
+ value = "967168";
type = "String";
}
}
@@ -712,7 +712,23 @@
{
datum baseAddress
{
- value = "770544";
+ value = "967160";
+ type = "String";
+ }
+ }
+ element reg_nof_crosslets
+ {
+ datum _sortIndex
+ {
+ value = "57";
+ type = "int";
+ }
+ }
+ element reg_nof_crosslets.mem
+ {
+ datum baseAddress
+ {
+ value = "12296";
type = "String";
}
}
@@ -728,7 +744,7 @@
{
datum baseAddress
{
- value = "770512";
+ value = "967128";
type = "String";
}
}
@@ -765,7 +781,7 @@
{
datum baseAddress
{
- value = "770400";
+ value = "967008";
type = "String";
}
}
@@ -781,7 +797,7 @@
{
datum baseAddress
{
- value = "770176";
+ value = "966784";
type = "String";
}
}
@@ -797,7 +813,7 @@
{
datum baseAddress
{
- value = "770536";
+ value = "967152";
type = "String";
}
}
@@ -813,7 +829,7 @@
{
datum baseAddress
{
- value = "770432";
+ value = "967040";
type = "String";
}
}
@@ -829,7 +845,7 @@
{
datum baseAddress
{
- value = "770496";
+ value = "967112";
type = "String";
}
}
@@ -845,7 +861,7 @@
{
datum baseAddress
{
- value = "12296";
+ value = "967104";
type = "String";
}
}
@@ -2321,6 +2337,41 @@
internal="reg_mmdp_data.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_nof_crosslets_address"
+ internal="reg_nof_crosslets.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_clk"
+ internal="reg_nof_crosslets.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_read"
+ internal="reg_nof_crosslets.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_readdata"
+ internal="reg_nof_crosslets.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_reset"
+ internal="reg_nof_crosslets.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_write"
+ internal="reg_nof_crosslets.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_writedata"
+ internal="reg_nof_crosslets.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_nw_10gbe_eth10g_address"
internal="reg_nw_10gbe_eth10g.address"
@@ -5805,7 +5856,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xB0000' end='0xB8000' datawidth='32' /><slave name='jesd204b.mem' start='0xB8000' end='0xBC000' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xBC000' end='0xBC040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xBC040' end='0xBC080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xBC080' end='0xBC0C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xBC0C0' end='0xBC100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xBC100' end='0xBC120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xBC120' end='0xBC140' datawidth='32' /><slave name='reg_epcs.mem' start='0xBC140' end='0xBC160' datawidth='32' /><slave name='reg_remu.mem' start='0xBC160' end='0xBC180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xBC180' end='0xBC190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xBC190' end='0xBC1A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xBC1A0' end='0xBC1B0' datawidth='32' /><slave name='pio_pps.mem' start='0xBC1B0' end='0xBC1C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xBC1C0' end='0xBC1C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xBC1C8' end='0xBC1D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xBC1D0' end='0xBC1D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xBC1D8' end='0xBC1E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xBC1E0' end='0xBC1E8' datawidth='32' /><slave name='reg_si.mem' start='0xBC1E8' end='0xBC1F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xBC1F0' end='0xBC1F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xBC1F8' end='0xBC200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xBC200' end='0xBC208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xBC208' end='0xBC210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xBC210' end='0xBC218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xEC000' end='0xEC040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xEC040' end='0xEC080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xEC080' end='0xEC0C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xEC0C0' end='0xEC100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xEC100' end='0xEC120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xEC120' end='0xEC140' datawidth='32' /><slave name='reg_epcs.mem' start='0xEC140' end='0xEC160' datawidth='32' /><slave name='reg_remu.mem' start='0xEC160' end='0xEC180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xEC180' end='0xEC190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xEC190' end='0xEC1A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xEC1A0' end='0xEC1B0' datawidth='32' /><slave name='pio_pps.mem' start='0xEC1B0' end='0xEC1C0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xEC1C0' end='0xEC1C8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xEC1C8' end='0xEC1D0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xEC1D0' end='0xEC1D8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xEC1D8' end='0xEC1E0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xEC1E0' end='0xEC1E8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xEC1E8' end='0xEC1F0' datawidth='32' /><slave name='reg_si.mem' start='0xEC1F0' end='0xEC1F8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xEC1F8' end='0xEC200' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC200' end='0xEC208' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC208' end='0xEC210' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC210' end='0xEC218' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC218' end='0xEC220' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -15852,7 +15903,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15916,7 +15967,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15985,7 +16036,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16391,11 +16442,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28772,7 +28823,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_eth10g"
+ name="reg_nof_crosslets"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29358,37 +29409,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_mac"
+ name="reg_nw_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29404,7 +29455,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29468,7 +29519,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29537,7 +29588,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29943,11 +29994,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29974,37 +30025,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_nw_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30020,7 +30071,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30084,7 +30135,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30153,7 +30204,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30559,11 +30610,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30590,37 +30641,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_sdp_info"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30636,7 +30687,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30700,7 +30751,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30769,7 +30820,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31175,11 +31226,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31206,37 +31257,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31252,7 +31303,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31316,7 +31367,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31385,7 +31436,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31791,11 +31842,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31822,37 +31873,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31868,7 +31919,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31932,7 +31983,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32001,7 +32052,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32407,11 +32458,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32438,37 +32489,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_sst"
+ name="reg_stat_enable_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32484,7 +32535,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32548,7 +32599,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32617,7 +32668,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33023,11 +33074,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33054,37 +33105,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_xst"
+ name="reg_stat_enable_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33670,37 +33721,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_bst"
+ name="reg_stat_enable_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33716,7 +33767,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33780,7 +33831,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33849,7 +33900,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34255,11 +34306,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34286,37 +34337,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_sst"
+ name="reg_stat_hdr_dat_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34332,7 +34383,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34396,7 +34447,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34465,7 +34516,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34871,11 +34922,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34902,37 +34953,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_xst"
+ name="reg_stat_hdr_dat_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35518,37 +35569,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_pmbus"
+ name="reg_stat_hdr_dat_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36134,37 +36185,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_sens"
+ name="reg_unb_pmbus"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36750,37 +36801,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wdi"
+ name="reg_unb_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36796,7 +36847,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36860,7 +36911,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36929,7 +36980,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37335,11 +37386,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -37366,37 +37417,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wg"
+ name="reg_wdi"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37412,7 +37463,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37476,7 +37527,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37545,7 +37596,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37951,11 +38002,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -37982,37 +38033,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="rom_system_info"
+ name="reg_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38028,7 +38079,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38092,7 +38143,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38161,7 +38212,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38567,11 +38618,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -38598,37 +38649,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_rom_system_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="timer_0"
+ name="rom_system_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38636,17 +38687,17 @@
<boundary>
<interfaces>
<interface>
- <name>clk</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -38655,27 +38706,26 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>irq</name>
- <type>interrupt</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>irq</name>
- <role>irq</role>
+ <name>coe_clk_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -38687,106 +38737,63 @@
</assignments>
<parameters>
<parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>timer_0.s1</value>
- </entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
</entry>
<entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>s1</name>
+ <name>mem</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>address</name>
+ <name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>writedata</name>
- <role>writedata</role>
+ <name>avs_mem_write</name>
+ <role>write</role>
<direction>Input</direction>
- <width>16</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>16</width>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>chipselect</name>
- <role>chipselect</role>
+ <name>avs_mem_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -38807,17 +38814,13 @@
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
- <entry>
- <key>embeddedsw.configuration.isTimerDevice</key>
- <value>1</value>
- </entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
- <value>NATIVE</value>
+ <value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
@@ -38825,7 +38828,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38837,11 +38840,675 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
+ <value>system</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>15</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_rom_system_info</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="timer_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>irq</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>irq</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>timer_0.s1</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>s1</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <role>chipselect</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>write_n</name>
+ <role>write_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isTimerDevice</key>
+ <value>1</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>NATIVE</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -39356,7 +40023,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x000bc210" />
+ <parameter name="baseAddress" value="0x000ec218" />
</connection>
<connection
kind="avalon"
@@ -39391,7 +40058,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x000bc1b0" />
+ <parameter name="baseAddress" value="0x000ec1b0" />
</connection>
<connection
kind="avalon"
@@ -39405,49 +40072,49 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x000bc160" />
+ <parameter name="baseAddress" value="0x000ec160" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x000bc140" />
+ <parameter name="baseAddress" value="0x000ec140" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x000bc208" />
+ <parameter name="baseAddress" value="0x000ec210" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x000bc200" />
+ <parameter name="baseAddress" value="0x000ec208" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x000bc1f8" />
+ <parameter name="baseAddress" value="0x000ec200" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x000bc1f0" />
+ <parameter name="baseAddress" value="0x000ec1f8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x000bc120" />
+ <parameter name="baseAddress" value="0x000ec120" />
</connection>
<connection
kind="avalon"
@@ -39461,28 +40128,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x000bc0c0" />
+ <parameter name="baseAddress" value="0x000ec0c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_st_sst.mem">
- <parameter name="baseAddress" value="0x000a0000" />
+ <parameter name="baseAddress" value="0x000d0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x000bc1e8" />
+ <parameter name="baseAddress" value="0x000ec1f0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
- <parameter name="baseAddress" value="0x00090000" />
+ <parameter name="baseAddress" value="0x000c0000" />
</connection>
<connection
kind="avalon"
@@ -39503,7 +40170,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_wg.mem">
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x000b0000" />
</connection>
<connection
kind="avalon"
@@ -39517,14 +40184,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x000bc1e0" />
+ <parameter name="baseAddress" value="0x000ec1e8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x000bc100" />
+ <parameter name="baseAddress" value="0x000ec100" />
</connection>
<connection
kind="avalon"
@@ -39545,42 +40212,42 @@
version="18.0"
start="cpu_0.data_master"
end="jesd204b.mem">
- <parameter name="baseAddress" value="0x000b8000" />
+ <parameter name="baseAddress" value="0x000e8000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x000bc1d8" />
+ <parameter name="baseAddress" value="0x000ec1e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
- <parameter name="baseAddress" value="0x000b0000" />
+ <parameter name="baseAddress" value="0x000e0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
- <parameter name="baseAddress" value="0x00070000" />
+ <parameter name="baseAddress" value="0x000a0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_bf_weights.mem">
- <parameter name="baseAddress" value="0x00040000" />
+ <parameter name="baseAddress" value="0x00080000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x000bc1a0" />
+ <parameter name="baseAddress" value="0x000ec1a0" />
</connection>
<connection
kind="avalon"
@@ -39594,7 +40261,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x000bc190" />
+ <parameter name="baseAddress" value="0x000ec190" />
</connection>
<connection
kind="avalon"
@@ -39608,14 +40275,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x000bc080" />
+ <parameter name="baseAddress" value="0x000ec080" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x000bc1d0" />
+ <parameter name="baseAddress" value="0x000ec1d8" />
</connection>
<connection
kind="avalon"
@@ -39643,14 +40310,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x000bc1c8" />
+ <parameter name="baseAddress" value="0x000ec1d0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x000bc1c0" />
+ <parameter name="baseAddress" value="0x000ec1c8" />
</connection>
<connection
kind="avalon"
@@ -39664,7 +40331,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
- <parameter name="baseAddress" value="0x000bc180" />
+ <parameter name="baseAddress" value="0x000ec180" />
</connection>
<connection
kind="avalon"
@@ -39678,21 +40345,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x000bc040" />
+ <parameter name="baseAddress" value="0x000ec040" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_st_xsq.mem">
- <parameter name="baseAddress" value="0x00060000" />
+ <parameter name="baseAddress" value="0x00040000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
- <parameter name="baseAddress" value="0x3008" />
+ <parameter name="baseAddress" value="0x000ec1c0" />
</connection>
<connection
kind="avalon"
@@ -39706,7 +40373,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
- <parameter name="baseAddress" value="0x000bc000" />
+ <parameter name="baseAddress" value="0x000ec000" />
</connection>
<connection
kind="avalon"
@@ -39715,6 +40382,13 @@
end="ram_st_histogram.mem">
<parameter name="baseAddress" value="0x8000" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_nof_crosslets.mem">
+ <parameter name="baseAddress" value="0x3008" />
+ </connection>
<connection
kind="avalon"
version="18.0"
@@ -39983,6 +40657,11 @@
version="18.0"
start="clk_0.clk"
end="ram_st_histogram.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_nof_crosslets.system" />
<connection
kind="interrupt"
version="18.0"
@@ -40274,6 +40953,11 @@
version="18.0"
start="clk_0.clk_reset"
end="ram_st_histogram.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_nof_crosslets.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index f36f2cc65cfeefa831d61658599d2ee41550219f..47231fbe541d551d6bdb92c6c48bc09b653a2775 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -70,6 +70,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 3390c4ce2e915beb415c474bb2cc26791980e18a..e7a2f088c467d8b91ec13aba55f7c09e611711ad 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -78,6 +78,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index c26430cca8f28cf5da9c0c199670dd48382c21b6..b2d1eea11539f3d7903d8fa5338780ff8051c768 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -77,6 +77,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
index bdcb9fdfac3e39477e4dc1480e96126282c6fa21..da63f4ad44f09a53a08c7d24de9b661a38da52c5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
@@ -74,6 +74,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
index 48c90eb869b2e85ff23b2fe086665e44666cd49b..518df2c35a131e4190899ba41c3c13401b25edbb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -77,6 +77,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
index fc24b687fddfaee847726ec8b8e5690f254aa374..3ea6397634aea1802adacf6985b0f7f951f34c18 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
@@ -220,7 +220,7 @@ BEGIN
-- Enable xsub
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, 1, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_nof_block_per_sync, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 2f8f0c9f3fc0490a3af9074fe6dd40600443bc4f..3e0d82ec1f8fd82831ceb77191574f26fa194bd6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -280,7 +280,11 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
----------------------------------------------
-- crosslets_info
SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- crosslets_info
+ SIGNAL reg_nof_crosslets_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_nof_crosslets_miso : t_mem_miso := c_mem_miso_rst;
-- bsn_scheduler_xsub
SIGNAL reg_bsn_sync_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -643,7 +647,9 @@ BEGIN
reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
+ reg_nof_crosslets_miso => reg_nof_crosslets_miso,
reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
@@ -743,6 +749,8 @@ BEGIN
-- XSUB
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
+ reg_nof_crosslets_miso => reg_nof_crosslets_miso,
reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index a5002af9f73741ef85cdc67d2e19b1da323838f4..c97efa9fc2080f8c071a0f87e19ad6b4c7e53b70 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -214,6 +214,10 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_crosslets_info_mosi : OUT t_mem_mosi;
reg_crosslets_info_miso : IN t_mem_miso;
+ -- crosslets_info
+ reg_nof_crosslets_mosi : OUT t_mem_mosi;
+ reg_nof_crosslets_miso : IN t_mem_miso;
+
-- bsn_sync_scheduler_xsub
reg_bsn_sync_scheduler_xsub_mosi : OUT t_mem_mosi;
reg_bsn_sync_scheduler_xsub_miso : IN t_mem_miso;
@@ -371,6 +375,9 @@ BEGIN
u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
+ u_mm_file_reg_nof_crosslets : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
+ PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_mosi, reg_nof_crosslets_miso);
+
u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_miso);
@@ -790,6 +797,14 @@ BEGIN
reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_clk_export => OPEN,
+ reg_nof_crosslets_reset_export => OPEN,
+ reg_nof_crosslets_address_export => reg_nof_crosslets_mosi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
+ reg_nof_crosslets_write_export => reg_nof_crosslets_mosi.wr,
+ reg_nof_crosslets_writedata_export => reg_nof_crosslets_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_read_export => reg_nof_crosslets_mosi.rd,
+ reg_nof_crosslets_readdata_export => reg_nof_crosslets_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_mosi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 43cfd5dfa11f988ffadde1d9878cb641e9b44a55..5c5bef332284cbcec6b5e03aa08da1a881858172 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -343,6 +343,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_crosslets_info_reset_export : out std_logic; -- export
reg_crosslets_info_write_export : out std_logic; -- export
reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
@@ -350,7 +357,7 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
ram_st_xsq_clk_export : out std_logic; -- export
ram_st_xsq_read_export : out std_logic; -- export
ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index a0b991efb87598f013bc1b8f1e04e2bf20fa3be8..25a06589b55204a66e325bfac1d79e9eedb36c6d 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -48,6 +48,18 @@ peripherals:
number_of_fields: 15
address_offset: 0x0
+ - peripheral_name: sdp_nof_crosslets # pi_sdp_nof_crosslets.py
+ peripheral_description: "SDP nof crosslets."
+ mm_ports:
+ - mm_port_name: REG_NOF_CROSSLETS
+ mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
+ mm_port_description: |
+ "The SDP nof crosslets contains the number of crosslets that are being sent out the UDP offload
+ where 1 <= nof_crosslets <= N_crosslets_max"
+ fields:
+ - - { field_name: nof_crosslets, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: unused, access_mode: RW, address_offset: 0x4 }
- peripheral_name: sdp_subband_equalizer # pi_sdp_subband_equalizer.py
peripheral_description: "SDP Subband equalizer coefficients."
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 4e578e7da26853edc548e0ea26fa1247d5e1d7dc..530ce569f6a5528af4e6b18a1cbc189deac959c5 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -58,6 +58,8 @@ ENTITY node_sdp_correlator IS
reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso;
reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_crosslets_info_miso : OUT t_mem_miso;
+ reg_nof_crosslets_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_nof_crosslets_miso : OUT t_mem_miso;
ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_st_xsq_miso : OUT t_mem_miso;
reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
@@ -93,7 +95,9 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
- SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
+ SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
+ SIGNAL nof_crosslets_reg : STD_LOGIC_VECTOR(c_sdp_nof_crosslets_reg_w-1 DOWNTO 0);
+ SIGNAL nof_crosslets : STD_LOGIC_VECTOR(c_sdp_nof_crosslets_reg_w-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------
-- Requantize 18b to 16b
@@ -125,7 +129,7 @@ BEGIN
---------------------------------------------------------------
u_crosslets_subband_select : ENTITY work.sdp_crosslets_subband_select
GENERIC MAP (
- g_N_crosslets => c_sdp_N_crosslets
+ g_N_crosslets => c_sdp_N_crosslets_max
)
PORT MAP(
dp_clk => dp_clk,
@@ -172,7 +176,7 @@ BEGIN
gen_dp_to_mm : FOR I IN 0 TO g_P_sq-1 GENERATE
u_st_xsq_dp_to_mm : ENTITY st_lib.st_xsq_dp_to_mm
GENERIC MAP(
- g_nof_crosslets => c_sdp_N_crosslets,
+ g_nof_crosslets => c_sdp_N_crosslets_max,
g_nof_signal_inputs => c_sdp_S_pn,
g_dsp_data_w => c_sdp_W_crosslet
)
@@ -194,7 +198,7 @@ BEGIN
u_crosslets_stats : ENTITY st_lib.st_xst
GENERIC MAP(
g_nof_streams => g_P_sq,
- g_nof_crosslets => c_sdp_N_crosslets,
+ g_nof_crosslets => c_sdp_N_crosslets_max,
g_nof_signal_inputs => c_sdp_S_pn,
g_in_data_w => c_sdp_W_crosslet,
g_stat_data_w => c_longword_w,
@@ -236,6 +240,32 @@ BEGIN
mux_miso => master_mem_mux_miso
);
+ ---------------------------------------------------------------
+ -- REG_NOF_CROSSLETS
+ ---------------------------------------------------------------
+ u_nof_crosslets : ENTITY common_lib.mms_common_reg
+ GENERIC MAP(
+ g_mm_reg => c_sdp_mm_reg_nof_crosslets
+ )
+ PORT MAP(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- MM bus access in memory-mapped clock domain
+ reg_mosi => reg_nof_crosslets_mosi,
+ reg_miso => reg_nof_crosslets_miso,
+
+ in_reg => nof_crosslets,
+ out_reg => nof_crosslets_reg
+ );
+ -- Force nof crosslets to max nof crosslets if a higher value is written or to 1 if a lower value is written via MM.
+ nof_crosslets <= TO_UVEC(1, c_sdp_nof_crosslets_reg_w) WHEN TO_UINT(nof_crosslets_reg) < 1 ELSE
+ nof_crosslets_reg WHEN TO_UINT(nof_crosslets_reg) <= c_sdp_N_crosslets_max ELSE
+ TO_UVEC(c_sdp_N_crosslets_max, c_sdp_nof_crosslets_reg_w);
+
---------------------------------------------------------------
-- XST UDP offload
---------------------------------------------------------------
@@ -271,6 +301,7 @@ BEGIN
eth_src_mac => stat_eth_src_mac,
udp_src_port => stat_udp_src_port,
ip_src_addr => stat_ip_src_addr,
+ nof_crosslets => nof_crosslets,
crosslets_info => crosslets_info
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
index 9b1a265d65e5a1bd44b9afd0db077a6a355ec5bd..de8c07ed0fbdd9d3704df5e35c01be6d0c81c17b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
@@ -80,7 +80,7 @@ ARCHITECTURE str OF sdp_beamformer_output IS
-- c_fifo_fill must be the exact size of a packet such that no packet gets stuck in the FIFO or the FIFO gets read out too soon.
-- For packets of variable length, dp_fifo_fill_eop must be used. In this case we can use the standard fill fifo.
- CONSTANT c_fifo_fill : NATURAL := c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block / 4; -- Size of packet: 4 beamlets fit in 1 64bit longword
+ CONSTANT c_fifo_fill : NATURAL := c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block / 2; -- Size of packet: 2 beamlets (dual pol) fit in 1 64bit longword
CONSTANT c_fifo_size : NATURAL := c_fifo_fill*2; -- Make fifo size large enough for adding header and muxing beamsets.
SIGNAL snk_in_concat : t_dp_sosi;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 0af185f5fbff6ab24243bfb6a028d45f6ad296ed..eb1ff3b7ffa9399c4eecdf6cac9570efecf6530f 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -41,7 +41,7 @@ USE work.sdp_pkg.ALL;
ENTITY sdp_crosslets_subband_select IS
GENERIC (
- g_N_crosslets : NATURAL := c_sdp_N_crosslets;
+ g_N_crosslets : NATURAL := c_sdp_N_crosslets_max;
g_ctrl_interval_size_min : NATURAL := c_sdp_xst_nof_clk_per_sync_min
);
PORT (
@@ -101,7 +101,8 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS
SIGNAL col_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
SIGNAL row_sosi : t_dp_sosi;
- SIGNAL crosslets_info_reg : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL crosslets_info_reg : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL crosslets_info_reg_in : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL active_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
@@ -147,9 +148,17 @@ BEGIN
reg_mosi => reg_crosslets_info_mosi,
reg_miso => reg_crosslets_info_miso,
- in_reg => crosslets_info_reg,
+ in_reg => crosslets_info_reg_in,
out_reg => crosslets_info_reg
);
+ p_set_unused_crosslets : PROCESS(crosslets_info_reg)
+ BEGIN
+ crosslets_info_reg_in <= crosslets_info_reg; -- Always use crosslets info 6:0 + step(@ index 15)
+ -- Set crosslets 14:7 to -1
+ FOR I IN g_N_crosslets TO c_sdp_mm_reg_crosslets_info.nof_dat - 2 LOOP
+ crosslets_info_reg_in((I+1) * c_sdp_crosslets_index_w - 1 DOWNTO I * c_sdp_crosslets_index_w ) <= TO_SVEC(-1, c_sdp_crosslets_index_w);
+ END LOOP;
+ END PROCESS;
---------------------------------------------------------------
-- Crosslets control process
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index dfdb732de1ba6f91a47525f6e54f6097e10648aa..547b1301ff19305c0f30051aeb7338b251818620 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -69,7 +69,7 @@ PACKAGE sdp_pkg is
-- L3 SDP Decision: SDP Parameter definitions
CONSTANT c_sdp_f_adc_MHz : NATURAL := 200;
CONSTANT c_sdp_N_beamsets : NATURAL := 2;
- CONSTANT c_sdp_N_crosslets : NATURAL := 1;
+ CONSTANT c_sdp_N_crosslets_max : NATURAL := 7;
CONSTANT c_sdp_N_fft : NATURAL := 1024;
CONSTANT c_sdp_N_pn_lb : NATURAL := 16;
CONSTANT c_sdp_N_pol : NATURAL := 2;
@@ -219,7 +219,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_cep_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D0"; -- 15:8, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
CONSTANT c_sdp_cep_nof_blocks_per_packet : NATURAL := 4;
- CONSTANT c_sdp_cep_nof_beamlets_per_block : NATURAL := c_sdp_N_pol_bf * c_sdp_S_sub_bf; -- FIXME in L2SDP-471
+ CONSTANT c_sdp_cep_nof_beamlets_per_block : NATURAL := c_sdp_S_sub_bf; -- number of dual pol beamlets (c_sdp_N_pol_bf = 2)
CONSTANT c_sdp_cep_nof_hdr_fields : NATURAL := 3+12+4+18+1; -- 592b; 9.25 64b words
CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"1100"&"00000010"&"000110"&"0"; -- 0=data path, 1=MM controlled TODO
--CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "100"&"000000010001"&"0100"&"0100"&"00000000"&"101000"&"0"; -- 0=data path, 1=MM controlled TODO
@@ -327,12 +327,20 @@ PACKAGE sdp_pkg is
init_sl => '0');
CONSTANT c_sdp_crosslets_info_reg_w : NATURAL := c_sdp_mm_reg_crosslets_info.nof_dat*c_sdp_mm_reg_crosslets_info.dat_w;
+ CONSTANT c_sdp_mm_reg_nof_crosslets : t_c_mem := (latency => 1,
+ adr_w => 1,
+ dat_w => ceil_log2(c_sdp_N_crosslets_max+1),
+ nof_dat => 1,
+ init_sl => '0'); -- Default = 1
+ CONSTANT c_sdp_nof_crosslets_reg_w : NATURAL := c_sdp_mm_reg_nof_crosslets.nof_dat*c_sdp_mm_reg_nof_crosslets.dat_w;
+
CONSTANT c_sdp_xst_nof_clk_per_sync_min : NATURAL := (c_sdp_f_adc_MHz *10**6) / 10; -- 0.1 second
-- XSUB MM address widths
CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
+ CONSTANT c_sdp_reg_nof_crosslets_addr_w : NATURAL := c_sdp_mm_reg_nof_crosslets.adr_w;
CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4;
- CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
+ CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
END PACKAGE sdp_pkg;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 26714361d8e8392a1f5244f777916a0ee2e5704e..a7ce65a423c59fafc5aa03058c1410b9f40105b2 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -176,7 +176,11 @@ ENTITY sdp_station IS
----------------------------------------------
-- crosslets_info
reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- nof_crosslets
+ reg_nof_crosslets_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_nof_crosslets_miso : OUT t_mem_miso := c_mem_miso_rst;
-- bsn_scheduler_xsub
reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
@@ -520,7 +524,9 @@ BEGIN
mm_clk => mm_clk,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
+ reg_nof_crosslets_miso => reg_nof_crosslets_miso,
reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index e190d901f21e8bb499875a41aeb1e2399061735d..e756819c794fc0da75ecb178147bc40837302179 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -80,6 +80,7 @@ ENTITY sdp_statistics_offload IS
ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
sdp_info : IN t_sdp_info;
subband_calibrated_flag : IN STD_LOGIC := '0';
+ nof_crosslets : IN STD_LOGIC_VECTOR(c_sdp_nof_crosslets_reg_w-1 DOWNTO 0) := (OTHERS => '0');
crosslets_info : IN STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
gn_index : IN NATURAL
@@ -104,7 +105,7 @@ ARCHITECTURE str OF sdp_statistics_offload IS
CONSTANT c_block_size : NATURAL := c_nof_data * c_step_size;
CONSTANT c_nof_packets : NATURAL := sel_a_b(g_statistics_type="BST", 1,
- sel_a_b(g_statistics_type="XST", g_P_sq,
+ sel_a_b(g_statistics_type="XST", g_P_sq * c_sdp_N_crosslets_max,
c_sdp_S_pn)); -- SST
CONSTANT c_marker : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_marker_bst,
@@ -135,9 +136,13 @@ ARCHITECTURE str OF sdp_statistics_offload IS
payload_err : STD_LOGIC;
interval_cnt : NATURAL;
integration_interval : NATURAL;
+ crosslet_count : NATURAL;
+ nof_crosslets : NATURAL;
END RECORD;
- CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0'), 0, '0', 0, 0);
+ CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0'), 0, '0', 0, 0, 0, 0);
+
+ TYPE t_selected_crosslet_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_sdp_crosslets_index_w-1 DOWNTO 0);
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
@@ -153,13 +158,14 @@ ARCHITECTURE str OF sdp_statistics_offload IS
SIGNAL dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0):= (OTHERS => '0');
SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
- SIGNAL selected_crosslet : STD_LOGIC_VECTOR(c_sdp_crosslets_index_w-1 DOWNTO 0);
- --SIGNAL sdp_data_id : STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL selected_crosslet_arr : t_selected_crosslet_arr(c_sdp_N_crosslets_max-1 DOWNTO 0);
BEGIN
bsn_at_sync <= RESIZE_UVEC(in_sosi.bsn, 64) WHEN rising_edge(dp_clk) AND in_sosi.sync = '1';
- selected_crosslet <= crosslets_info(c_sdp_crosslets_index_w-1 DOWNTO 0);
+ gen_sel_crosslets : FOR I IN 0 TO c_sdp_N_crosslets_max-1 GENERATE
+ selected_crosslet_arr(I) <= crosslets_info((I+1)*c_sdp_crosslets_index_w-1 DOWNTO I*c_sdp_crosslets_index_w);
+ END GENERATE;
-------------------------------------------------------------------------------
-- Assemble offload header info
@@ -198,7 +204,7 @@ BEGIN
END IF;
END PROCESS;
- p_control_packet_offload : PROCESS(r, gn_index, in_sosi, trigger, done, dp_header_info, selected_crosslet)
+ p_control_packet_offload : PROCESS(r, gn_index, in_sosi, trigger, done, dp_header_info, selected_crosslet_arr, nof_crosslets)
VARIABLE v: t_reg;
BEGIN
v := r;
@@ -226,7 +232,7 @@ BEGIN
ELSIF g_statistics_type = "BST" THEN
v.data_id := x"0000" & TO_UVEC(c_beamlet_id, 16);
ELSIF g_statistics_type = "XST" THEN
- v.data_id := x"0" & "000" & RESIZE_UVEC(selected_crosslet, 9) & TO_UVEC(r.block_count * c_sdp_S_pn, 8) & TO_UVEC(r.block_count * c_sdp_S_pn, 8); -- RW TODO: define for P_sq > 1
+ v.data_id := x"0" & "000" & RESIZE_UVEC(selected_crosslet_arr(r.crosslet_count), 9) & TO_UVEC(r.block_count * c_sdp_S_pn, 8) & TO_UVEC(r.block_count * c_sdp_S_pn, 8); -- RW TODO: define for P_sq > 1
ELSE
v.data_id := x"00000000";
END IF;
@@ -234,28 +240,41 @@ BEGIN
-- Issue start_pulse per packet offload
IF trigger = '1' THEN
-- Use trigger to start first packet
- v.start_pulse := '1';
- v.start_address := 0;
- v.block_count := 0;
+ v.start_pulse := '1';
+ v.start_address := 0;
+ v.block_count := 0;
+ v.crosslet_count := 0;
+ v.nof_crosslets := TO_UINT(nof_crosslets); -- register nof_crosslets to make sure it does not change during packet output.
ELSIF done = '1' THEN
-- Use done to start next packets
- IF r.block_count < c_nof_packets-1 THEN
- IF r.block_count MOD c_nof_data_per_step = 0 THEN
- v.start_address := r.block_count / c_nof_data_per_step * c_block_size; -- jump to first packet in next block
- ELSE
- v.start_address := r.start_address + c_data_size; -- step to next packet within block
+ IF r.block_count < c_nof_packets-1 THEN
+ IF g_statistics_type /= "XST" OR r.crosslet_count < r.nof_crosslets-1 THEN
+ -- For SST, BST and for XST nof_crosslets do:
+ IF r.block_count MOD c_nof_data_per_step = 0 THEN
+ v.start_address := r.block_count / c_nof_data_per_step * c_block_size; -- jump to first packet in next block
+ ELSE
+ v.start_address := r.start_address + c_data_size; -- step to next packet within block
+ END IF;
+ v.start_pulse := '1';
+ v.block_count := r.block_count + 1;
+ v.crosslet_count := r.crosslet_count + 1;
+ ELSE
+ -- For XST after nof_crosslets do:
+ v.crosslet_count := 0;
+ -- skip block indices for unused XST blocks in this P_sq iteration by setting the block count to the next multiple of N_crosslets_max i.e. 7, 14, 21, etc.
+ v.block_count := r.block_count + 1 + (c_sdp_N_crosslets_max - r.nof_crosslets);
END IF;
- v.start_pulse := '1';
- v.block_count := r.block_count + 1;
+
ELSE
-- Prepare for next trigger interval.
v.start_address := 0;
v.block_count := 0;
+ v.crosslet_count := 0;
END IF;
END IF;
- -- Release header info per packet offload
IF trigger = '1' OR done = '1' THEN
+ -- Release header info per packet offload
v.dp_header_info := dp_header_info;
END IF;
nxt_r <= v;
diff --git a/doc/erko_hdl_design_article.txt b/doc/erko_hdl_design_article.txt
index bd1a76b1206da56a341a15b54e638a32f13c7fd7..f33018fb8cf93b0123681154e039cd08b261fa8f 100644
--- a/doc/erko_hdl_design_article.txt
+++ b/doc/erko_hdl_design_article.txt
@@ -1,3 +1,15 @@
+
+
+Synchronous logic RTL
+Asynchronous logic to cross clock domains, typically from IO to internal logic.
+ . single signal --> FF in series strobes
+ . parallel word --> FF in series for strobes that transfer the data
+ . streaming data --> FIFO using gray encoding for wr and rd address comparision, use one
+ wide FIFO for all data inputs in parallel to preserve their relative
+ timing.
+
+Reset : asynchronous or synchronous ?
+
Digital logic: Ik noem logic zonder klok vaak "combinatorial logic". Deze term is op zich correct, maar de meer gangbare term is "combinational logic", zie
https://en.wikipedia.org/wiki/Combinational_logic . Ik zal dat aanpassen in de documentatie. De logic met klok wordt "sequential logic" genoemd. Tesamen heet het "digital logic".
@@ -36,7 +48,7 @@ Idea / rule: Distinguish beteen state registers and pipeline registers.
. Components that do need input flow control can OR their input flow control with the external flow control
and wire that to the input_siso.
-
+
$RADIOHDL_WORK/applications/lofar2/doc/prestudy/
@@ -72,6 +84,8 @@ Ik zie twee niveaus:
dat de packets die binnenkomen van buiten de FPGA correct zijn (bijv. mbv CRC ok) dan is de
block processing foutloos (dwz what you want is what you get). Dan kunnen we er intern steeds
van uitgaan dat de blokken data correct zijn en hoeven we dus intern geen checks meer te doen.
+ De processing moet wel bestand zijn tegen missende blocken, bijv. tgv data loss aan een input
+ of uit en aan zetten van een input.
Design steps:
@@ -97,6 +111,11 @@ Implementation steps:
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
+ . -- Memoryless signals in p_comb (wires used as local auxiliary variables)
+ SIGNAL s : t_comb;
+
+ . -- Structural signals (wires used to connect components and IO)
+
. -- Pipeline registers
SIGNAL in_data_p : ...
@@ -131,11 +150,24 @@ Implementation steps:
-- next state
nxt_r <= v;
+
+ -- memory less signals, only for view in wave window
+ s <= d;
END PROCESS;
. -- Pipelining
- TB: Test the functionality of the DUT:
+ . Every component should have a tb (= unit test)
+ . The tb should be self checking and self stopping, so that it can be part of a
+ regression test.
+ . Only test the added functionality of the DUT, do not test lower level component
+ instances, because these have been tested already in detail at their level. E.g
+ for an MMP interface component, only check that the MM access is wired correctly.
+ . if possible also create the dual component, e.g. tx --> rx, encoder --> decoder
+ multiplexer --> demultiplexer (see dp, diag examples). This makes tb verification
+ easier, because expected results are in the same format as the stimuli and
+ because it yields the dual component, which can be useful for future applications.
. start with easiest, default use case,
. then verify the additional functions and features,
. then verify the corner cases (e.g. 0, 1, some prime value, smallest, largest),
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index a90a6b409d457c725474ec61abceb497fccc868e..316fad525c67fd545216814cd22c85645d28b169 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -266,6 +266,8 @@ git remote remove <remote name> # remove a remote repo
* GIT workflow and review process using Gitlab
*******************************************************************************
+https://ohshitgit.com/
+
We identify two persons in this process:
- the coder
- the reviewer
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
index a663665879e5e6e7d3ec68c1938e2e46b7100a95..e6f4c5cb082864f6fdc9ed78d009f9ec9e18fbf1 100644
--- a/libraries/dsp/st/st.peripheral.yaml
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -139,7 +139,7 @@ peripherals:
# Parameters of pi_st_xst.py, fixed in node_sdp_correlator.vhd / sdp_pkg.vhd
- { name: g_nof_streams, value: 9 } # P_sq
# Parameters of st_xst.vhd, st_xsq_arr.vhd fixed in node_sdp_correlator.vhd / sdp_pkg.vhd
- - { name: g_nof_crosslets, value: 1 } # N_crosslets
+ - { name: g_nof_crosslets, value: 7 } # N_crosslets_max
- { name: g_nof_signal_inputs, value: 12 } # S_pn = 12
- { name: g_in_data_w, value: 16 } # W_crosslet = 16
- { name: g_stat_data_w, value: 64 } # W_statistic = 64