diff --git a/libraries/base/diag/hdllib.cfg b/libraries/base/diag/hdllib.cfg
index e1dd075816a3c6d3c67197fcd4be47e3821e62a4..93badcf5f368184778121aa425c9120581b6537d 100644
--- a/libraries/base/diag/hdllib.cfg
+++ b/libraries/base/diag/hdllib.cfg
@@ -12,7 +12,7 @@ synth_files =
src/vhdl/diag_pkg.vhd
$UNB/Firmware/modules/Lofar/diag/src/vhdl/diag_bypass.vhd
src/vhdl/diag_tx_seq.vhd
- $UNB/Firmware/modules/Lofar/diag/src/vhdl/diag_tx_frm.vhd
+ src/vhdl/diag_tx_frm.vhd
src/vhdl/diag_rx_seq.vhd
src/vhdl/diag_frm_generator.vhd
$UNB/Firmware/modules/Lofar/diag/src/vhdl/diag_frm_monitor.vhd
diff --git a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
index e334b8f244d13e69753b84ce0f5f252ae8d7c582..5f1ce364949ec0f7cf61477d124f00da929d69b2 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
@@ -29,7 +29,7 @@ USE common_lib.common_pkg.ALL;
-- Purpose: Generate a stream of frames with test sequence data.
-- Description:
-- Each frame has g_frame_len words of out_dat. The test data can be PRSG or
--- COUNTER dependent on diag_sel.
+-- COUNTER dependent on diag_sel, or constant data when diag_dc='1'.
-- The frame generator is enabled by diag_en. The actual frame rate depends
-- on the g_sop_period and on out_ready.
-- The out_ready acts as a data request. During a frame the out_dat is valid
@@ -56,7 +56,8 @@ ENTITY diag_frm_generator IS
-- Static control input (connect via MM or leave open to use default)
diag_en : IN STD_LOGIC;
- diag_sel : IN STD_LOGIC := g_sel;
+ diag_sel : IN STD_LOGIC := g_sel; -- '0' = PRSG sequence data, '1' = COUNTER sequence data
+ diag_dc : IN STD_LOGIC := '0'; -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
diag_frame_len : IN STD_LOGIC_VECTOR(ceil_log2(g_frame_len)-1 DOWNTO 0) := TO_UVEC(g_frame_len, ceil_log2(g_frame_len));
diag_frame_empty : IN STD_LOGIC_VECTOR(ceil_log2(g_dat_w/g_symbol_w)-1 DOWNTO 0) := TO_UVEC(g_empty, ceil_log2(g_dat_w/g_symbol_w));
diag_sof_period : IN STD_LOGIC_VECTOR(ceil_log2(g_sof_period)-1 DOWNTO 0) := TO_UVEC(g_sof_period, ceil_log2(g_sof_period));
@@ -79,8 +80,8 @@ ARCHITECTURE str OF diag_frm_generator IS
CONSTANT c_frame_len_w : NATURAL := ceil_log2(g_frame_len);
SIGNAL diag_en_revt : STD_LOGIC;
- SIGNAL diag_dat : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(c_init, g_dat_w); -- init data for out_dat when diag_sop = '1'
- SIGNAL nxt_diag_dat : STD_LOGIC_VECTOR(diag_dat'RANGE);
+ SIGNAL diag_init : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(c_init, g_dat_w); -- init data for out_dat when diag_sop = '1'
+ SIGNAL nxt_diag_init : STD_LOGIC_VECTOR(diag_init'RANGE);
SIGNAL diag_sop : STD_LOGIC;
SIGNAL diag_ready : STD_LOGIC;
@@ -113,17 +114,17 @@ BEGIN
p_clk : PROCESS (rst, clk)
BEGIN
IF rst='1' THEN
- diag_dat <= TO_UVEC(c_init, g_dat_w);
+ diag_init <= TO_UVEC(c_init, g_dat_w);
diag_frame_cnt <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN
IF clken='1' THEN
- diag_dat <= nxt_diag_dat;
+ diag_init <= nxt_diag_init;
diag_frame_cnt <= nxt_diag_frame_cnt;
END IF;
END IF;
END PROCESS;
- nxt_diag_dat <= TO_UVEC(c_init, g_dat_w) WHEN diag_en='0' ELSE INCR_UVEC(diag_dat, 1) WHEN i_out_sop='1';
+ nxt_diag_init <= TO_UVEC(c_init, g_dat_w) WHEN diag_en='0' ELSE INCR_UVEC(diag_init, 1) WHEN i_out_sop='1';
u_pulse_sop : ENTITY common_lib.common_pulser
GENERIC MAP (
@@ -169,11 +170,12 @@ BEGIN
-- Static control input (connect via MM or leave open to use default)
diag_sel => diag_sel,
+ diag_dc => diag_dc,
diag_frame_len => diag_frame_len,
-- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
diag_ready => diag_ready,
- diag_dat => diag_dat,
+ diag_init => diag_init,
diag_sop => diag_sop,
-- ST output
diff --git a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
index f5cc14a13f5868e597327bff50c59c81afa882ed..2894ee1c8e564b53ffc609a04cddd2f5012e2ba6 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
@@ -57,12 +57,13 @@ ENTITY diag_tx_frm IS
clken : IN STD_LOGIC := '1';
-- Static control input (connect via MM or leave open to use default)
- diag_sel : IN STD_LOGIC := g_sel;
+ diag_sel : IN STD_LOGIC := g_sel; -- '0' = PRSG sequence data, '1' = COUNTER sequence data
+ diag_dc : IN STD_LOGIC := '0'; -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
diag_frame_len : IN STD_LOGIC_VECTOR(ceil_log2(g_frame_len)-1 DOWNTO 0) := TO_UVEC(g_frame_len, ceil_log2(g_frame_len));
-- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
diag_ready : OUT STD_LOGIC; -- '1' when the generator can accept a new diag_sop
- diag_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(g_init, g_dat_w); -- init data for out_dat when diag_sop = '1'
+ diag_init : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(g_init, g_dat_w); -- init data for out_dat when diag_sop = '1'
diag_sop : IN STD_LOGIC := '1'; -- '1' start a frame generation
-- ST output
@@ -163,7 +164,8 @@ BEGIN
clken => clken,
diag_en => diag_en,
diag_sel => diag_sel,
- diag_dat => diag_dat,
+ diag_dc => diag_dc,
+ diag_init => diag_init,
diag_req => out_ready,
out_dat => out_dat,
out_val => OPEN
diff --git a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
index 0a6efa2856dd6a49119ea65f3257a9ab43b3347d..93f041bd5d6517f2dd481ee610257b874579a8d8 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
@@ -28,9 +28,11 @@ USE common_lib.common_lfsr_sequences_pkg.ALL;
-- Purpose: Transmit continuous PRSG or COUNTER test sequence data.
-- Description:
--- The Tx test data can be PRSG or COUNTER dependent on diag_sel.
+-- The Tx test data can sequence data or constant value data dependent on
+-- diag_dc.
+-- The Tx test sequence data can be PRSG or COUNTER dependent on diag_sel.
-- The Tx is enabled by diag_en. When the Tx is disabled then the sequence
--- gets initialised with diag_dat.
+-- data gets initialised with diag_init.
-- The out_ready acts as a data request. When the generator is enabled then
-- output is valid for every active out_ready, to support streaming flow
-- control. With g_latency=1 the out_val is active one cycle after diag_req,
@@ -49,9 +51,10 @@ ENTITY diag_tx_seq IS
clk : IN STD_LOGIC;
clken : IN STD_LOGIC := '1';
-- Static control input (connect via MM or leave open to use default)
- diag_en : IN STD_LOGIC; -- '0' = init and disable output sequence, '1' = enable output sequence
- diag_sel : IN STD_LOGIC := g_sel;
- diag_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(g_init, g_dat_w); -- init value for out_dat when diag_en = '0'
+ diag_en : IN STD_LOGIC; -- '0' = init and disable output sequence, '1' = enable output sequence
+ diag_sel : IN STD_LOGIC := g_sel; -- '0' = PRSG sequence data, '1' = COUNTER sequence data
+ diag_dc : IN STD_LOGIC := '0'; -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
+ diag_init : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(g_init, g_dat_w); -- init value for out_dat when diag_en = '0'
-- ST output
diag_req : IN STD_LOGIC := '1'; -- '1' = request output, '0' = halt output
out_cnt : OUT STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0); -- count valid output test sequence data
@@ -115,13 +118,13 @@ BEGIN
common_lfsr_nxt_seq(c_lfsr_nr, -- IN
diag_en, -- IN
diag_req, -- IN
- diag_dat, -- IN
+ diag_init, -- IN
prsg, -- IN
cntr, -- IN
nxt_prsg, -- OUT
nxt_cntr); -- OUT
- nxt_out_dat <= prsg WHEN diag_sel='0' ELSE cntr;
+ nxt_out_dat <= diag_init WHEN diag_dc='1' ELSE prsg WHEN diag_sel='0' ELSE cntr;
nxt_out_val <= diag_en AND diag_req; -- 'en' for entire test on/off, 'req' for dynamic invalid gaps in the stream
-- Count number of valid output data
diff --git a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
index 16c6b86b0cb3b4f7971d936fe16f15fa2c3ef6b7..e9d282bd9116ce6a33bc6594c3aab4fb5bb3a8b5 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
@@ -29,9 +29,9 @@
--
-- 31 24 23 16 15 8 7 0 wi
-- |-----------------|-----------------|-----------------|-----------------|
--- | select = [1], enable = [0] | 0
+-- | diag_dc = [2], diag_sel = [1], diag_en = [0] | 0
-- |-----------------------------------------------------------------------|
--- | init[31:0] | 1
+-- | diag_init[31:0] | 1
-- |-----------------------------------------------------------------------|
-- | tx_cnt[31:0] | 2
-- |-----------------------------------------------------------------------|
@@ -56,9 +56,17 @@
-- smaller g_seq_dat_w can be used to provide CNTR or LFSR data for the DP
-- data.
--
+-- . diag_en
+-- '0' = init and disable output sequence
+-- '1' = enable output sequence
+--
-- . diag_sel
--- 0 = PSRG data
--- 1 = CNTR data
+-- '0' = PSRG data
+-- '1' = CNTR data
+--
+-- . diag_dc
+-- '0' = Output sequence data (as selected by diag_sel)
+-- '1' = Output constant data (value as set by diag_init)
--
-- . diag_init
-- Note that MM diag_init has c_word_w=32 bits, so if g_seq_dat_w is wider
@@ -129,6 +137,7 @@ ARCHITECTURE str OF mms_diag_tx_seq IS
SIGNAL diag_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_sel_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL diag_dc_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_init_mm_arr : t_slv_32_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0')); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
SIGNAL diag_init_arr : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
@@ -152,19 +161,20 @@ BEGIN
g_dat_w => g_seq_dat_w
)
PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
+ rst => dp_rst,
+ clk => dp_clk,
-- Write and read back registers:
- diag_en => diag_en_arr(I),
- diag_sel => diag_sel_arr(I),
- diag_dat => diag_init_arr(I),
+ diag_en => diag_en_arr(I),
+ diag_sel => diag_sel_arr(I),
+ diag_dc => diag_dc_arr(I),
+ diag_init => diag_init_arr(I),
-- Streaming
- diag_req => tx_req_arr(I),
- out_cnt => tx_cnt_arr(I),
- out_dat => tx_dat_arr(I),
- out_val => tx_val_arr(I)
+ diag_req => tx_req_arr(I),
+ out_cnt => tx_cnt_arr(I),
+ out_dat => tx_dat_arr(I),
+ out_val => tx_val_arr(I)
);
tx_req_arr(I) <= tx_src_in_arr(I).ready;
@@ -178,6 +188,7 @@ BEGIN
-- Register mapping
diag_en_arr(I) <= ctrl_reg_arr(I)( 0); -- address 0, data bit [0]
diag_sel_arr(I) <= ctrl_reg_arr(I)( 1); -- address 0, data bit [1]
+ diag_dc_arr(I) <= ctrl_reg_arr(I)( 2); -- address 0, data bit [2]
diag_init_mm_arr(I) <= ctrl_reg_arr(I)(2*c_word_w-1 DOWNTO c_word_w); -- address 1, data bits [31:0]
diag_init_arr(I) <= RESIZE_UVEC(diag_init_mm_arr(I), g_seq_dat_w);
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
index 9af57b3ee0549937bb388cf4cc1e269ad99c9670..be0e95dffc8ea7d7f6cfce1eafebb6e1dc122fd5 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
@@ -44,7 +44,7 @@ ARCHITECTURE tb OF tb_diag_tx_frm IS
SIGNAL diag_sel : STD_LOGIC;
SIGNAL diag_frame_len : STD_LOGIC_VECTOR(c_frame_len_w-1 DOWNTO 0) := TO_UVEC(c_frame_len, c_frame_len_w);
- SIGNAL diag_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+ SIGNAL diag_init : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
SIGNAL diag_ready : STD_LOGIC;
SIGNAL diag_sop : STD_LOGIC;
@@ -64,7 +64,7 @@ BEGIN
-- run 100 us
BEGIN
diag_sel <= c_sel;
- diag_dat <= TO_UVEC(c_init, c_dat_w);
+ diag_init <= TO_UVEC(c_init, c_dat_w);
diag_sop <= '0';
seq_req <= '1';
WAIT FOR 10*c_period;
@@ -72,7 +72,7 @@ BEGIN
-- Keep seq_req='1'
seq_req <= '1';
WAIT FOR c_period;
- diag_sop <= '1'; -- Generate one frame
+ diag_sop <= '1'; -- Generate one frame
WAIT FOR c_period;
diag_sop <= '0';
WAIT FOR c_nof_cycles*c_period;
@@ -80,16 +80,16 @@ BEGIN
-- Keep seq_req='1'
seq_req <= '1';
- diag_dat <= TO_UVEC(0, c_dat_w);
+ diag_init <= TO_UVEC(0, c_dat_w);
WAIT FOR 10*c_period;
diag_sop <= '1'; -- Generate one frame with actual c_init only during diag_sop
- diag_dat <= TO_UVEC(c_init, c_dat_w);
+ diag_init <= TO_UVEC(c_init, c_dat_w);
WAIT FOR c_period;
diag_sop <= '0';
- diag_dat <= TO_UVEC(0, c_dat_w);
+ diag_init <= TO_UVEC(0, c_dat_w);
WAIT FOR c_nof_cycles*c_period;
WAIT FOR 10*c_period;
- diag_dat <= TO_UVEC(c_init, c_dat_w);
+ diag_init <= TO_UVEC(c_init, c_dat_w);
-- Keep diag_sop='1' to immediately request a next frame again
seq_req <= '1';
@@ -171,7 +171,7 @@ BEGIN
diag_frame_len => diag_frame_len,
-- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
diag_ready => diag_ready,
- diag_dat => diag_dat,
+ diag_init => diag_init,
diag_sop => diag_sop,
-- ST output
out_ready => seq_req,