From 66e6b57286ef19094ab66b9549486e847550ee67 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 22 Feb 2024 11:01:54 +0100
Subject: [PATCH] Remove obsolete g_no_rx. Improve comments at AIT instances.
---
.../sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd | 6 ++----
.../libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd | 1 -
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index ba5ace7994..edb98df159 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -286,7 +286,6 @@ begin
gen_rx_ait : if g_no_jesd = false and g_use_tech_jesd204b_v2 = false generate
u_rx_ait : entity work.sdp_adc_input_and_timing
generic map (
- g_no_rx => g_no_jesd, -- when false use Rx and WG, else only use WG
g_no_st_histogram => g_no_st_histogram,
g_buf_nof_data => g_buf_nof_data,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync, -- Default 200M, overide for short simulation
@@ -401,11 +400,10 @@ begin
);
end generate; -- gen_rx_ait
- -- Wire dp_clk to AIT when jesd is not used or when jesd IP tech_jesd204b_v2 is used
- gen_dp_ait : if g_no_jesd = true or (g_no_jesd = false and g_use_tech_jesd204b_v2 = true) generate
+ -- Wire dp_clk to AIT when jesd IP tech_jesd204b_v2 is used, or when only the WG is used (so no jesd)
+ gen_dp_ait : if (g_no_jesd = false and g_use_tech_jesd204b_v2 = true) or g_no_jesd = true generate
u_dp_ait : entity work.sdp_adc_input_and_timing
generic map (
- g_no_rx => g_no_jesd, -- when false use Rx and WG, else only use WG
g_no_st_histogram => g_no_st_histogram,
g_buf_nof_data => g_buf_nof_data,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync, -- Default 200M, overide for short simulation
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
index 6664891230..8a53a0d6a0 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
@@ -36,7 +36,6 @@ use work.sdp_pkg.all;
entity sdp_adc_input_and_timing is
generic (
- g_no_rx : boolean := false; -- when false use Rx and WG, else use only WG
g_no_st_histogram : boolean := true; -- when false use input histogram, else not to save block RAM
g_buf_nof_data : natural := c_sdp_V_si_db;
g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
--
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