diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index ba5ace7994c52065b2c62316717a2e6230e93370..edb98df15980958c38a4fc3d011ce1bee1d98a67 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -286,7 +286,6 @@ begin
   gen_rx_ait : if g_no_jesd = false and g_use_tech_jesd204b_v2 = false generate
     u_rx_ait : entity work.sdp_adc_input_and_timing
     generic map (
-      g_no_rx                   => g_no_jesd,  -- when false use Rx and WG, else only use WG
       g_no_st_histogram         => g_no_st_histogram,
       g_buf_nof_data            => g_buf_nof_data,
       g_bsn_nof_clk_per_sync    => g_bsn_nof_clk_per_sync,  -- Default 200M, overide for short simulation
@@ -401,11 +400,10 @@ begin
     );
   end generate;  -- gen_rx_ait
 
-  -- Wire dp_clk to AIT when jesd is not used or when jesd IP tech_jesd204b_v2 is used
-  gen_dp_ait : if g_no_jesd = true or (g_no_jesd = false and g_use_tech_jesd204b_v2 = true) generate
+  -- Wire dp_clk to AIT when jesd IP tech_jesd204b_v2 is used, or when only the WG is used (so no jesd)
+  gen_dp_ait : if (g_no_jesd = false and g_use_tech_jesd204b_v2 = true) or g_no_jesd = true generate
     u_dp_ait : entity work.sdp_adc_input_and_timing
     generic map (
-      g_no_rx                   => g_no_jesd,  -- when false use Rx and WG, else only use WG
       g_no_st_histogram         => g_no_st_histogram,
       g_buf_nof_data            => g_buf_nof_data,
       g_bsn_nof_clk_per_sync    => g_bsn_nof_clk_per_sync,  -- Default 200M, overide for short simulation
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
index 6664891230ae8ae486ce8847f513145cae58ed14..8a53a0d6a035b87573d2570ea14250748e2af77a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
@@ -36,7 +36,6 @@ use work.sdp_pkg.all;
 
 entity sdp_adc_input_and_timing is
   generic (
-    g_no_rx                   : boolean := false;  -- when false use Rx and WG, else use only WG
     g_no_st_histogram         : boolean := true;  -- when false use input histogram, else not to save block RAM
     g_buf_nof_data            : natural := c_sdp_V_si_db;
     g_bsn_nof_clk_per_sync    : natural := c_sdp_N_clk_per_sync;  -- Default 200M, overide for short simulation