diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
index 5a9b316df33bfba16e79999a4823e6d3f46f74f9..a765109f22564f6c5b8db4f5333585a9c79fd632 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
@@ -21,9 +21,9 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_phy_10gbase_r_lib;
-LIBRARY ip_arria10_transceiver_pll_10g_lib;
-LIBRARY ip_arria10_transceiver_reset_controller_1_lib;
+LIBRARY ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140;
+LIBRARY ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140;
+LIBRARY ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140;
 
 LIBRARY IEEE, tech_pll_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;