diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
index 424f5df52bb65098e156e725c0388a85efc82acb..1c5bb853caf166cf6b5536e9b5b9ab0bf05b8f23 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -24,6 +24,7 @@ LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
+USE work.diag_pkg.ALL;
-- Purpose: test bench for diag_rx_seq control
-- Usage:
@@ -34,17 +35,24 @@ USE common_lib.common_pkg.ALL;
--- stimuli process, these mismatches are reported
ENTITY tb_diag_rx_seq IS
+ GENERIC (
+ g_use_steps : BOOLEAN := TRUE;
+ g_steps_arr : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0) := (OTHERS=>1);
+ g_seq_dat_w : NATURAL := 16 -- = 12b for Lofar RCU test data, 16b for Lofar TBBI test data
+ );
END tb_diag_rx_seq;
ARCHITECTURE tb OF tb_diag_rx_seq IS
CONSTANT c_period : TIME := 100 ns;
CONSTANT c_nof_cycles : NATURAL := 100;
+ CONSTANT c_latency : NATURAL := 2;
- CONSTANT c_dat_w : NATURAL := 12; -- = 12, for RCU test data
- --CONSTANT c_dat_w : NATURAL := 16; -- = 16, for TBBI test data
+ CONSTANT c_nof_steps : NATURAL := c_diag_seq_rx_reg_nof_steps;
+ CONSTANT c_diag_res_w : NATURAL := g_seq_dat_w + 1;
- CONSTANT c_diag_res_w : NATURAL := c_dat_w + 1;
+ CONSTANT c_diag_res_ok : STD_LOGIC_VECTOR(c_diag_res_w-1 DOWNTO 0) := '0' & TO_UVEC( 0, c_diag_res_w-1);
+ CONSTANT c_diag_res_wrong : STD_LOGIC_VECTOR(c_diag_res_w-1 DOWNTO 0) := '0' & TO_UVEC(2**g_seq_dat_w-1, c_diag_res_w-1);
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
@@ -54,14 +62,17 @@ ARCHITECTURE tb OF tb_diag_rx_seq IS
SIGNAL tx_diag_en : STD_LOGIC;
SIGNAL tx_diag_sel : STD_LOGIC;
SIGNAL tx_diag_req : STD_LOGIC;
- SIGNAL seq_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+ SIGNAL seq_dat : STD_LOGIC_VECTOR(g_seq_dat_w-1 DOWNTO 0);
SIGNAL seq_val : STD_LOGIC;
-- Rx test data
- SIGNAL rx_diag_en : STD_LOGIC;
- SIGNAL rx_diag_sel : STD_LOGIC;
- SIGNAL diag_res : STD_LOGIC_VECTOR(c_diag_res_w-1 DOWNTO 0);
- SIGNAL diag_res_val : STD_LOGIC;
+ SIGNAL rx_diag_en : STD_LOGIC;
+ SIGNAL rx_diag_sel : STD_LOGIC;
+ SIGNAL rx_diag_steps_arr : t_integer_arr(c_nof_steps-1 DOWNTO 0) := g_steps_arr;
+ SIGNAL diag_res : STD_LOGIC_VECTOR(c_diag_res_w-1 DOWNTO 0);
+ SIGNAL diag_res_val : STD_LOGIC;
+
+ SIGNAL expected_res : STD_LOGIC_VECTOR(c_diag_res_w-1 DOWNTO 0);
BEGIN
@@ -78,6 +89,7 @@ BEGIN
tx_diag_req <= '1';
-- COUNTER
+ expected_res <= sel_a_b(g_use_steps, c_diag_res_ok, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '1';
rx_diag_sel <= '1';
@@ -107,8 +119,10 @@ BEGIN
tx_diag_req <= '1';
WAIT FOR c_nof_cycles*c_period;
rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR c_latency*c_period;
-- PRSG
+ expected_res <= sel_a_b(g_use_steps, c_diag_res_wrong, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '0';
rx_diag_sel <= '0';
@@ -118,8 +132,11 @@ BEGIN
rx_diag_en <= '1'; -- restart diag_res
WAIT FOR c_nof_cycles*c_period;
rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR c_latency*c_period;
-- COUNTER
+ WAIT FOR c_latency*c_period;
+ expected_res <= sel_a_b(g_use_steps, c_diag_res_ok, c_diag_res_ok);
tx_diag_en <= '0'; -- stop tx
WAIT FOR c_period;
tx_diag_sel <= '1';
@@ -134,8 +151,10 @@ BEGIN
tx_diag_req <= '1';
WAIT FOR c_nof_cycles*c_period;
rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR c_latency*c_period;
-- COUNTER
+ expected_res <= sel_a_b(g_use_steps, c_diag_res_ok, c_diag_res_ok);
tx_diag_en <= '0'; -- stop tx
tx_diag_req <= '0'; -- inactive tx request
WAIT FOR c_period;
@@ -163,8 +182,10 @@ BEGIN
WAIT FOR c_period;
WAIT FOR c_nof_cycles*c_period;
rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR c_latency*c_period;
-- PRSG
+ expected_res <= sel_a_b(g_use_steps, c_diag_res_wrong, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '0';
rx_diag_sel <= '0';
@@ -177,8 +198,10 @@ BEGIN
tx_diag_en <= '0'; -- stop tx
WAIT FOR c_nof_cycles*c_period;
rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR c_latency*c_period;
-- PRSG
+ expected_res <= sel_a_b(g_use_steps, c_diag_res_wrong, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '0';
rx_diag_sel <= '0';
@@ -201,8 +224,10 @@ BEGIN
tx_diag_en <= '0'; -- stop tx
WAIT FOR c_nof_cycles*c_period;
rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR c_latency*c_period;
-- COUNTER
+ expected_res <= sel_a_b(g_use_steps, c_diag_res_ok, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '1';
rx_diag_sel <= '1';
@@ -217,6 +242,7 @@ BEGIN
WAIT FOR c_nof_cycles*c_period; -- some more cylces to show that the diag_res error state is preserved
tx_diag_en <= '0'; -- stop tx
rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR c_latency*c_period;
WAIT FOR c_nof_cycles*c_period;
tb_end <= '1';
@@ -226,7 +252,7 @@ BEGIN
u_diag_tx_seq : ENTITY work.diag_tx_seq
GENERIC MAP (
- g_dat_w => c_dat_w
+ g_dat_w => g_seq_dat_w
)
PORT MAP (
clk => clk,
@@ -240,25 +266,28 @@ BEGIN
u_diag_rx_seq : ENTITY work.diag_rx_seq
GENERIC MAP (
- g_dat_w => c_dat_w,
+ g_use_steps => g_use_steps,
+ g_nof_steps => c_nof_steps,
+ g_dat_w => g_seq_dat_w,
g_diag_res_w => c_diag_res_w
)
PORT MAP (
- clk => clk,
- rst => rst,
- in_dat => seq_dat,
- in_val => seq_val,
- diag_en => rx_diag_en,
- diag_sel => rx_diag_sel,
- diag_res => diag_res,
- diag_res_val => diag_res_val
+ clk => clk,
+ rst => rst,
+ in_dat => seq_dat,
+ in_val => seq_val,
+ diag_en => rx_diag_en,
+ diag_sel => rx_diag_sel,
+ diag_steps_arr => rx_diag_steps_arr,
+ diag_res => diag_res,
+ diag_res_val => diag_res_val
);
p_report : PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF diag_res_val='1' THEN
- ASSERT UNSIGNED(diag_res)=0 REPORT "DIAG sequence mismatch occured.";
+ ASSERT UNSIGNED(diag_res)=UNSIGNED(expected_res) REPORT "DIAG sequence mismatch occured.";
END IF;
END IF;
END PROCESS;