diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..ce382f19c6df077e1d097aeef00ce28e7e7fed30
--- /dev/null
+++ b/libraries/base/common/hdllib.cfg
@@ -0,0 +1,235 @@
+hdl_lib_name = common
+hdl_library_clause_name = common_lib
+hdl_lib_uses = tst
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    ../MegaWizard/fifo_sc/fifo_sc.vhd
+    ../MegaWizard/fifo_dc/fifo_dc.vhd
+    ../MegaWizard/fifo_dc/fifo_dc_mixed_widths.vhd
+    ../MegaWizard/mem/rom_r.vhd
+    ../MegaWizard/mem/ram_r_w.vhd
+    ../MegaWizard/mem/ram_crw_crw.vhd
+    ../MegaWizard/mem/ram_crwk_crw.vhd
+    ../MegaWizard/mem/ram_cr_cw.vhd
+    ../MegaWizard/arith/lut_add_sub.vhd
+    ../MegaWizard/arith/dsp_add_sub.vhd
+    ../MegaWizard/arith/dsp_mult_add2.vhd
+    ../MegaWizard/arith/dsp_mult_add4.vhd
+    ../MegaWizard/arith/dsp_complex_mult.vhd
+    
+    src/ip/MegaWizard/iobuf_in.vhd
+    
+    src/vhdl/common_pkg.vhd
+    src/vhdl/common_str_pkg.vhd
+    src/vhdl/common_mem_pkg.vhd
+    src/vhdl/common_field_pkg.vhd
+    src/vhdl/common_lfsr_sequences_pkg.vhd
+    src/vhdl/common_components_pkg.vhd
+    
+    src/vhdl/common_wideband_data_scope.vhd
+    src/vhdl/common_iobuf_in.vhd
+    src/vhdl/common_iobuf_in_a_stratix4.vhd
+    src/vhdl/common_ddio_in.vhd
+    src/vhdl/common_ddio_in_a_stratix4.vhd
+    src/vhdl/common_ddio_out.vhd
+    src/vhdl/common_ddio_out_a_stratix4.vhd
+    src/vhdl/common_inout.vhd
+    src/vhdl/common_async.vhd
+    src/vhdl/common_async_slv.vhd
+    src/vhdl/common_areset.vhd
+    src/vhdl/common_acapture.vhd
+    src/vhdl/common_acapture_slv.vhd
+    src/vhdl/common_pipeline.vhd
+    src/vhdl/common_pipeline_sl.vhd
+    src/vhdl/common_pipeline_integer.vhd
+    src/vhdl/common_pipeline_natural.vhd
+    src/vhdl/common_fanout.vhd
+    src/vhdl/common_fanout_tree.vhd
+    src/vhdl/common_ddreg.vhd
+    src/vhdl/common_ddreg_slv.vhd
+    src/vhdl/common_evt.vhd
+    src/vhdl/common_flank_to_pulse.vhd
+    src/vhdl/common_toggle.vhd
+    src/vhdl/common_switch.vhd
+    src/vhdl/common_request.vhd
+    src/vhdl/common_pulse_extend.vhd
+    src/vhdl/common_spulse.vhd
+    src/vhdl/common_counter.vhd
+    src/vhdl/common_init.vhd
+    src/vhdl/common_pulser.vhd
+    src/vhdl/common_debounce.vhd
+    src/vhdl/common_frame_busy.vhd
+    src/vhdl/common_stable_delayed.vhd
+    src/vhdl/common_stable_monitor.vhd
+    src/vhdl/common_interval_monitor.vhd
+    src/vhdl/common_clock_active_detector.vhd
+    src/vhdl/common_clock_phase_detector.vhd
+    src/vhdl/common_resize.vhd
+    src/vhdl/common_round.vhd
+    src/vhdl/common_requantize.vhd
+    src/vhdl/common_clip.vhd
+    src/vhdl/common_pipeline_symbol.vhd
+    src/vhdl/common_shiftreg.vhd
+    src/vhdl/common_shiftreg_symbol.vhd
+    src/vhdl/common_add_symbol.vhd
+    src/vhdl/common_select_symbol.vhd
+    src/vhdl/common_select_m_symbols.vhd
+    src/vhdl/common_reorder_symbol.vhd
+    src/vhdl/common_multiplexer.vhd
+    src/vhdl/common_demultiplexer.vhd
+    src/vhdl/common_transpose_symbol.vhd
+    src/vhdl/common_transpose.vhd
+    src/vhdl/common_complex_round.vhd
+    src/vhdl/common_add_sub.vhd
+    src/vhdl/common_add_sub_a_stratix4.vhd
+    src/vhdl/common_add_sub_a_rtl.vhd
+    src/vhdl/common_complex_add_sub.vhd
+    src/vhdl/common_accumulate.vhd
+    src/vhdl/common_int2float.vhd
+    src/vhdl/common_adder_staged.vhd
+    src/vhdl/common_adder_tree.vhd
+    src/vhdl/common_adder_tree_a_recursive.vhd
+    src/vhdl/common_adder_tree_a_str.vhd
+    src/vhdl/common_operation.vhd
+    src/vhdl/common_operation_tree.vhd
+    src/vhdl/common_mult.vhd
+    src/vhdl/common_mult_a_stratix4.vhd
+    src/vhdl/common_mult_a_rtl.vhd
+    src/vhdl/common_mult_add2.vhd
+    src/vhdl/common_mult_add2_a_stratix4.vhd
+    src/vhdl/common_mult_add2_a_rtl_stratix4.vhd
+    src/vhdl/common_mult_add2_a_rtl.vhd
+    src/vhdl/common_mult_add4.vhd
+    src/vhdl/common_mult_add4_a_stratix4.vhd
+    src/vhdl/common_mult_add4_a_rtl.vhd
+    src/vhdl/common_complex_mult.vhd
+    src/vhdl/common_complex_mult_a_stratix4.vhd
+    src/vhdl/common_complex_mult_a_str_stratix4.vhd
+    src/vhdl/common_complex_mult_add.vhd
+    src/vhdl/common_complex_mult_add_parallel.vhd
+    src/vhdl/common_complex_mult_add_pipeline.vhd
+    src/vhdl/common_rl_decrease.vhd
+    src/vhdl/common_rl_increase.vhd
+    src/vhdl/common_rl_register.vhd
+    src/vhdl/common_fifo_rd.vhd
+    src/vhdl/common_fifo_sc.vhd
+    src/vhdl/common_fifo_sc_a_stratix4.vhd
+    src/vhdl/common_fifo_dc_mixed_widths.vhd
+    src/vhdl/common_fifo_dc_mixed_widths_a_stratix4.vhd
+    src/vhdl/common_fifo_dc.vhd
+    src/vhdl/common_fifo_dc_a_stratix4.vhd
+    src/vhdl/common_blockreg.vhd
+    src/vhdl/common_fifo_dc_lock_control.vhd
+    src/vhdl/common_mem_mux.vhd
+    src/vhdl/common_reg_cross_domain.vhd
+    src/vhdl/common_reg_r_w.vhd
+    src/vhdl/common_reg_r_w_dc.vhd
+    src/vhdl/common_ram_crw_crw_ratio.vhd
+    src/vhdl/common_ram_crw_crw_ratio_a_stratix4.vhd
+    src/vhdl/common_ram_crw_crw.vhd
+    src/vhdl/common_ram_crw_crw_a_stratix4.vhd
+    src/vhdl/common_ram_crw_cr.vhd
+    src/vhdl/common_ram_crw_cr_a_str.vhd
+    src/vhdl/common_ram_crw_cw.vhd
+    src/vhdl/common_ram_crw_cw_a_str.vhd
+    src/vhdl/common_ram_cr_cw.vhd
+    src/vhdl/common_ram_cr_cw_a_str.vhd
+    src/vhdl/common_ram_cr_cw_ratio.vhd
+    src/vhdl/common_ram_cr_cw_ratio_a_str.vhd
+    src/vhdl/common_ram_rw_rw.vhd
+    src/vhdl/common_ram_rw_rw_a_str.vhd
+    src/vhdl/common_ram_r_w.vhd
+    src/vhdl/common_interleave.vhd
+    src/vhdl/common_deinterleave.vhd
+    src/vhdl/common_reinterleave.vhd
+    src/vhdl/common_ram_r_w_a_str.vhd
+    src/vhdl/common_rom.vhd
+    src/vhdl/common_rom_a_str.vhd
+    src/vhdl/common_paged_reg.vhd
+    src/vhdl/common_paged_ram_crw_crw.vhd
+    src/vhdl/common_paged_ram_rw_rw.vhd
+    src/vhdl/common_paged_ram_r_w.vhd
+    src/vhdl/common_paged_ram_ww_rr.vhd
+    src/vhdl/common_paged_ram_w_rr.vhd
+    src/vhdl/common_zip.vhd
+    src/vhdl/common_duty_cycle.vhd
+    src/vhdl/common_bit_delay.vhd
+    src/vhdl/common_delay.vhd
+    src/vhdl/common_shiftram.vhd
+    
+    src/vhdl/mms_common_reg.vhd
+    src/vhdl/mms_common_stable_monitor.vhd
+        
+    src/vhdl/avs_common_mm.vhd
+    src/vhdl/avs_common_mm_irq.vhd
+    src/vhdl/avs_common_mm_readlatency0.vhd
+    src/vhdl/avs_common_mm_readlatency2.vhd
+    src/vhdl/avs_common_reg_r_w.vhd
+    
+    synth/quartus/common_top.vhd
+
+test_bench_files = 
+    tb/vhdl/tb_common_pkg.vhd
+    tb/vhdl/tb_common_mem_pkg.vhd
+    
+    tb/vhdl/tb_common_acapture.vhd
+    tb/vhdl/tb_common_add_sub.vhd
+    tb/vhdl/tb_common_adder_tree.vhd
+    tb/vhdl/tb_common_async.vhd
+    tb/vhdl/tb_common_clock_phase_detector.vhd
+    tb/vhdl/tb_common_complex_mult.vhd
+    tb/vhdl/tb_common_complex_mult_add_parallel.vhd
+    tb/vhdl/tb_common_complex_mult_add_pipeline.vhd
+    tb/vhdl/tb_common_counter.vhd
+    tb/vhdl/tb_common_ddreg.vhd
+    tb/vhdl/tb_common_debounce.vhd
+    tb/vhdl/tb_common_duty_cycle.vhd
+    tb/vhdl/tb_common_fanout_tree.vhd
+    tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
+    tb/vhdl/tb_common_fifo_rd.vhd
+    tb/vhdl/tb_common_flank_to_pulse.vhd
+    tb/vhdl/tb_common_iobuf_in.vhd
+    tb/vhdl/tb_common_init.vhd
+    tb/vhdl/tb_common_int2float.vhd
+    tb/vhdl/tb_common_mem_mux.vhd
+    tb/vhdl/tb_common_mult.vhd
+    tb/vhdl/tb_common_mult_add2.vhd
+    tb/vhdl/tb_common_multiplexer.vhd
+    tb/vhdl/tb_common_operation_tree.vhd
+    tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+    tb/vhdl/tb_common_paged_ram_ww_rr.vhd
+    tb/vhdl/tb_common_pulse_extend.vhd
+    tb/vhdl/tb_common_pulser.vhd
+    tb/vhdl/tb_common_reg_cross_domain.vhd
+    tb/vhdl/tb_common_reinterleave.vhd
+    tb/vhdl/tb_common_reorder_symbol.vhd
+    tb/vhdl/tb_common_rl.vhd
+    tb/vhdl/tb_common_rl_register.vhd
+    tb/vhdl/tb_common_select_m_symbols.vhd
+    tb/vhdl/tb_common_shiftram.vhd
+    tb/vhdl/tb_common_shiftreg.vhd
+    tb/vhdl/tb_common_spulse.vhd
+    tb/vhdl/tb_common_switch.vhd
+    tb/vhdl/tb_common_toggle.vhd
+    tb/vhdl/tb_common_transpose.vhd
+    tb/vhdl/tb_common_transpose_symbol.vhd
+    tb/vhdl/tb_common_zip.vhd
+    tb/vhdl/tb_requantize.vhd
+    tb/vhdl/tb_resize.vhd
+    tb/vhdl/tb_round.vhd
+    
+    tb/vhdl/tb_tb_common_add_sub.vhd
+    tb/vhdl/tb_tb_common_adder_tree.vhd
+    tb/vhdl/tb_tb_common_fanout_tree.vhd
+    tb/vhdl/tb_tb_common_mult.vhd
+    tb/vhdl/tb_tb_common_multiplexer.vhd
+    tb/vhdl/tb_tb_common_operation_tree.vhd
+    tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
+    tb/vhdl/tb_tb_common_reinterleave.vhd
+    tb/vhdl/tb_tb_common_reorder_symbol.vhd
+    tb/vhdl/tb_tb_common_rl.vhd
+    tb/vhdl/tb_tb_common_rl_register.vhd
+    tb/vhdl/tb_tb_common_transpose.vhd