From 663a87d4af2080e71ae4f40d5ff88909f5af0dfd Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Fri, 23 Jan 2015 15:57:48 +0000
Subject: [PATCH] in xgmii_mac PLL the power_down input has to be controllable
according to quartus compile
---
libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd | 1 +
libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd | 1 +
libraries/technology/eth_10g/tb_tech_eth_10g.vhd | 1 +
libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd | 3 ++-
4 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
index 856638b1b5..ad44883346 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
@@ -185,6 +185,7 @@ BEGIN
)
PORT MAP (
refclk_644 => tr_ref_clk_644,
+ rst_in => mm_rst,
clk_156 => tr_ref_clk_156,
clk_312 => tr_ref_clk_312,
rst_156 => tr_ref_rst_156,
diff --git a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
index 0d7ba4f7c8..6fba84aa3e 100644
--- a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
@@ -101,6 +101,7 @@ BEGIN
)
PORT MAP (
refclk_644 => tr_ref_clk_644,
+ rst_in => '0',
clk_156 => clk_156,
clk_312 => OPEN,
rst_156 => rst_156,
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
index c4b39e6dd8..fd8a3ba1d4 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
@@ -229,6 +229,7 @@ BEGIN
)
PORT MAP (
refclk_644 => tr_ref_clk_644,
+ rst_in => mm_rst,
clk_156 => tr_ref_clk_156,
clk_312 => tr_ref_clk_312,
rst_156 => tr_ref_rst_156,
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index c149f89bab..65d077be48 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -49,6 +49,7 @@ ENTITY tech_pll_xgmii_mac_clocks IS
);
PORT (
refclk_644 : IN STD_LOGIC; -- 644.53125 MHz reference clock for PLL
+ rst_in : IN STD_LOGIC; -- PLL powerdown input, as reset
clk_156 : OUT STD_LOGIC; -- 156.25 MHz PLL output clock
clk_312 : OUT STD_LOGIC; -- 312.5 MHz PLL output clock
rst_156 : OUT STD_LOGIC; -- reset in clk_156 domain based on PLL locked
@@ -70,7 +71,7 @@ BEGIN
u0 : ip_arria10_pll_xgmii_mac_clocks
PORT MAP (
pll_refclk0 => refclk_644,
- pll_powerdown => '0',
+ pll_powerdown => rst_in,
pll_locked => pll_locked,
outclk0 => i_clk_156,
pll_cal_busy => OPEN,
--
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