diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index 7f4b54b25ff6c6364389ef12711d18042f36a542..72b511a2c90420e1732e0aaa2e802a18a2ccfe0a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_info.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_input_monitor.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0xEC000' end='0xEC200' datawidth='32' /><slave name='reg_wg.mem' start='0xEC200' end='0xEC300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0xEC300' end='0xEC400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0xEC400' end='0xEC500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0xEC500' end='0xEC600' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0xEC600' end='0xEC640' datawidth='32' /><slave name='reg_bsn_align.mem' start='0xEC640' end='0xEC680' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xEC680' end='0xEC6C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xEC6C0' end='0xEC700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xEC700' end='0xEC740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xEC740' end='0xEC780' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0xEC780' end='0xEC7A0' datawidth='32' /><slave name='reg_output_monitor.mem' start='0xEC7A0' end='0xEC7C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xEC7C0' end='0xEC7E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xEC7E0' end='0xEC800' datawidth='32' /><slave name='reg_epcs.mem' start='0xEC800' end='0xEC820' datawidth='32' /><slave name='reg_remu.mem' start='0xEC820' end='0xEC840' datawidth='32' /><slave name='pio_wdi.s1' start='0xEC840' end='0xEC850' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0xEC850' end='0xEC860' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xEC860' end='0xEC870' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xEC870' end='0xEC880' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xEC880' end='0xEC890' datawidth='32' /><slave name='pio_pps.mem' start='0xEC890' end='0xEC8A0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0xEC8A0' end='0xEC8A8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xEC8A8' end='0xEC8B0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xEC8B0' end='0xEC8B8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xEC8B8' end='0xEC8C0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xEC8C0' end='0xEC8C8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xEC8C8' end='0xEC8D0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xEC8D0' end='0xEC8D8' datawidth='32' /><slave name='reg_si.mem' start='0xEC8D8' end='0xEC8E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xEC8E0' end='0xEC8E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC8E8' end='0xEC8F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC8F0' end='0xEC8F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC8F8' end='0xEC900' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC900' end='0xEC908' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_input_monitor.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE8000' end='0xF0000' datawidth='32' /><slave name='jesd204b.mem' start='0xF0000' end='0xF4000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0xF4000' end='0xF4200' datawidth='32' /><slave name='reg_wg.mem' start='0xF4200' end='0xF4300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0xF4300' end='0xF4400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0xF4400' end='0xF4500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0xF4500' end='0xF4600' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0xF4600' end='0xF4640' datawidth='32' /><slave name='reg_bsn_align.mem' start='0xF4640' end='0xF4680' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xF4680' end='0xF46C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xF46C0' end='0xF4700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xF4700' end='0xF4740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xF4740' end='0xF4780' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0xF4780' end='0xF47A0' datawidth='32' /><slave name='reg_output_monitor.mem' start='0xF47A0' end='0xF47C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xF47C0' end='0xF47E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xF47E0' end='0xF4800' datawidth='32' /><slave name='reg_epcs.mem' start='0xF4800' end='0xF4820' datawidth='32' /><slave name='reg_remu.mem' start='0xF4820' end='0xF4840' datawidth='32' /><slave name='reg_ring_info.mem' start='0xF4840' end='0xF4850' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0xF4850' end='0xF4860' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xF4860' end='0xF4870' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xF4870' end='0xF4880' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xF4880' end='0xF4890' datawidth='32' /><slave name='pio_pps.mem' start='0xF4890' end='0xF48A0' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0xF48A0' end='0xF48A8' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0xF48A8' end='0xF48B0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xF48B0' end='0xF48B8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xF48B8' end='0xF48C0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xF48C0' end='0xF48C8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xF48C8' end='0xF48D0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xF48D0' end='0xF48D8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xF48D8' end='0xF48E0' datawidth='32' /><slave name='reg_si.mem' start='0xF48E0' end='0xF48E8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xF48E8' end='0xF48F0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xF48F0' end='0xF48F8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xF48F8' end='0xF4900' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xF4900' end='0xF4908' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xF4908' end='0xF4910' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_info.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_input_monitor.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0xEC000' end='0xEC200' datawidth='32' /><slave name='reg_wg.mem' start='0xEC200' end='0xEC300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0xEC300' end='0xEC400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0xEC400' end='0xEC500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0xEC500' end='0xEC600' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0xEC600' end='0xEC640' datawidth='32' /><slave name='reg_bsn_align.mem' start='0xEC640' end='0xEC680' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xEC680' end='0xEC6C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xEC6C0' end='0xEC700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xEC700' end='0xEC740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xEC740' end='0xEC780' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0xEC780' end='0xEC7A0' datawidth='32' /><slave name='reg_output_monitor.mem' start='0xEC7A0' end='0xEC7C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xEC7C0' end='0xEC7E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xEC7E0' end='0xEC800' datawidth='32' /><slave name='reg_epcs.mem' start='0xEC800' end='0xEC820' datawidth='32' /><slave name='reg_remu.mem' start='0xEC820' end='0xEC840' datawidth='32' /><slave name='pio_wdi.s1' start='0xEC840' end='0xEC850' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0xEC850' end='0xEC860' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xEC860' end='0xEC870' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xEC870' end='0xEC880' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xEC880' end='0xEC890' datawidth='32' /><slave name='pio_pps.mem' start='0xEC890' end='0xEC8A0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0xEC8A0' end='0xEC8A8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xEC8A8' end='0xEC8B0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xEC8B0' end='0xEC8B8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xEC8B8' end='0xEC8C0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xEC8C0' end='0xEC8C8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xEC8C8' end='0xEC8D0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xEC8D0' end='0xEC8D8' datawidth='32' /><slave name='reg_si.mem' start='0xEC8D8' end='0xEC8E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xEC8E0' end='0xEC8E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC8E8' end='0xEC8F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC8F0' end='0xEC8F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC8F8' end='0xEC900' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC900' end='0xEC908' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_input_monitor.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE8000' end='0xF0000' datawidth='32' /><slave name='jesd204b.mem' start='0xF0000' end='0xF4000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0xF4000' end='0xF4200' datawidth='32' /><slave name='reg_wg.mem' start='0xF4200' end='0xF4300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0xF4300' end='0xF4400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0xF4400' end='0xF4500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0xF4500' end='0xF4600' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0xF4600' end='0xF4640' datawidth='32' /><slave name='reg_bsn_align.mem' start='0xF4640' end='0xF4680' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xF4680' end='0xF46C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xF46C0' end='0xF4700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xF4700' end='0xF4740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xF4740' end='0xF4780' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0xF4780' end='0xF47A0' datawidth='32' /><slave name='reg_output_monitor.mem' start='0xF47A0' end='0xF47C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xF47C0' end='0xF47E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xF47E0' end='0xF4800' datawidth='32' /><slave name='reg_epcs.mem' start='0xF4800' end='0xF4820' datawidth='32' /><slave name='reg_remu.mem' start='0xF4820' end='0xF4840' datawidth='32' /><slave name='reg_ring_info.mem' start='0xF4840' end='0xF4850' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0xF4850' end='0xF4860' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xF4860' end='0xF4870' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xF4870' end='0xF4880' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xF4880' end='0xF4890' datawidth='32' /><slave name='pio_pps.mem' start='0xF4890' end='0xF48A0' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0xF48A0' end='0xF48A8' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0xF48A8' end='0xF48B0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xF48B0' end='0xF48B8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xF48B8' end='0xF48C0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xF48C0' end='0xF48C8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xF48C8' end='0xF48D0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xF48D0' end='0xF48D8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xF48D8' end='0xF48E0' datawidth='32' /><slave name='reg_si.mem' start='0xF48E0' end='0xF48E8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xF48E8' end='0xF48F0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xF48F0' end='0xF48F8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xF48F8' end='0xF4900' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xF4900' end='0xF4908' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xF4908' end='0xF4910' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index 8d96a00fac81e35c525bd152405064bfc7c40e8b..8057e4150eb27e12adcea63328f7802b3e6dfaad 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "950272";
+ value = "983040";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "968960";
+ value = "1001736";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "968888";
+ value = "1001664";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "968848";
+ value = "1001616";
type = "String";
}
}
@@ -202,7 +202,7 @@
{
datum baseAddress
{
- value = "968768";
+ value = "12304";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "917504";
+ value = "950272";
type = "String";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "98304";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "967424";
+ value = "1000192";
type = "String";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "968832";
+ value = "1001600";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "968256";
+ value = "1001024";
type = "String";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "968912";
+ value = "1001688";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "968640";
+ value = "1001408";
type = "String";
}
}
@@ -522,7 +522,7 @@
{
datum baseAddress
{
- value = "968320";
+ value = "1001088";
type = "String";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "968384";
+ value = "1001152";
type = "String";
}
}
@@ -570,7 +570,7 @@
{
datum baseAddress
{
- value = "968784";
+ value = "1001552";
type = "String";
}
}
@@ -586,7 +586,7 @@
{
datum baseAddress
{
- value = "968192";
+ value = "1000960";
type = "String";
}
}
@@ -602,7 +602,7 @@
{
datum baseAddress
{
- value = "968904";
+ value = "1001680";
type = "String";
}
}
@@ -634,7 +634,7 @@
{
datum baseAddress
{
- value = "968816";
+ value = "1001584";
type = "String";
}
}
@@ -655,7 +655,7 @@
{
datum baseAddress
{
- value = "968952";
+ value = "1001728";
type = "String";
}
}
@@ -676,7 +676,7 @@
{
datum baseAddress
{
- value = "968944";
+ value = "1001720";
type = "String";
}
}
@@ -697,7 +697,7 @@
{
datum baseAddress
{
- value = "968704";
+ value = "1001472";
type = "String";
}
}
@@ -713,7 +713,7 @@
{
datum baseAddress
{
- value = "968672";
+ value = "1001440";
type = "String";
}
}
@@ -734,7 +734,7 @@
{
datum baseAddress
{
- value = "968512";
+ value = "1001280";
type = "String";
}
}
@@ -750,7 +750,7 @@
{
datum baseAddress
{
- value = "966656";
+ value = "999424";
type = "String";
}
}
@@ -787,7 +787,7 @@
{
datum baseAddress
{
- value = "968936";
+ value = "1001712";
type = "String";
}
}
@@ -808,7 +808,7 @@
{
datum baseAddress
{
- value = "968928";
+ value = "1001704";
type = "String";
}
}
@@ -824,7 +824,7 @@
{
datum baseAddress
{
- value = "968864";
+ value = "1001640";
type = "String";
}
}
@@ -840,7 +840,7 @@
{
datum baseAddress
{
- value = "968896";
+ value = "1001672";
type = "String";
}
}
@@ -856,7 +856,7 @@
{
datum baseAddress
{
- value = "98304";
+ value = "917504";
type = "String";
}
}
@@ -872,7 +872,7 @@
{
datum baseAddress
{
- value = "968608";
+ value = "1001376";
type = "String";
}
}
@@ -893,7 +893,7 @@
{
datum baseAddress
{
- value = "968736";
+ value = "1001504";
type = "String";
}
}
@@ -909,7 +909,7 @@
{
datum baseAddress
{
- value = "12304";
+ value = "1001536";
type = "String";
}
}
@@ -925,7 +925,7 @@
{
datum baseAddress
{
- value = "12296";
+ value = "1001632";
type = "String";
}
}
@@ -941,7 +941,7 @@
{
datum baseAddress
{
- value = "968448";
+ value = "1001216";
type = "String";
}
}
@@ -957,7 +957,7 @@
{
datum baseAddress
{
- value = "968920";
+ value = "1001696";
type = "String";
}
}
@@ -973,7 +973,7 @@
{
datum baseAddress
{
- value = "968800";
+ value = "1001568";
type = "String";
}
}
@@ -989,7 +989,7 @@
{
datum baseAddress
{
- value = "968880";
+ value = "1001656";
type = "String";
}
}
@@ -1005,7 +1005,7 @@
{
datum baseAddress
{
- value = "968872";
+ value = "1001648";
type = "String";
}
}
@@ -1057,6 +1057,38 @@
type = "String";
}
}
+ element reg_tr_10gbe_eth10g
+ {
+ datum _sortIndex
+ {
+ value = "68";
+ type = "int";
+ }
+ }
+ element reg_tr_10gbe_eth10g.mem
+ {
+ datum baseAddress
+ {
+ value = "12296";
+ type = "String";
+ }
+ }
+ element reg_tr_10gbe_mac
+ {
+ datum _sortIndex
+ {
+ value = "69";
+ type = "int";
+ }
+ }
+ element reg_tr_10gbe_mac.mem
+ {
+ datum baseAddress
+ {
+ value = "32768";
+ type = "String";
+ }
+ }
element reg_unb_pmbus
{
datum _sortIndex
@@ -1069,7 +1101,7 @@
{
datum baseAddress
{
- value = "967680";
+ value = "1000448";
type = "String";
}
}
@@ -1085,7 +1117,7 @@
{
datum baseAddress
{
- value = "967936";
+ value = "1000704";
type = "String";
}
}
@@ -1127,7 +1159,7 @@
{
datum baseAddress
{
- value = "967168";
+ value = "999936";
type = "String";
}
}
@@ -1143,7 +1175,7 @@
{
datum baseAddress
{
- value = "968576";
+ value = "1001344";
type = "String";
}
}
@@ -3212,6 +3244,76 @@
internal="reg_stat_hdr_dat_xst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_tr_10gbe_eth10g_address"
+ internal="reg_tr_10gbe_eth10g.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_eth10g_clk"
+ internal="reg_tr_10gbe_eth10g.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_eth10g_read"
+ internal="reg_tr_10gbe_eth10g.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_eth10g_readdata"
+ internal="reg_tr_10gbe_eth10g.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_eth10g_reset"
+ internal="reg_tr_10gbe_eth10g.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_eth10g_write"
+ internal="reg_tr_10gbe_eth10g.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_eth10g_writedata"
+ internal="reg_tr_10gbe_eth10g.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_mac_address"
+ internal="reg_tr_10gbe_mac.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_mac_clk"
+ internal="reg_tr_10gbe_mac.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_mac_read"
+ internal="reg_tr_10gbe_mac.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_mac_readdata"
+ internal="reg_tr_10gbe_mac.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_mac_reset"
+ internal="reg_tr_10gbe_mac.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_mac_write"
+ internal="reg_tr_10gbe_mac.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_mac_writedata"
+ internal="reg_tr_10gbe_mac.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_unb_pmbus_address"
internal="reg_unb_pmbus.address"
@@ -6366,7 +6468,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_info.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_input_monitor.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0xEC000' end='0xEC200' datawidth='32' /><slave name='reg_wg.mem' start='0xEC200' end='0xEC300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0xEC300' end='0xEC400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0xEC400' end='0xEC500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0xEC500' end='0xEC600' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0xEC600' end='0xEC640' datawidth='32' /><slave name='reg_bsn_align.mem' start='0xEC640' end='0xEC680' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xEC680' end='0xEC6C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xEC6C0' end='0xEC700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xEC700' end='0xEC740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xEC740' end='0xEC780' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0xEC780' end='0xEC7A0' datawidth='32' /><slave name='reg_output_monitor.mem' start='0xEC7A0' end='0xEC7C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xEC7C0' end='0xEC7E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xEC7E0' end='0xEC800' datawidth='32' /><slave name='reg_epcs.mem' start='0xEC800' end='0xEC820' datawidth='32' /><slave name='reg_remu.mem' start='0xEC820' end='0xEC840' datawidth='32' /><slave name='pio_wdi.s1' start='0xEC840' end='0xEC850' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0xEC850' end='0xEC860' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xEC860' end='0xEC870' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xEC870' end='0xEC880' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xEC880' end='0xEC890' datawidth='32' /><slave name='pio_pps.mem' start='0xEC890' end='0xEC8A0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0xEC8A0' end='0xEC8A8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xEC8A8' end='0xEC8B0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xEC8B0' end='0xEC8B8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xEC8B8' end='0xEC8C0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xEC8C0' end='0xEC8C8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xEC8C8' end='0xEC8D0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xEC8D0' end='0xEC8D8' datawidth='32' /><slave name='reg_si.mem' start='0xEC8D8' end='0xEC8E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xEC8E0' end='0xEC8E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC8E8' end='0xEC8F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC8F0' end='0xEC8F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC8F8' end='0xEC900' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC900' end='0xEC908' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_input_monitor.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE8000' end='0xF0000' datawidth='32' /><slave name='jesd204b.mem' start='0xF0000' end='0xF4000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0xF4000' end='0xF4200' datawidth='32' /><slave name='reg_wg.mem' start='0xF4200' end='0xF4300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0xF4300' end='0xF4400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0xF4400' end='0xF4500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0xF4500' end='0xF4600' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0xF4600' end='0xF4640' datawidth='32' /><slave name='reg_bsn_align.mem' start='0xF4640' end='0xF4680' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xF4680' end='0xF46C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xF46C0' end='0xF4700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xF4700' end='0xF4740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xF4740' end='0xF4780' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0xF4780' end='0xF47A0' datawidth='32' /><slave name='reg_output_monitor.mem' start='0xF47A0' end='0xF47C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xF47C0' end='0xF47E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xF47E0' end='0xF4800' datawidth='32' /><slave name='reg_epcs.mem' start='0xF4800' end='0xF4820' datawidth='32' /><slave name='reg_remu.mem' start='0xF4820' end='0xF4840' datawidth='32' /><slave name='reg_ring_info.mem' start='0xF4840' end='0xF4850' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0xF4850' end='0xF4860' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xF4860' end='0xF4870' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xF4870' end='0xF4880' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xF4880' end='0xF4890' datawidth='32' /><slave name='pio_pps.mem' start='0xF4890' end='0xF48A0' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0xF48A0' end='0xF48A8' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0xF48A8' end='0xF48B0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xF48B0' end='0xF48B8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xF48B8' end='0xF48C0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xF48C0' end='0xF48C8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xF48C8' end='0xF48D0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xF48D0' end='0xF48D8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xF48D8' end='0xF48E0' datawidth='32' /><slave name='reg_si.mem' start='0xF48E0' end='0xF48E8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xF48E8' end='0xF48F0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xF48F0' end='0xF48F8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xF48F8' end='0xF4900' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xF4900' end='0xF4908' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xF4908' end='0xF4910' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -12671,37 +12773,1269 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_fil_coefs"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>65536</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_scrap"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>2048</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>11</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_fil_coefs"
+ name="ram_ss_ss_wide"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13287,37 +14621,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_scrap"
+ name="ram_st_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13333,7 +14667,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13397,7 +14731,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13466,7 +14800,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13872,11 +15206,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>11</value>
+ <value>14</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -13903,37 +15237,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_ss_ss_wide"
+ name="ram_st_histogram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13949,7 +15283,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14013,7 +15347,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14082,7 +15416,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14488,11 +15822,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14519,37 +15853,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_bst"
+ name="ram_st_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14565,7 +15899,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14629,7 +15963,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14698,7 +16032,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15104,11 +16438,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>14</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15135,37 +16469,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_histogram"
+ name="ram_st_xsq"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15181,7 +16515,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15245,7 +16579,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15314,7 +16648,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15720,11 +17054,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15751,37 +17085,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_sst"
+ name="ram_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16367,37 +17701,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_xsq"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16413,7 +17747,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16477,7 +17811,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16546,7 +17880,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16952,11 +18286,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16983,37 +18317,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_wg"
+ name="reg_bf_scale"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17029,7 +18363,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17093,7 +18427,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17162,7 +18496,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17568,11 +18902,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17599,37 +18933,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="reg_bsn_align"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17645,7 +18979,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17709,7 +19043,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17778,7 +19112,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18184,11 +19518,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18215,37 +19549,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bf_scale"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18261,7 +19595,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18325,7 +19659,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18394,7 +19728,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18800,11 +20134,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18831,37 +20165,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_align"
+ name="reg_bsn_monitor_v2_ring_rx_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18877,7 +20211,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18941,7 +20275,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19010,7 +20344,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19416,11 +20750,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19447,37 +20781,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_bsn_monitor_v2_ring_tx_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19493,7 +20827,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19557,7 +20891,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19626,7 +20960,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20032,11 +21366,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20063,37 +21397,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_rx_xst"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20109,7 +21443,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20173,7 +21507,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20242,7 +21576,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20648,11 +21982,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20679,37 +22013,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_tx_xst"
+ name="reg_bsn_source_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20725,7 +22059,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20789,7 +22123,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20858,7 +22192,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21264,11 +22598,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21295,37 +22629,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_sync_scheduler_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21341,7 +22675,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21405,7 +22739,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21474,7 +22808,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21880,11 +23214,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21911,37 +23245,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source_v2"
+ name="reg_crosslets_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21957,7 +23291,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22021,7 +23355,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22090,7 +23424,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22496,11 +23830,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22527,37 +23861,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_sync_scheduler_xsub"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22573,7 +23907,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22637,7 +23971,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22706,7 +24040,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23112,11 +24446,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23143,37 +24477,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_crosslets_info"
+ name="reg_dp_block_validate_bsn_at_sync_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23189,7 +24523,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23253,7 +24587,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23322,7 +24656,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23728,11 +25062,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23759,37 +25093,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_dp_block_validate_err_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23805,7 +25139,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23869,7 +25203,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23938,7 +25272,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24344,11 +25678,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24375,37 +25709,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_bsn_at_sync_xst"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24421,7 +25755,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24485,7 +25819,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24554,7 +25888,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24960,11 +26294,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24991,37 +26325,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_err_xst"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25037,7 +26371,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25101,7 +26435,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25170,7 +26504,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25576,11 +26910,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25607,37 +26941,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_dp_xonoff"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25653,7 +26987,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25717,7 +27051,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25786,7 +27120,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26192,11 +27526,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26223,37 +27557,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26269,7 +27603,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26333,7 +27667,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26402,7 +27736,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26808,11 +28142,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26839,37 +28173,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_xonoff"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26885,7 +28219,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26949,7 +28283,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27018,7 +28352,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27424,11 +28758,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27455,37 +28789,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27501,7 +28835,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27565,7 +28899,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27634,7 +28968,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28040,11 +29374,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28071,37 +29405,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28117,7 +29451,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28181,7 +29515,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28250,7 +29584,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28656,11 +29990,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28687,37 +30021,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28733,7 +30067,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28797,7 +30131,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28866,7 +30200,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29272,11 +30606,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29303,37 +30637,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29349,7 +30683,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29413,7 +30747,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29482,7 +30816,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29888,11 +31222,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29919,37 +31253,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_input_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29965,7 +31299,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30029,7 +31363,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30098,7 +31432,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30504,11 +31838,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30535,37 +31869,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_input_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_hdr_dat"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30581,7 +31915,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30645,7 +31979,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30714,7 +32048,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31120,11 +32454,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31151,37 +32485,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_input_monitor"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31197,7 +32531,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31261,7 +32595,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31330,7 +32664,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31736,11 +33070,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31767,37 +33101,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_input_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_input_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_nof_crosslets"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32383,37 +33717,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_nw_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32999,37 +34333,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nof_crosslets"
+ name="reg_nw_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33045,7 +34379,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33109,7 +34443,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33178,7 +34512,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33584,11 +34918,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33615,37 +34949,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_eth10g"
+ name="reg_output_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33661,7 +34995,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33725,7 +35059,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33794,7 +35128,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34200,11 +35534,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34231,37 +35565,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_output_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_mac"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34277,7 +35611,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34341,7 +35675,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34410,7 +35744,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34816,11 +36150,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34847,37 +36181,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_output_monitor"
+ name="reg_ring_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34893,7 +36227,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34957,7 +36291,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35026,7 +36360,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35432,11 +36766,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -35463,37 +36797,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_output_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_output_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_ring_lane_info_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35509,7 +36843,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35573,7 +36907,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35642,7 +36976,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36048,11 +37382,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36079,37 +37413,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_info"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36125,7 +37459,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36189,7 +37523,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36258,7 +37592,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36664,11 +37998,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36695,37 +38029,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_lane_info_xst"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37311,37 +38645,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_sdp_info"
+ name="reg_stat_enable_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37357,7 +38691,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37421,7 +38755,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37490,7 +38824,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37896,11 +39230,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -37927,37 +39261,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_stat_enable_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38543,37 +39877,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst"
+ name="reg_stat_enable_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38589,7 +39923,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38653,7 +39987,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38722,7 +40056,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39128,11 +40462,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39159,37 +40493,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_sst"
+ name="reg_stat_hdr_dat_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -39205,7 +40539,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39269,7 +40603,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39338,7 +40672,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39744,11 +41078,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39775,37 +41109,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_xst"
+ name="reg_stat_hdr_dat_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -39821,7 +41155,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39885,7 +41219,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39954,7 +41288,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40360,11 +41694,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -40391,37 +41725,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_bst"
+ name="reg_stat_hdr_dat_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -40437,7 +41771,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40501,7 +41835,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40570,7 +41904,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40976,11 +42310,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -41007,37 +42341,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_sst"
+ name="reg_tr_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -41053,7 +42387,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41117,7 +42451,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41186,7 +42520,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -41592,11 +42926,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -41623,37 +42957,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_xst"
+ name="reg_tr_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -41669,7 +43003,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41733,7 +43067,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41802,7 +43136,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42208,11 +43542,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -42239,30 +43573,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -46693,7 +48027,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x000ec900" />
+ <parameter name="baseAddress" value="0x000f4908" />
</connection>
<connection
kind="avalon"
@@ -46707,7 +48041,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="baseAddress" value="0x000ec500" />
+ <parameter name="baseAddress" value="0x000f4500" />
</connection>
<connection
kind="avalon"
@@ -46728,7 +48062,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x000ec890" />
+ <parameter name="baseAddress" value="0x000f4890" />
</connection>
<connection
kind="avalon"
@@ -46742,63 +48076,63 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x000ec820" />
+ <parameter name="baseAddress" value="0x000f4820" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x000ec800" />
+ <parameter name="baseAddress" value="0x000f4800" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x000ec8f8" />
+ <parameter name="baseAddress" value="0x000f4900" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x000ec8f0" />
+ <parameter name="baseAddress" value="0x000f48f8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x000ec8e8" />
+ <parameter name="baseAddress" value="0x000f48f0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x000ec8e0" />
+ <parameter name="baseAddress" value="0x000f48e8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x000ec7e0" />
+ <parameter name="baseAddress" value="0x000f47e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_unb_pmbus.mem">
- <parameter name="baseAddress" value="0x000ec400" />
+ <parameter name="baseAddress" value="0x000f4400" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x000ec740" />
+ <parameter name="baseAddress" value="0x000f4740" />
</connection>
<connection
kind="avalon"
@@ -46812,7 +48146,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x000ec8d8" />
+ <parameter name="baseAddress" value="0x000f48e0" />
</connection>
<connection
kind="avalon"
@@ -46833,7 +48167,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x000ec300" />
+ <parameter name="baseAddress" value="0x000f4300" />
</connection>
<connection
kind="avalon"
@@ -46854,21 +48188,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x000ec8d0" />
+ <parameter name="baseAddress" value="0x000f48d8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x000ec7c0" />
+ <parameter name="baseAddress" value="0x000f47c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_wg.mem">
- <parameter name="baseAddress" value="0x000ec200" />
+ <parameter name="baseAddress" value="0x000f4200" />
</connection>
<connection
kind="avalon"
@@ -46882,21 +48216,21 @@
version="18.0"
start="cpu_0.data_master"
end="jesd204b.mem">
- <parameter name="baseAddress" value="0x000e8000" />
+ <parameter name="baseAddress" value="0x000f0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x000ec8c8" />
+ <parameter name="baseAddress" value="0x000f48d0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
- <parameter name="baseAddress" value="0x000e0000" />
+ <parameter name="baseAddress" value="0x000e8000" />
</connection>
<connection
kind="avalon"
@@ -46917,21 +48251,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x000ec880" />
+ <parameter name="baseAddress" value="0x000f4880" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
- <parameter name="baseAddress" value="0x000ec000" />
+ <parameter name="baseAddress" value="0x000f4000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x000ec870" />
+ <parameter name="baseAddress" value="0x000f4870" />
</connection>
<connection
kind="avalon"
@@ -46945,21 +48279,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x000ec700" />
+ <parameter name="baseAddress" value="0x000f4700" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x000ec8c0" />
+ <parameter name="baseAddress" value="0x000f48c8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_mac.mem">
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x000e0000" />
</connection>
<connection
kind="avalon"
@@ -46980,14 +48314,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x000ec8b8" />
+ <parameter name="baseAddress" value="0x000f48c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x000ec8b0" />
+ <parameter name="baseAddress" value="0x000f48b8" />
</connection>
<connection
kind="avalon"
@@ -47001,7 +48335,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
- <parameter name="baseAddress" value="0x000ec860" />
+ <parameter name="baseAddress" value="0x000f4860" />
</connection>
<connection
kind="avalon"
@@ -47015,7 +48349,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x000ec6c0" />
+ <parameter name="baseAddress" value="0x000f46c0" />
</connection>
<connection
kind="avalon"
@@ -47029,7 +48363,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
- <parameter name="baseAddress" value="0x000ec8a8" />
+ <parameter name="baseAddress" value="0x000f48b0" />
</connection>
<connection
kind="avalon"
@@ -47043,28 +48377,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
- <parameter name="baseAddress" value="0x000ec680" />
+ <parameter name="baseAddress" value="0x000f4680" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_st_histogram.mem">
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00018000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
- <parameter name="baseAddress" value="0x000ec8a0" />
+ <parameter name="baseAddress" value="0x000f48a8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_align.mem">
- <parameter name="baseAddress" value="0x000ec640" />
+ <parameter name="baseAddress" value="0x000f4640" />
</connection>
<connection
kind="avalon"
@@ -47078,21 +48412,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_output_monitor.mem">
- <parameter name="baseAddress" value="0x000ec7a0" />
+ <parameter name="baseAddress" value="0x000f47a0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_xst_udp_monitor.mem">
- <parameter name="baseAddress" value="0x000ec780" />
+ <parameter name="baseAddress" value="0x000f4780" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_lane_info_xst.mem">
- <parameter name="baseAddress" value="0x3008" />
+ <parameter name="baseAddress" value="0x000f48a0" />
</connection>
<connection
kind="avalon"
@@ -47113,21 +48447,35 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
- <parameter name="baseAddress" value="0x000ec600" />
+ <parameter name="baseAddress" value="0x000f4600" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
- <parameter name="baseAddress" value="0x000ec850" />
+ <parameter name="baseAddress" value="0x000f4850" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_info.mem">
- <parameter name="baseAddress" value="0x3010" />
+ <parameter name="baseAddress" value="0x000f4840" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_tr_10gbe_eth10g.mem">
+ <parameter name="baseAddress" value="0x3008" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_tr_10gbe_mac.mem">
+ <parameter name="baseAddress" value="0x8000" />
</connection>
<connection
kind="avalon"
@@ -47162,7 +48510,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_wdi.s1">
- <parameter name="baseAddress" value="0x000ec840" />
+ <parameter name="baseAddress" value="0x3010" />
</connection>
<connection
kind="avalon"
@@ -47452,6 +48800,16 @@
version="18.0"
start="clk_0.clk"
end="reg_ring_info.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_tr_10gbe_eth10g.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_tr_10gbe_mac.system" />
<connection
kind="interrupt"
version="18.0"
@@ -47798,6 +49156,16 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_ring_info.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_tr_10gbe_eth10g.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_tr_10gbe_mac.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 2580851b5005275b85fd7d6666cb76a1f9162892..20e80dc85a65f98bd91844426187c2ce16ec22f2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -89,6 +89,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_output_monitor.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 0075eca3896a3cdf012fd5c6db3f6b8ed9447d10..5ce4fcd3b788d92daf80f01eec8c0c068578f635 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -97,6 +97,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_output_monitor.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index 95225f6e0f5a80f49b89b0286171eaa37c0f63e8..c8a726cd92847520110d0bb0881bc941995529be 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -96,6 +96,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_output_monitor.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
index 940afbfec668ef37c46928fddc6d8a9e755aab4b..89891dbafbcff5577dada90a38bd5b69aedd39ac 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
@@ -93,6 +93,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_output_monitor.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
index 54bf042c84f7bebe88727f9198ad7072f34bc980..798d1696c413add3a7677a9b195f74481e774dcd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -96,6 +96,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_output_monitor.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
index c34587868aeba259066652119f02d3ca8790e000..a794505be0ddfe6ad85c2d1eba571ece74bc2348 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
@@ -93,6 +93,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_output_monitor.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index de89d4a9e2d6aadf8587702688265f845e180000..e85b584af4e870d88793a093a7cb273c5f744d84 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -239,46 +239,46 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_nw_10GbE_eth10g_miso : IN t_mem_miso;
-- XST bsn aligner_v2
- reg_bsn_align_copi : IN t_mem_mosi;
- reg_bsn_align_cipo : OUT t_mem_miso;
+ reg_bsn_align_copi : OUT t_mem_mosi;
+ reg_bsn_align_cipo : IN t_mem_miso;
-- XST bsn aligner_v2 bsn monitors
- reg_input_monitor_copi : IN t_mem_mosi;
- reg_input_monitor_cipo : OUT t_mem_miso;
- reg_output_monitor_copi : IN t_mem_mosi;
- reg_output_monitor_cipo : OUT t_mem_miso;
+ reg_input_monitor_copi : OUT t_mem_mosi;
+ reg_input_monitor_cipo : IN t_mem_miso;
+ reg_output_monitor_copi : OUT t_mem_mosi;
+ reg_output_monitor_cipo : IN t_mem_miso;
-- XST UDP offload bsn monitor
- reg_xst_udp_monitor_copi : IN t_mem_mosi;
- reg_xst_udp_monitor_cipo : OUT t_mem_miso;
+ reg_xst_udp_monitor_copi : OUT t_mem_mosi;
+ reg_xst_udp_monitor_cipo : IN t_mem_miso;
-- XST ring lane info
- reg_ring_lane_info_xst_copi : IN t_mem_mosi;
- reg_ring_lane_info_xst_cipo : OUT t_mem_miso;
+ reg_ring_lane_info_xst_copi : OUT t_mem_mosi;
+ reg_ring_lane_info_xst_cipo : IN t_mem_miso;
-- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_ring_rx_xst_copi: OUT t_mem_mosi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: IN t_mem_miso;
-- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_ring_tx_xst_copi : OUT t_mem_mosi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : IN t_mem_miso;
-- XST ring validate err
- reg_dp_block_validate_err_xst_copi : IN t_mem_mosi;
- reg_dp_block_validate_err_xst_cipo : OUT t_mem_miso;
+ reg_dp_block_validate_err_xst_copi : OUT t_mem_mosi;
+ reg_dp_block_validate_err_xst_cipo : IN t_mem_miso;
-- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : IN t_mem_mosi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : OUT t_mem_miso;
+ reg_dp_block_validate_bsn_at_sync_xst_copi : OUT t_mem_mosi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : IN t_mem_miso;
-- XST ring MAC
- reg_tr_10GbE_mac_copi : IN t_mem_mosi;
- reg_tr_10GbE_mac_cipo : OUT t_mem_miso;
+ reg_tr_10GbE_mac_copi : OUT t_mem_mosi;
+ reg_tr_10GbE_mac_cipo : IN t_mem_miso;
-- XST ring ETH
- reg_tr_10GbE_eth10g_copi : IN t_mem_mosi;
- reg_tr_10GbE_eth10g_cipo : OUT t_mem_miso;
+ reg_tr_10GbE_eth10g_copi : OUT t_mem_mosi;
+ reg_tr_10GbE_eth10g_cipo : IN t_mem_miso;
-- Scrap ram
ram_scrap_mosi : OUT t_mem_mosi;
@@ -439,31 +439,38 @@ BEGIN
u_mm_file_reg_nw_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+ u_mm_file_reg_bsn_align : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_align_copi, reg_bsn_align_cipo );
+ u_mm_file_reg_input_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_INPUT_MONITOR")
+ PORT MAP(mm_rst, mm_clk, reg_input_monitor_copi, reg_input_monitor_cipo );
- u_mm_file_reg_bsn_align : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_bsn_align")
- PORT MAP(mm_rst, mm_clk, reg_bsn_align_copi, reg_bsn_align_cipo );
- u_mm_file_reg_input_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_input_monitor")
- PORT MAP(mm_rst, mm_clk, reg_input_monitor_copi, reg_input_monitor_cipo );
- u_mm_file_reg_output_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_output_monitor")
- PORT MAP(mm_rst, mm_clk, reg_output_monitor_copi, reg_output_monitor_cipo );
- u_mm_file_reg_xst_udp_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_xst_udp_monitor")
- PORT MAP(mm_rst, mm_clk, reg_xst_udp_monitor_copi, reg_xst_udp_monitor_cipo );
- u_mm_file_reg_ring_lane_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_ring_lane_info_xst")
- PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_bsn_monitor_v2_ring_rx_xst")
+ u_mm_file_reg_output_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_OUTPUT_MONITOR")
+ PORT MAP(mm_rst, mm_clk, reg_output_monitor_copi, reg_output_monitor_cipo );
+
+ u_mm_file_reg_xst_udp_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_XST_UDP_MONITOR")
+ PORT MAP(mm_rst, mm_clk, reg_xst_udp_monitor_copi, reg_xst_udp_monitor_cipo );
+
+ u_mm_file_reg_ring_lane_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
+ PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_bsn_monitor_v2_ring_tx_xst")
- PORT MAP(mm_rst, mm_clk, _copi, _cipo );
- u_mm_file_reg_dp_block_validate_err_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_dp_block_validate_err_xst")
+
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
+
+ u_mm_file_reg_dp_block_validate_err_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
- u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_dp_block_validate_bsn_at_sync_xst")
+
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
- u_mm_file_reg_tr_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_tr_10GbE_mac")
- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
- u_mm_file_reg_tr_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "reg_tr_10GbE_eth10g")
- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+ u_mm_file_reg_tr_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+
+ u_mm_file_reg_tr_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
@@ -926,7 +933,7 @@ BEGIN
reg_bsn_align_write_export => reg_bsn_align_copi.wr,
reg_bsn_align_writedata_export => reg_bsn_align_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_align_read_export => reg_bsn_align_copi.rd,
- reg_bsn_align_readdata_export => reg_bsn_align_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_align_readdata_export => reg_bsn_align_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_input_monitor_clk_export => OPEN,
reg_input_monitor_reset_export => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 737e82cb1f1359d2aaa45dc24b0ebbe968fad99e..a5ebbddb51b972ff540cc98ea45f69f4761b499a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -351,6 +351,20 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_nw_10gbe_mac_reset_export : out std_logic; -- export
reg_nw_10gbe_mac_write_export : out std_logic; -- export
reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_output_monitor_address_export : out std_logic_vector(2 downto 0); -- export
reg_output_monitor_clk_export : out std_logic; -- export
reg_output_monitor_read_export : out std_logic; -- export
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 6639d32cb224ce41c833c9f7418d8d96c5f923ba..ba9be2780ae073840d0c5f53b77a39619c4216c1 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -1053,7 +1053,7 @@ BEGIN
unb2_board_qsfp_leds_rx_sosi_arr(c_nof_10GbE_offload_streams+c_quad-1 DOWNTO c_quad) <= nw_10gbe_src_out_arr;
-- QSFP 0 - Ring
- unb2_board_qsfp_leds_tx_siso_arr(0 DOWNTO 0) <= tr_10gbe_snk_out_arr;
- unb2_board_qsfp_leds_tx_sosi_arr(0 DOWNTO 0) <= tr_10gbe_snk_in_arr;
- unb2_board_qsfp_leds_rx_sosi_arr(0 DOWNTO 0) <= tr_10gbe_src_out_arr;
+ unb2_board_qsfp_leds_tx_siso_arr(0 DOWNTO 0) <= tr_10gbe_snk_out_arr(0 DOWNTO 0);
+ unb2_board_qsfp_leds_tx_sosi_arr(0 DOWNTO 0) <= tr_10gbe_snk_in_arr(0 DOWNTO 0);
+ unb2_board_qsfp_leds_rx_sosi_arr(0 DOWNTO 0) <= tr_10gbe_src_out_arr(0 DOWNTO 0);
END str;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
index 53d63fe0aa937b6241052077a3594b7e99193d8c..64f65917b628ddbfb991270552efc5a0b6748f46 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
@@ -112,7 +112,7 @@ ARCHITECTURE tb OF tb_st_xst IS
----------------------------------------------------------------------------
SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL st_xst_mm_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL st_xst_mm_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL st_xst_mm_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
SIGNAL in_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
@@ -240,8 +240,8 @@ BEGIN
rd_rst => dp_rst,
rd_clk => dp_clk,
- rd_en => st_xst_mm_mosi_arr(I).rd,
- rd_adr => st_xst_mm_mosi_arr(I).address(c_mm_ram.adr_w-1 DOWNTO 0),
+ rd_en => st_xst_mm_mosi.rd,
+ rd_adr => st_xst_mm_mosi.address(c_mm_ram.adr_w-1 DOWNTO 0),
rd_dat => st_xst_mm_miso_arr(I).rddata(c_mm_ram.dat_w-1 DOWNTO 0),
rd_val => st_xst_mm_miso_arr(I).rdval
);
@@ -269,7 +269,7 @@ BEGIN
in_sosi => in_sosi,
-- DP Memory Mapped
- mm_mosi_arr => st_xst_mm_mosi_arr,
+ mm_mosi => st_xst_mm_mosi,
mm_miso_arr => st_xst_mm_miso_arr,
-- Memory Mapped