diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 897bc9fd572f8bdd39a735f47cec983c542beeac..5bbdd336503d4398956bcd1f019a61b6fe20a7a4 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -54,8 +54,7 @@ ARCHITECTURE tb OF tb_ddrctrl IS
   CONSTANT  c_in_data_w       : NATURAL                                     := g_nof_streams * g_data_w;                -- output data with, 168
   CONSTANT  c_out_data_w      : NATURAL                                     := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
   CONSTANT  c_adr_w           : NATURAL                                     := 4;                                       -- address with in simulation
-  CONSTANT  c_max_adr         : NATURAL                                     := 2**c_adr_w-1;                            -- max address in simulation
-
+  CONSTANT  c_adr_size        : NATURAL                                     := 2**c_adr_w;                              -- address size in simulation
 
   -- function for making total data vector
   FUNCTION  c_total_vector_init RETURN STD_LOGIC_VECTOR IS
@@ -126,17 +125,17 @@ BEGIN
     ASSERT FALSE                                                                                                                            REPORT "Test: OK"                                                                 SEVERITY FAILURE;
   END PROCESS;
 
-  -- excecuting the reset test
+  -- Excecuting the reset test.
   p_test_reset : PROCESS
   BEGIN
     rst <= '0';
     WAIT FOR c_clk_period*g_sim_lengt*3/4;
-    rst <= '1';
-    IF lag_due_reset + TO_UINT(out_mosi.address) >= c_max_adr THEN
-      lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_max_adr;
+    IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
+      lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
     ELSE
       lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
     END IF;
+    rst <= '1';
     WAIT FOR c_clk_period*1;
   END PROCESS;
 
@@ -163,14 +162,15 @@ BEGIN
   -- verifying if the address is correct by keeping trach of the address
   p_verify_address : PROCESS
   BEGIN
-    FOR I IN 0 TO c_max_adr LOOP
-      WAIT UNTIL rising_edge(out_mosi.wr);
-      IF rst = '0' THEN                                                                     -- testing on reset is a bad idea
-        IF I >= lag_due_reset THEN
-          ASSERT I-lag_due_reset = TO_UINT(out_mosi.address)                                                                                REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset)                  SEVERITY ERROR;
-        ELSE
-          ASSERT I+c_max_adr-lag_due_reset+1 = TO_UINT(out_mosi.address)                                                                    REPORT "Wrong address, 2, I = " & NATURAL'image(I+c_max_adr-lag_due_reset+1)      SEVERITY ERROR;
-        END IF;
+    FOR I IN 0 TO c_adr_size-1 LOOP
+      WAIT UNTIL out_mosi.wr = '1';
+      IF rst = '1' THEN
+        WAIT UNTIL out_mosi.wr = '1';
+      END IF;
+      IF I >= lag_due_reset THEN
+        ASSERT I-lag_due_reset   = TO_UINT(out_mosi.address)                           REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address))                SEVERITY ERROR;
+      ELSE
+        ASSERT (I-lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address)                REPORT "Wrong address, 2, I = " & NATURAL'image((I-lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address))   SEVERITY ERROR;
       END IF;
     END LOOP;
   END PROCESS;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
index 60a7cffc69282292c804da7048884f7b858433bf..14c4720aa347f5dc22279a861a8f4aa6a1556694 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
@@ -115,12 +115,12 @@ BEGIN
   BEGIN
     rst <= '0';
     WAIT FOR c_clk_period*g_sim_lengt*3/4;
-    rst <= '1';
     IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
       lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
     ELSE
       lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
     END IF;
+    rst <= '1';
     WAIT FOR c_clk_period*1;
   END PROCESS;
 
@@ -128,13 +128,14 @@ BEGIN
   p_verify_address : PROCESS
   BEGIN
     FOR I IN 0 TO c_adr_size-1 LOOP
-      WAIT UNTIL rising_edge(out_mosi.wr);
-      IF rst = '0' THEN                                                                     -- testing on reset is a bad idea
-        IF I >= lag_due_reset THEN
-          ASSERT I-lag_due_reset = TO_UINT(out_mosi.address)                             REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset)                SEVERITY ERROR;
-        ELSE
-          ASSERT (I-lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address)                REPORT "Wrong address, 2, I = " & NATURAL'image((I-lag_due_reset)+c_adr_size)   SEVERITY ERROR;
-        END IF;
+      WAIT UNTIL out_mosi.wr = '1';
+      IF rst = '1' THEN
+        WAIT UNTIL out_mosi.wr = '1';
+      END IF;
+      IF I >= lag_due_reset THEN
+        ASSERT I-lag_due_reset   = TO_UINT(out_mosi.address)                           REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address))                SEVERITY ERROR;
+      ELSE
+        ASSERT (I-lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address)                REPORT "Wrong address, 2, I = " & NATURAL'image((I-lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address))   SEVERITY ERROR;
       END IF;
     END LOOP;
   END PROCESS;