diff --git a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
index b05c82b799a5ea519ba1d51ce2e2668a9a4bba22..0776996779c75dcf4e92d1fc534c60fae1018ec7 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
+++ b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
@@ -29,7 +29,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "303104";
type = "String";
}
}
@@ -37,7 +37,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "256";
type = "String";
}
}
@@ -85,7 +85,7 @@
{
datum baseAddress
{
- value = "12608";
+ value = "536";
type = "String";
}
}
@@ -130,7 +130,7 @@
{
datum baseAddress
{
- value = "12600";
+ value = "528";
type = "String";
}
}
@@ -162,7 +162,7 @@
{
datum baseAddress
{
- value = "12304";
+ value = "480";
type = "String";
}
}
@@ -178,7 +178,7 @@
{
datum _sortIndex
{
- value = "27";
+ value = "29";
type = "int";
}
}
@@ -186,7 +186,7 @@
{
datum baseAddress
{
- value = "16384";
+ value = "524288";
type = "String";
}
}
@@ -194,7 +194,7 @@
{
datum _sortIndex
{
- value = "25";
+ value = "27";
type = "int";
}
}
@@ -210,7 +210,7 @@
{
datum _sortIndex
{
- value = "19";
+ value = "21";
type = "int";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "256";
+ value = "294912";
type = "String";
}
}
@@ -226,7 +226,7 @@
{
datum _sortIndex
{
- value = "26";
+ value = "28";
type = "int";
}
}
@@ -234,7 +234,7 @@
{
datum baseAddress
{
- value = "12416";
+ value = "352";
type = "String";
}
}
@@ -242,7 +242,7 @@
{
datum _sortIndex
{
- value = "24";
+ value = "26";
type = "int";
}
}
@@ -258,7 +258,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "24";
type = "int";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "1024";
+ value = "32768";
type = "String";
}
}
@@ -274,7 +274,7 @@
{
datum _sortIndex
{
- value = "20";
+ value = "22";
type = "int";
}
}
@@ -282,7 +282,7 @@
{
datum baseAddress
{
- value = "12448";
+ value = "1024";
type = "String";
}
}
@@ -290,7 +290,7 @@
{
datum _sortIndex
{
- value = "21";
+ value = "23";
type = "int";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "13312";
+ value = "262144";
type = "String";
}
}
@@ -306,7 +306,7 @@
{
datum _sortIndex
{
- value = "23";
+ value = "25";
type = "int";
}
}
@@ -314,7 +314,7 @@
{
datum baseAddress
{
- value = "512";
+ value = "16384";
type = "String";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "12592";
+ value = "520";
type = "String";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "12584";
+ value = "512";
type = "String";
}
}
@@ -362,7 +362,7 @@
{
datum baseAddress
{
- value = "12480";
+ value = "384";
type = "String";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "12576";
+ value = "504";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "12296";
+ value = "496";
type = "String";
}
}
@@ -410,11 +410,43 @@
{
datum baseAddress
{
- value = "12512";
+ value = "416";
+ type = "String";
+ }
+ }
+ element reg_tr_10GbE_back0
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ }
+ element reg_tr_10GbE_back0.mem
+ {
+ datum baseAddress
+ {
+ value = "4194304";
+ type = "String";
+ }
+ }
+ element reg_tr_10GbE_back1
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ }
+ element reg_tr_10GbE_back1.mem
+ {
+ datum baseAddress
+ {
+ value = "1048576";
type = "String";
}
}
- element reg_tr_10GbE
+ element reg_tr_10GbE_qsfp_ring
{
datum _sortIndex
{
@@ -422,11 +454,11 @@
type = "int";
}
}
- element reg_tr_10GbE.mem
+ element reg_tr_10GbE_qsfp_ring.mem
{
datum baseAddress
{
- value = "262144";
+ value = "2097152";
type = "String";
}
}
@@ -442,7 +474,7 @@
{
datum baseAddress
{
- value = "12544";
+ value = "448";
type = "String";
}
}
@@ -500,7 +532,7 @@
{
datum baseAddress
{
- value = "12320";
+ value = "320";
type = "String";
}
}
@@ -1205,43 +1237,123 @@
type="conduit"
dir="end" />
<interface
- name="reg_tr_10gbe_address"
- internal="reg_tr_10GbE.address"
+ name="reg_tr_10gbe_back0_address"
+ internal="reg_tr_10GbE_back0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back0_clk"
+ internal="reg_tr_10GbE_back0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back0_read"
+ internal="reg_tr_10GbE_back0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back0_readdata"
+ internal="reg_tr_10GbE_back0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back0_reset"
+ internal="reg_tr_10GbE_back0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back0_waitrequest"
+ internal="reg_tr_10GbE_back0.waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back0_write"
+ internal="reg_tr_10GbE_back0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back0_writedata"
+ internal="reg_tr_10GbE_back0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back1_address"
+ internal="reg_tr_10GbE_back1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back1_clk"
+ internal="reg_tr_10GbE_back1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back1_read"
+ internal="reg_tr_10GbE_back1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back1_readdata"
+ internal="reg_tr_10GbE_back1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back1_reset"
+ internal="reg_tr_10GbE_back1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back1_waitrequest"
+ internal="reg_tr_10GbE_back1.waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back1_write"
+ internal="reg_tr_10GbE_back1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_back1_writedata"
+ internal="reg_tr_10GbE_back1.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_qsfp_ring_address"
+ internal="reg_tr_10GbE_qsfp_ring.address"
type="conduit"
dir="end" />
<interface
- name="reg_tr_10gbe_clk"
- internal="reg_tr_10GbE.clk"
+ name="reg_tr_10gbe_qsfp_ring_clk"
+ internal="reg_tr_10GbE_qsfp_ring.clk"
type="conduit"
dir="end" />
<interface
- name="reg_tr_10gbe_read"
- internal="reg_tr_10GbE.read"
+ name="reg_tr_10gbe_qsfp_ring_read"
+ internal="reg_tr_10GbE_qsfp_ring.read"
type="conduit"
dir="end" />
<interface
- name="reg_tr_10gbe_readdata"
- internal="reg_tr_10GbE.readdata"
+ name="reg_tr_10gbe_qsfp_ring_readdata"
+ internal="reg_tr_10GbE_qsfp_ring.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_tr_10gbe_reset"
- internal="reg_tr_10GbE.reset"
+ name="reg_tr_10gbe_qsfp_ring_reset"
+ internal="reg_tr_10GbE_qsfp_ring.reset"
type="conduit"
dir="end" />
<interface
- name="reg_tr_10gbe_waitrequest"
- internal="reg_tr_10GbE.waitrequest"
+ name="reg_tr_10gbe_qsfp_ring_waitrequest"
+ internal="reg_tr_10GbE_qsfp_ring.waitrequest"
type="conduit"
dir="end" />
<interface
- name="reg_tr_10gbe_write"
- internal="reg_tr_10GbE.write"
+ name="reg_tr_10gbe_qsfp_ring_write"
+ internal="reg_tr_10GbE_qsfp_ring.write"
type="conduit"
dir="end" />
<interface
- name="reg_tr_10gbe_writedata"
- internal="reg_tr_10GbE.writedata"
+ name="reg_tr_10gbe_qsfp_ring_writedata"
+ internal="reg_tr_10GbE_qsfp_ring.writedata"
type="conduit"
dir="end" />
<interface
@@ -1366,10 +1478,10 @@
<parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
- <parameter name="dataAddrWidth" value="19" />
+ <parameter name="dataAddrWidth" value="23" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_diag_bg.mem' start='0x3080' end='0x30A0' /><slave name='reg_dp_offload_tx.mem' start='0x30A0' end='0x30C0' /><slave name='reg_epcs.mem' start='0x30C0' end='0x30E0' /><slave name='reg_remu.mem' start='0x30E0' end='0x3100' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3120' /><slave name='reg_mmdp_ctrl.mem' start='0x3120' end='0x3128' /><slave name='reg_dpmm_data.mem' start='0x3128' end='0x3130' /><slave name='reg_dpmm_ctrl.mem' start='0x3130' end='0x3138' /><slave name='pio_pps.mem' start='0x3138' end='0x3140' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3140' end='0x3148' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='ram_diag_bg.mem' start='0x4000' end='0x8000' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='avs_eth_0.mms_reg' start='0x100' end='0x140' /><slave name='timer_0.s1' start='0x140' end='0x160' /><slave name='reg_diag_bg.mem' start='0x160' end='0x180' /><slave name='reg_epcs.mem' start='0x180' end='0x1A0' /><slave name='reg_remu.mem' start='0x1A0' end='0x1C0' /><slave name='reg_unb_sens.mem' start='0x1C0' end='0x1E0' /><slave name='pio_wdi.s1' start='0x1E0' end='0x1F0' /><slave name='reg_mmdp_data.mem' start='0x1F0' end='0x1F8' /><slave name='reg_mmdp_ctrl.mem' start='0x1F8' end='0x200' /><slave name='reg_dpmm_data.mem' start='0x200' end='0x208' /><slave name='reg_dpmm_ctrl.mem' start='0x208' end='0x210' /><slave name='pio_pps.mem' start='0x210' end='0x218' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x218' end='0x220' /><slave name='reg_dp_offload_tx.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x4000' end='0x8000' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x40000' end='0x48000' /><slave name='reg_bsn_monitor.mem' start='0x48000' end='0x4A000' /><slave name='avs_eth_0.mms_ram' start='0x4A000' end='0x4B000' /><slave name='ram_diag_bg.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@@ -1599,7 +1711,7 @@
</module>
<module name="ram_diag_bg" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="12" />
+ <parameter name="g_adr_w" value="17" />
<parameter name="g_dat_w" value="32" />
</module>
<module
@@ -1613,7 +1725,7 @@
</module>
<module name="reg_bsn_monitor" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="6" />
+ <parameter name="g_adr_w" value="11" />
<parameter name="g_dat_w" value="32" />
</module>
<module name="reg_diag_bg" kind="avs_common_mm" version="1.0" enabled="1">
@@ -1636,7 +1748,7 @@
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="8" />
+ <parameter name="g_adr_w" value="13" />
<parameter name="g_dat_w" value="32" />
</module>
<module
@@ -1645,7 +1757,7 @@
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="3" />
+ <parameter name="g_adr_w" value="8" />
<parameter name="g_dat_w" value="32" />
</module>
<module
@@ -1654,7 +1766,7 @@
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="8" />
+ <parameter name="g_adr_w" value="13" />
<parameter name="g_dat_w" value="32" />
</module>
<module
@@ -1663,7 +1775,7 @@
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="7" />
+ <parameter name="g_adr_w" value="12" />
<parameter name="g_dat_w" value="32" />
</module>
<module name="reg_dpmm_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
@@ -1697,12 +1809,30 @@
<parameter name="g_dat_w" value="32" />
</module>
<module
- name="reg_tr_10GbE"
+ name="reg_tr_10GbE_back0"
kind="avs_common_mm_readlatency0"
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="15" />
+ <parameter name="g_adr_w" value="18" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_tr_10GbE_back1"
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="18" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_tr_10GbE_qsfp_ring"
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="19" />
<parameter name="g_dat_w" value="32" />
</module>
<module name="reg_unb_sens" kind="avs_common_mm" version="1.0" enabled="1">
@@ -1737,7 +1867,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3140" />
+ <parameter name="baseAddress" value="0x0218" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1755,7 +1885,7 @@
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3100" />
+ <parameter name="baseAddress" value="0x01c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1782,7 +1912,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3138" />
+ <parameter name="baseAddress" value="0x0210" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1800,7 +1930,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30e0" />
+ <parameter name="baseAddress" value="0x01a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1809,7 +1939,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30c0" />
+ <parameter name="baseAddress" value="0x0180" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1818,7 +1948,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3130" />
+ <parameter name="baseAddress" value="0x0208" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1827,7 +1957,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3128" />
+ <parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1836,7 +1966,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3120" />
+ <parameter name="baseAddress" value="0x01f8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1845,16 +1975,16 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3008" />
+ <parameter name="baseAddress" value="0x01f0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="14.1"
start="cpu_0.data_master"
- end="reg_tr_10GbE.mem">
+ end="reg_tr_10GbE_qsfp_ring.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00040000" />
+ <parameter name="baseAddress" value="0x00200000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1863,7 +1993,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x00048000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1872,7 +2002,7 @@
start="cpu_0.data_master"
end="reg_dp_offload_tx.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30a0" />
+ <parameter name="baseAddress" value="0x0400" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1881,7 +2011,7 @@
start="cpu_0.data_master"
end="reg_dp_offload_tx_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x00040000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1890,7 +2020,7 @@
start="cpu_0.data_master"
end="reg_dp_offload_rx_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1899,7 +2029,7 @@
start="cpu_0.data_master"
end="reg_dp_offload_tx_hdr_ovr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
+ <parameter name="baseAddress" value="0x4000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1926,7 +2056,7 @@
start="cpu_0.data_master"
end="reg_diag_bg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x0160" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1935,7 +2065,25 @@
start="cpu_0.data_master"
end="ram_diag_bg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x4000" />
+ <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_tr_10GbE_back0.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00400000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_tr_10GbE_back1.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00100000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1944,7 +2092,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x0004a000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1953,7 +2101,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x0100" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1980,7 +2128,7 @@
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3010" />
+ <parameter name="baseAddress" value="0x01e0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1989,7 +2137,7 @@
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3020" />
+ <parameter name="baseAddress" value="0x0140" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2063,7 +2211,7 @@
kind="clock"
version="14.1"
start="clk_0.clk"
- end="reg_tr_10GbE.system" />
+ end="reg_tr_10GbE_qsfp_ring.system" />
<connection
kind="clock"
version="14.1"
@@ -2109,6 +2257,16 @@
version="14.1"
start="clk_0.clk"
end="ram_diag_bg.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_tr_10GbE_back0.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_tr_10GbE_back1.system" />
<connection
kind="interrupt"
version="14.1"
@@ -2211,7 +2369,7 @@
kind="reset"
version="14.1"
start="clk_0.clk_reset"
- end="reg_tr_10GbE.system_reset" />
+ end="reg_tr_10GbE_qsfp_ring.system_reset" />
<connection
kind="reset"
version="14.1"
@@ -2257,6 +2415,16 @@
version="14.1"
start="clk_0.clk_reset"
end="ram_diag_bg.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_tr_10GbE_back0.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_tr_10GbE_back1.system_reset" />
<connection
kind="reset"
version="14.1"
@@ -2346,7 +2514,7 @@
kind="reset"
version="14.1"
start="cpu_0.debug_reset_request"
- end="reg_tr_10GbE.system_reset" />
+ end="reg_tr_10GbE_qsfp_ring.system_reset" />
<connection
kind="reset"
version="14.1"
@@ -2392,6 +2560,16 @@
version="14.1"
start="cpu_0.debug_reset_request"
end="ram_diag_bg.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_tr_10GbE_back0.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_tr_10GbE_back1.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 9358667f7c8cd6196d635b09abeb7ea2bea4be7d..87e442e2c089aa82ef6721c2c0ee3141cf223148 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
+LIBRARY IEEE, common_lib, unb2_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -37,17 +37,22 @@ USE technology_lib.technology_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE work.qsys_unb2_test_pkg.ALL;
+USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
ENTITY mmm_unb2_test IS
GENERIC (
- g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
- g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0;
- g_nof_streams : NATURAL;
- g_bg_block_size : NATURAL;
- g_hdr_field_arr : t_common_field_arr
+ g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_technology : NATURAL := c_tech_arria10;
+ g_bg_block_size : NATURAL;
+ g_hdr_field_arr : t_common_field_arr;
+ g_nof_streams_qsfp : NATURAL;
+ g_nof_streams_ring : NATURAL;
+ g_nof_streams_back0: NATURAL;
+ g_nof_streams_back1: NATURAL
);
PORT (
mm_rst : IN STD_LOGIC;
@@ -132,8 +137,12 @@ ENTITY mmm_unb2_test IS
reg_diag_data_buf_miso : IN t_mem_miso;
-- 10GbE
- reg_tr_10GbE_mosi : OUT t_mem_mosi;
- reg_tr_10GbE_miso : IN t_mem_miso
+ reg_tr_10GbE_qsfp_ring_mosi : OUT t_mem_mosi;
+ reg_tr_10GbE_qsfp_ring_miso : IN t_mem_miso;
+ reg_tr_10GbE_back0_mosi : OUT t_mem_mosi;
+ reg_tr_10GbE_back0_miso : IN t_mem_miso;
+ reg_tr_10GbE_back1_mosi : OUT t_mem_mosi;
+ reg_tr_10GbE_back1_miso : IN t_mem_miso
);
END mmm_unb2_test;
@@ -142,12 +151,13 @@ ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_sim_node_nr : NATURAL := g_sim_node_nr;
CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
+ CONSTANT g_nof_streams : NATURAL := g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back0 + g_nof_streams_back1;
+
-- Block generator
CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
- CONSTANT c_reg_dp_offload_tx_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_adr_w));
+ CONSTANT c_reg_dp_offload_tx_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_unb2_board_peripherals_mm_reg_default.reg_dp_offload_tx_adr_w));
CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
@@ -162,15 +172,15 @@ ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
-- tr_10GbE
- CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := 13;
- CONSTANT c_reg_tr_10GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_tr_10GbE_adr_w));
+ CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := func_tech_mac_10g_csr_addr_w(g_technology);
+ CONSTANT c_reg_tr_10GbE_qsfp_ring_multi_adr_w : NATURAL := ceil_log2((g_nof_streams_qsfp+g_nof_streams_ring) * pow2(c_reg_tr_10GbE_adr_w));
+ CONSTANT c_reg_tr_10GbE_back0_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_back0 * pow2(c_reg_tr_10GbE_adr_w));
+ CONSTANT c_reg_tr_10GbE_back1_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_back1 * pow2(c_reg_tr_10GbE_adr_w));
-- BSN monitors
CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-- Simulation
- CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
-
CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
@@ -252,8 +262,12 @@ BEGIN
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso);
- u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")
- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ u_mm_file_reg_tr_10GbE_back0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+ u_mm_file_reg_tr_10GbE_back1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -414,14 +428,32 @@ BEGIN
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_tr_10gbe_reset_export => OPEN,
- reg_tr_10gbe_clk_export => OPEN,
- reg_tr_10gbe_address_export => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_multi_adr_w-1 DOWNTO 0),
- reg_tr_10gbe_write_export => reg_tr_10GbE_mosi.wr,
- reg_tr_10gbe_writedata_export => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_tr_10gbe_read_export => reg_tr_10GbE_mosi.rd,
- reg_tr_10gbe_readdata_export => reg_tr_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_tr_10gbe_waitrequest_export => reg_tr_10GbE_miso.waitrequest,
+ reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w-1 DOWNTO 0),
+ reg_tr_10gbe_qsfp_ring_write_export => reg_tr_10GbE_qsfp_ring_mosi.wr,
+ reg_tr_10gbe_qsfp_ring_writedata_export => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_qsfp_ring_read_export => reg_tr_10GbE_qsfp_ring_mosi.rd,
+ reg_tr_10gbe_qsfp_ring_readdata_export => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
+
+ reg_tr_10gbe_back0_reset_export => OPEN,
+ reg_tr_10gbe_back0_clk_export => OPEN,
+ reg_tr_10gbe_back0_address_export => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w-1 DOWNTO 0),
+ reg_tr_10gbe_back0_write_export => reg_tr_10GbE_back0_mosi.wr,
+ reg_tr_10gbe_back0_writedata_export => reg_tr_10GbE_back0_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_back0_read_export => reg_tr_10GbE_back0_mosi.rd,
+ reg_tr_10gbe_back0_readdata_export => reg_tr_10GbE_back0_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_back0_waitrequest_export => reg_tr_10GbE_back0_miso.waitrequest,
+
+ reg_tr_10gbe_back1_reset_export => OPEN,
+ reg_tr_10gbe_back1_clk_export => OPEN,
+ reg_tr_10gbe_back1_address_export => reg_tr_10GbE_back1_mosi.address(c_reg_tr_10GbE_back1_multi_adr_w-1 DOWNTO 0),
+ reg_tr_10gbe_back1_write_export => reg_tr_10GbE_back1_mosi.wr,
+ reg_tr_10gbe_back1_writedata_export => reg_tr_10GbE_back1_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_back1_read_export => reg_tr_10GbE_back1_mosi.rd,
+ reg_tr_10gbe_back1_readdata_export => reg_tr_10GbE_back1_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_back1_waitrequest_export => reg_tr_10GbE_back1_miso.waitrequest,
reg_bsn_monitor_reset_export => OPEN,
reg_bsn_monitor_clk_export => OPEN,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index a3d01301eaeffdd978f3b67cd7f9ecff54a0e0c2..82d70b8f2a9ed9e20cc0b98c87bb674b3ab87a77 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -129,49 +129,74 @@ PACKAGE qsys_unb2_test_pkg IS
reg_dpmm_data_address_export : out std_logic;--_vector(0 downto 0); -- export
reg_dpmm_data_clk_export : out std_logic; -- export
reg_dpmm_data_reset_export : out std_logic; -- export
- reg_tr_10gbe_reset_export : out std_logic; -- export
- reg_tr_10gbe_clk_export : out std_logic; -- export
- reg_tr_10gbe_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_write_export : out std_logic; -- export
- reg_tr_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_read_export : out std_logic; -- export
- reg_tr_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_waitrequest_export : in std_logic := 'X'; -- export
+
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(19-1 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(18-1 downto 0); -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(18-1 downto 0); -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+
reg_bsn_monitor_reset_export : out std_logic; -- export
reg_bsn_monitor_clk_export : out std_logic; -- export
- reg_bsn_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_bsn_monitor_address_export : out std_logic_vector(11-1 downto 0); -- export
reg_bsn_monitor_write_export : out std_logic; -- export
reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_read_export : out std_logic; -- export
reg_bsn_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+
reg_dp_offload_tx_reset_export : out std_logic; -- export
reg_dp_offload_tx_clk_export : out std_logic; -- export
- reg_dp_offload_tx_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_offload_tx_address_export : out std_logic_vector(8-1 downto 0); -- export
reg_dp_offload_tx_write_export : out std_logic; -- export
reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_read_export : out std_logic; -- export
reg_dp_offload_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+
reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(13-1 downto 0); -- export
reg_dp_offload_tx_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+
reg_dp_offload_rx_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(13-1 downto 0); -- export
reg_dp_offload_rx_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_rx_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+
reg_dp_offload_tx_hdr_ovr_reset_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_clk_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_ovr_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_offload_tx_hdr_ovr_address_export : out std_logic_vector(12-1 downto 0); -- export
reg_dp_offload_tx_hdr_ovr_write_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_hdr_ovr_read_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+
reg_diag_data_buffer_reset_export : out std_logic; -- export
reg_diag_data_buffer_clk_export : out std_logic; -- export
reg_diag_data_buffer_address_export : out std_logic_vector(4 downto 0); -- export
@@ -193,9 +218,10 @@ PACKAGE qsys_unb2_test_pkg IS
reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_bg_read_export : out std_logic; -- export
reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+
ram_diag_bg_reset_export : out std_logic; -- export
ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_diag_bg_address_export : out std_logic_vector(17-1 downto 0); -- export
ram_diag_bg_write_export : out std_logic; -- export
ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_bg_read_export : out std_logic; -- export