diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 9f20e268cf6ab22a04817c893d8bba1f4a5ae0ab..6f27a4b62d8da0288057e1d70dd0729106e7249b 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -62,7 +62,7 @@ END ddrctrl;
ARCHITECTURE str OF ddrctrl IS
-- constant for readability
- CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w; -- the input data with for ddrctrl_repack
+ CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w; -- the input data with for ddrctrl_repack
-- signals for connecting the components
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 12a9abbd263bb354a571fa6c2f8be1c9cf3a0b18..fa829a0ca0b101d788971212ac445e4a28592aac 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -100,7 +100,7 @@ BEGIN
-- start the test
tb_end <= '0';
- WAIT UNTIL rising_edge(clk); -- align to rising edge
+ WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT FOR c_clk_period*5;
rst <= '1';
WAIT FOR c_clk_period*1;
@@ -111,11 +111,15 @@ BEGIN
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
END IF;
WAIT FOR c_clk_period*1;
- test_running <= '1'; -- start of test
-- filling the input data vectors with the corresponding numbers
- make_data : FOR J IN 0 TO g_sim_length-1 LOOP
- fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
+ fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
+ in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)-1 DOWNTO g_data_w*I);
+ END LOOP;
+ WAIT FOR c_clk_period*1;
+ test_running <= '1'; -- beceause there is al delay in address counter, test running should go up one clockcycle later in order for p_verify to function
+ make_data : FOR J IN 1 TO g_sim_length-1 LOOP
+ fill_in_sosi_arr_rest : FOR I IN 0 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
END LOOP;
WAIT FOR c_clk_period*1;
@@ -172,19 +176,19 @@ BEGIN
-- verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected
p_verify : PROCESS
- VARIABLE ctr_of : NATURAL := 0;
- VARIABLE out_data_cnt : NATURAL := 0;
+ VARIABLE ctr_of : NATURAL := 0;
+ VARIABLE out_data_cnt : NATURAL := 0;
BEGIN
- WAIT UNTIL test_running = '1';
- WAIT UNTIL out_mosi.wr = '1';
- out_data_cnt := out_data_cnt+1;
- IF out_data_cnt mod 2 = 0 THEN
- assert false report "in_data_cnt = " & NATURAL'image(in_data_cnt) & ", out_data_cnt = " & NATURAL'image(out_data_cnt) severity note;
- ctr_of := c_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
- ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
- END IF;
+ WAIT UNTIL rising_edge(clk);
+ IF test_running = '1' AND out_mosi.wr = '1'THEN
+ out_data_cnt := out_data_cnt+1;
+ IF out_data_cnt mod 2 = 0 THEN
+ ctr_of := c_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
+ ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
+ END IF;
ASSERT out_mosi.wrdata(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
+ END IF;
END PROCESS;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
index bcd20dfdeca84167ee4a48d02d9e32a290eb0994..0a5b356e3854690ade8716fec2a97549fd5729d4 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
@@ -101,7 +101,7 @@ BEGIN
-- stopping the test
WAIT FOR c_clk_period*4;
tb_end <= '1';
- ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
+ ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
-- generating compare data for out_mosi
@@ -122,8 +122,8 @@ BEGIN
BEGIN
WAIT UNTIL rising_edge(clk);
IF rising_edge(clk) THEN
- ASSERT q_in_data(c_data_w-1 DOWNTO 0) = out_mosi.wrdata(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata" SEVERITY ERROR;
- ASSERT q_in_data_enable = out_mosi.wr REPORT "in_sosi.valid does not match out_mosi.wr" SEVERITY ERROR;
+ ASSERT q_in_data(c_data_w-1 DOWNTO 0) = out_mosi.wrdata(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata" SEVERITY ERROR;
+ ASSERT q_in_data_enable = out_mosi.wr REPORT "in_sosi.valid does not match out_mosi.wr" SEVERITY ERROR;
END IF;
END PROCESS;
@@ -151,9 +151,9 @@ BEGIN
WAIT UNTIL out_mosi.wr = '1';
END IF;
IF I >= q_lag_due_reset THEN
- ASSERT I-q_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-q_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
+ ASSERT I-q_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-q_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ELSE
- ASSERT (I-q_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
+ ASSERT (I-q_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
END IF;
END LOOP;
END PROCESS;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
index 9406fe04729de6da4e0a7f5164c691ade11a8e63..7044955402ddc05bd96ea7acb5c9f769b5b265f9 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
@@ -99,9 +99,11 @@ BEGIN
rst <= '0';
WAIT FOR c_clk_period*1;
test_running <= '1'; -- start of test
+ in_data_cnt <= in_data_cnt +1;
+ WAIT FOR c_clk_period*1;
-- filling the input vector g_sim_lengt amount of times
- make_in_data : FOR I IN 0 TO g_sim_lengt-1 LOOP
+ make_in_data : FOR I IN 1 TO g_sim_lengt-1 LOOP
in_data(g_in_data_w-1 DOWNTO 0) <= TO_UVEC(I, g_in_data_w);
WAIT FOR c_clk_period*1;
in_data_cnt <= in_data_cnt + 1;
@@ -117,19 +119,19 @@ BEGIN
-- verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected
p_verify : PROCESS
- VARIABLE ctr_of : NATURAL := 0;
- VARIABLE out_data_cnt : NATURAL := 0;
+ VARIABLE ctr_of : NATURAL := 0;
+ VARIABLE out_data_cnt : NATURAL := 0;
BEGIN
- WAIT UNTIL test_running = '1';
- WAIT UNTIL out_sosi.valid = '1';
- out_data_cnt := out_data_cnt+1;
- IF out_data_cnt mod 2 = 0 THEN
- assert false report "in_data_cnt = " & NATURAL'image(in_data_cnt) & ", out_data_cnt = " & NATURAL'image(out_data_cnt) severity note;
- ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
- ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
+ WAIT UNTIL rising_edge(clk);
+ IF test_running = '1' AND out_sosi.valid = '1' THEN
+ out_data_cnt := out_data_cnt+1;
+ IF out_data_cnt mod 2 = 0 THEN
+ ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
+ ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
+ END IF;
+ ASSERT out_sosi.data(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
END IF;
- ASSERT out_sosi.data(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
END PROCESS;