diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
index ec46518bd35820b315fc5357a3ce687181177574..a20c7dff0c20264cf75cd47b395321ba95c95968 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
@@ -69,8 +69,8 @@ BEGIN
gen_wire_bus : FOR i IN 0 TO g_nof_qsfp-1 GENERATE
gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_qsfp.bus_w-1 GENERATE
- si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_qsfp.bus_w);
- serial_rx_arr(i*c_unb2_board_tr_qsfp.bus_w) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i*c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
END GENERATE;
END GENERATE;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
index f68e84df81e458456d5acd97e1219183278dae09..107618feaadd8e1c9cc126a1d31bd598448d3980 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
@@ -25,83 +25,40 @@ USE work.unb2_board_pkg.ALL;
ENTITY unb2_board_ring_io IS
+ GENERIC (
+ g_nof_ring_io : NATURAL := c_unb2_board_tr_ring.nof_bus
+ );
PORT (
- serial_tx_arr : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0);
- serial_rx_arr : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0);
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_ring_io * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_ring_io * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0);
-- ring transceivers
- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0)
+ RING_RX : IN t_unb2_board_ring_bus_2arr(g_nof_ring_io-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ RING_TX : OUT t_unb2_board_ring_bus_2arr(g_nof_ring_io-1 DOWNTO 0)
);
END unb2_board_ring_io;
ARCHITECTURE str OF unb2_board_ring_io IS
-- help signals so we can iterate through buses
- SIGNAL si_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL si_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0);
+ SIGNAL si_tx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_io-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_io-1 DOWNTO 0);
BEGIN
- RING_0_TX(0) <= si_tx_arr(0);
- RING_0_TX(1) <= si_tx_arr(1);
- RING_0_TX(2) <= si_tx_arr(2);
- RING_0_TX(3) <= si_tx_arr(3);
- RING_0_TX(4) <= si_tx_arr(4);
- RING_0_TX(5) <= si_tx_arr(5);
- RING_0_TX(6) <= si_tx_arr(6);
- RING_0_TX(7) <= si_tx_arr(7);
- RING_0_TX(8) <= si_tx_arr(8);
- RING_0_TX(9) <= si_tx_arr(9);
- RING_0_TX(10) <= si_tx_arr(10);
- RING_0_TX(11) <= si_tx_arr(11);
-
- RING_1_TX(0) <= si_tx_arr(12);
- RING_1_TX(1) <= si_tx_arr(13);
- RING_1_TX(2) <= si_tx_arr(14);
- RING_1_TX(3) <= si_tx_arr(15);
- RING_1_TX(4) <= si_tx_arr(16);
- RING_1_TX(5) <= si_tx_arr(17);
- RING_1_TX(6) <= si_tx_arr(18);
- RING_1_TX(7) <= si_tx_arr(19);
- RING_1_TX(8) <= si_tx_arr(20);
- RING_1_TX(9) <= si_tx_arr(21);
- RING_1_TX(10) <= si_tx_arr(22);
- RING_1_TX(11) <= si_tx_arr(23);
-
+ gen_buses : FOR i IN 0 TO g_nof_ring_io-1 GENERATE
+ RING_TX(i) <= si_tx_2arr(i);
+ si_rx_2arr(i) <= RING_RX(i);
+ END GENERATE;
- si_rx_arr(0) <= RING_0_RX(0);
- si_rx_arr(1) <= RING_0_RX(1);
- si_rx_arr(2) <= RING_0_RX(2);
- si_rx_arr(3) <= RING_0_RX(3);
- si_rx_arr(4) <= RING_0_RX(4);
- si_rx_arr(5) <= RING_0_RX(5);
- si_rx_arr(6) <= RING_0_RX(6);
- si_rx_arr(7) <= RING_0_RX(7);
- si_rx_arr(8) <= RING_0_RX(8);
- si_rx_arr(9) <= RING_0_RX(9);
- si_rx_arr(10) <= RING_0_RX(10);
- si_rx_arr(11) <= RING_0_RX(11);
- si_rx_arr(12) <= RING_1_RX(0);
- si_rx_arr(13) <= RING_1_RX(1);
- si_rx_arr(14) <= RING_1_RX(2);
- si_rx_arr(15) <= RING_1_RX(3);
- si_rx_arr(16) <= RING_1_RX(4);
- si_rx_arr(17) <= RING_1_RX(5);
- si_rx_arr(18) <= RING_1_RX(6);
- si_rx_arr(19) <= RING_1_RX(7);
- si_rx_arr(20) <= RING_1_RX(8);
- si_rx_arr(21) <= RING_1_RX(9);
- si_rx_arr(22) <= RING_1_RX(10);
- si_rx_arr(23) <= RING_1_RX(11);
+ gen_wire_bus : FOR i IN 0 TO g_nof_ring_io-1 GENERATE
+ gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_ring.bus_w-1 GENERATE
+ si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_ring.bus_w + j);
+ serial_rx_arr(i*c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
- wire_signals : FOR i IN 0 TO c_unb2_board_tr_ring_hw_nof_lines-1 GENERATE
- si_tx_arr(i) <= serial_tx_arr(i);
- serial_rx_arr(i) <= si_rx_arr(i);
+ END GENERATE;
END GENERATE;
END;