diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd index 5f2acfa1818b97d86048ad16e9466ef55ab7b3cb..ebf97ff3beb2003d734d0971ab263091c5b39c5b 100644 --- a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd +++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd @@ -42,7 +42,8 @@ ENTITY dp_bsn_source_v2 IS GENERIC ( g_block_size : NATURAL := 256; g_nof_block_per_sync : NATURAL := 8; - g_bsn_w : NATURAL := 48 + g_bsn_w : NATURAL := 48; + g_offset_w : NATURAL := 4 ); PORT ( rst : IN STD_LOGIC; @@ -56,6 +57,8 @@ ENTITY dp_bsn_source_v2 IS init_bsn : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0'); nof_block_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_block_per_sync, c_word_w); + offset_bsn : IN STD_LOGIC_VECTOR(g_offset_w-1 DOWNTO 0) := (OTHERS=>'0'); + --offset_bsn : IN STD_LOGIC_VECTOR(g_offset_w-1 DOWNTO 0) := TO_UVEC(4, g_offset_w); src_out : OUT t_dp_sosi -- only uses sync, bsn[], valid, sop and eop ); @@ -67,7 +70,7 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS CONSTANT c_block_size_cnt_w : NATURAL := ceil_log2(g_block_size); CONSTANT c_block_cnt_zero : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS => '0'); - TYPE t_state_enum IS (s_init, s_dp_off, s_dp_on_sop, s_dp_on, s_dp_on_eop); + TYPE t_state_enum IS (s_init, s_dp_off, s_dp_on_sop, s_dp_on, s_dp_on_eop, s_bsn_offset); SIGNAL state : t_state_enum; SIGNAL nxt_state : t_state_enum; @@ -84,13 +87,16 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS SIGNAL nxt_dp_on_status : STD_LOGIC; SIGNAL i_dp_on_status : STD_LOGIC; + + SIGNAL nxt_offset_bsn_cnt : STD_LOGIC_VECTOR(g_offset_w-1 DOWNTO 0); + SIGNAL offset_bsn_cnt : STD_LOGIC_VECTOR(g_offset_w-1 DOWNTO 0); BEGIN src_out <= i_src_out; dp_on_status <= i_dp_on_status; - p_state : PROCESS(state, prev_state, dp_on, dp_on_pps, pps, block_size_cnt, block_cnt, nof_block_per_sync, init_bsn, i_src_out, i_dp_on_status) + p_state : PROCESS(state, prev_state, dp_on, dp_on_pps, pps, block_size_cnt, block_cnt, nof_block_per_sync, init_bsn, i_src_out, i_dp_on_status, offset_bsn_cnt) BEGIN nxt_state <= state; nxt_src_out <= i_src_out; @@ -145,13 +151,25 @@ BEGIN IF dp_on = '1' THEN IF dp_on_pps = '1' THEN IF pps = '1' THEN - nxt_state <= s_dp_on_sop; + IF UNSIGNED(offset_bsn) = 0 THEN + nxt_state <= s_dp_on_sop; + ELSE + nxt_offset_bsn_cnt <= (OTHERS=>'0'); + nxt_state <= s_bsn_offset; + END IF; END IF; ELSE - nxt_state <= s_dp_on_sop; + nxt_state <= s_dp_on_sop; END IF; END IF; + WHEN s_bsn_offset => + IF offset_bsn_cnt = offset_bsn THEN + nxt_state <= s_dp_on_sop; + ELSE + nxt_offset_bsn_cnt <= INCR_UVEC(offset_bsn_cnt, 1); + END IF; + WHEN OTHERS => -- s_init nxt_state <= s_dp_off; @@ -162,19 +180,21 @@ BEGIN p_clk : PROCESS(rst, clk) BEGIN IF rst='1' THEN - prev_state <= s_init; - state <= s_init; - i_src_out <= c_dp_sosi_rst; - block_cnt <= (OTHERS=>'0'); - block_size_cnt <= (OTHERS=>'0'); - i_dp_on_status <= '0'; + prev_state <= s_init; + state <= s_init; + i_src_out <= c_dp_sosi_rst; + block_cnt <= (OTHERS=>'0'); + block_size_cnt <= (OTHERS=>'0'); + i_dp_on_status <= '0'; + offset_bsn_cnt <= (OTHERS=>'0'); ELSIF rising_edge(clk) THEN - prev_state <= state; - state <= nxt_state; - i_src_out <= nxt_src_out; - block_cnt <= nxt_block_cnt; - block_size_cnt <= nxt_block_size_cnt; - i_dp_on_status <= nxt_dp_on_status; + prev_state <= state; + state <= nxt_state; + i_src_out <= nxt_src_out; + block_cnt <= nxt_block_cnt; + block_size_cnt <= nxt_block_size_cnt; + i_dp_on_status <= nxt_dp_on_status; + offset_bsn_cnt <= nxt_offset_bsn_cnt; END IF; END PROCESS;