diff --git a/boards/uniboard2b/designs/unb2b_jesd/tb/python/util_unb2_jesd.py b/boards/uniboard2b/designs/unb2b_jesd/tb/python/util_unb2.py
similarity index 97%
rename from boards/uniboard2b/designs/unb2b_jesd/tb/python/util_unb2_jesd.py
rename to boards/uniboard2b/designs/unb2b_jesd/tb/python/util_unb2.py
index 31bf0f5e6d659e3cc3e4b4db67d8085920084b02..abe144367310c25a5f34ce7fa8a3f0d69441aede 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/tb/python/util_unb2_jesd.py
+++ b/boards/uniboard2b/designs/unb2b_jesd/tb/python/util_unb2.py
@@ -20,9 +20,9 @@
 #
 ###############################################################################
 
-"""Test case for util_unb2_jesd
+"""Test case for unb2_jesd
 
-Quickly get started, try this: python util_unb2_jesd.py --unb 1 --fn 0 --seq JESD
+Quickly get started, try this: python util_unb2.py --unb 1 --fn 0 --seq JESD
 
 Usage:
 
@@ -37,6 +37,10 @@ Description:
    - write to wdi to force reload from bank 0
    - flash access: write image to bank 1
    - remote update: start image in bank 1
+   - read status MAC 10GbE
+   - read status PHY XAUI
+   - BG - DB tests for 1 port on 1 FPGA
+   - BG - DB tests for all ports on all FPGAs
    - link test between ports on the same FPGA (same XO)
    - link test between ports on different Uniboards (XO drift)
    - stable link after image restart
@@ -110,7 +114,7 @@ def test_JESD(tc,io,cmd):
             toggle+=1
             toggle&=1
             
-        plt.plot(samples[:100])
+        plt.plot(samples) #[:100])
         plt.show()