From 64cd857b9e83460ff385002846046cda06a95602 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 8 May 2018 06:54:03 +0000
Subject: [PATCH] Pass on g_note_is_ful of the FIFO. Use FALSE to increase
simulation speed somewhat and to avoid (many) notes.
---
libraries/base/dp/src/vhdl/dp_fifo_core.vhd | 2 ++
libraries/base/dp/src/vhdl/dp_fifo_sc.vhd | 2 ++
libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd | 5 ++++-
libraries/dsp/correlator/src/vhdl/correlator.vhd | 7 +++++--
4 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
index aaebaa7fe6..8c7be411f7 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
@@ -49,6 +49,7 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_core IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
+ g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_use_dual_clock : BOOLEAN := FALSE;
g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
@@ -171,6 +172,7 @@ BEGIN
u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
GENERIC MAP (
g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
g_use_lut => g_use_lut_sc,
g_dat_w => c_fifo_dat_w,
g_nof_words => g_fifo_size
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index caf411938d..a504b5ba0a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -32,6 +32,7 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_sc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
+ g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_use_lut : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
g_bsn_w : NATURAL := 1;
@@ -72,6 +73,7 @@ BEGIN
u_dp_fifo_core : ENTITY work.dp_fifo_core
GENERIC MAP (
g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
g_use_dual_clock => FALSE,
g_use_lut_sc => g_use_lut,
g_data_w => g_data_w,
diff --git a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
index d5b5448ebf..e7f27d49c9 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
@@ -41,7 +41,9 @@ ENTITY corr_accumulator IS
g_nof_inputs : NATURAL; -- Number of input streams
g_nof_channels : NATURAL; -- Number of running sums to keep per input stream
g_nof_channel_accs : NATURAL; -- Maximum number of timesamples to accumulate (per channel)
- g_data_w : NATURAL -- Complex input data width
+ g_data_w : NATURAL; -- Complex input data width
+ g_note_is_ful : BOOLEAN := FALSE -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ -- when FALSE no note reports, to speed up simulation and avoid many notes
);
PORT (
rst : IN STD_LOGIC;
@@ -123,6 +125,7 @@ BEGIN
gen_dp_fifo_sc : FOR i IN 0 TO g_nof_inputs-1 GENERATE
u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP (
+ g_note_is_ful => g_note_is_ful,
g_data_w => 2*c_acc_data_w,
g_use_ctrl => FALSE,
g_use_sync => sel_a_b(i=0, TRUE, FALSE), -- Pass on sync of stream 0.
diff --git a/libraries/dsp/correlator/src/vhdl/correlator.vhd b/libraries/dsp/correlator/src/vhdl/correlator.vhd
index f7b91f96a5..0344dcdb8f 100644
--- a/libraries/dsp/correlator/src/vhdl/correlator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/correlator.vhd
@@ -40,7 +40,9 @@ ENTITY correlator IS
g_nof_channels : NATURAL := 64; -- Number of (serial) channels per (parallel) input
g_integration_period : NATURAL := 0; -- Expressed as the number of samples per channel to accumulate
g_inter_channel_delay : NATURAL := 0; -- 0: Channels are output back to back. Set to >0 (cycles) for more constant output rate
- g_visibility_buffer_depth : NATURAL := 0 -- 0: internally set to c_nof_accumulators. Use more depth e.g. in sim with shorter integration period.
+ g_visibility_buffer_depth : NATURAL := 0; -- 0: internally set to c_nof_accumulators. Use more depth e.g. in sim with shorter integration period.
+ g_note_is_ful : BOOLEAN := FALSE -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ -- when FALSE no note reports, to speed up simulation and avoid many notes g_nof_inputs : NATURAL; -- Number of input streams
);
PORT (
rst : IN STD_LOGIC;
@@ -185,7 +187,8 @@ BEGIN
g_nof_inputs => c_nof_mults,
g_nof_channels => c_nof_accumulators,
g_nof_channel_accs => g_integration_period,
- g_data_w => 2*g_data_w -- Multiplier output data width
+ g_data_w => 2*g_data_w, -- Multiplier output data width
+ g_note_is_ful => g_note_is_ful
)
PORT MAP (
clk => clk,
--
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