From 64b008d083aef3d6f814d7d6e37f4a2f201326ca Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 14 Feb 2022 14:59:40 +0100
Subject: [PATCH] processed review comment

---
 libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 56b49e0e1c..124fdb1e14 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -253,8 +253,8 @@ BEGIN
 
       -- No need to transfer eop counter across clock domains for single clock
       ELSE 
-        wr_eop_busy <= '0'; -- To prevent inferred latch.
-        wr_eop_new  <= '0'; -- To prevent inferred latch.
+        wr_eop_busy <= '0'; -- Not used here, fix value to prevent inferred latch.
+        wr_eop_new  <= '0'; -- Not used here, fix value to prevent inferred latch.
         IF snk_in.eop = '1' THEN
           wr_eop_cnt <= 1; -- wr_eop_cnt can simply be set to 1 instead of counting as it is immidiatly processed due to having a single clock.
         ELSE
-- 
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