diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..278d7877b6a960fdd1b81fee952c6af70758f668
--- /dev/null
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/flash/asmi_parallel/generated/sim"
+
+vlib ./work/
+
+vmap ip_arria10_asmi_parallel_altera_asmi_parallel_140 ./work/
+
+vlog "$IP_DIR/../altera_asmi_parallel_140/sim/ip_arria10_asmi_parallel_altera_asmi_parallel_140_o6bwnxy.v" -work ip_arria10_asmi_parallel_altera_asmi_parallel_140
+vcom "$IP_DIR/ip_arria10_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh
new file mode 100644
index 0000000000000000000000000000000000000000..9207393b155cb2bc8cfe137147fe9ebdacc2bb8d
--- /dev/null
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_asmi_parallel.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..4498816f43a49e8591104a3caf25696a158a0d39
--- /dev/null
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_asmi_parallel
+hdl_library_clause_name = ip_arria10_asmi_parallel_altera_asmi_parallel_140
+hdl_lib_uses =
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
+
+quartus_qip_files =
+ generated/ip_arria10_asmi_parallel.qip
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/ip_arria10_asmi_parallel.qsys b/libraries/technology/ip_arria10/flash/asmi_parallel/ip_arria10_asmi_parallel.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..0a4e09369d7018b04fb07ed1ec0f7577dbc964d3
--- /dev/null
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/ip_arria10_asmi_parallel.qsys
@@ -0,0 +1,167 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element asmi_parallel_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clkin" internal="asmi_parallel_0.clkin" type="clock" dir="end">
+ <port name="clkin" internal="clkin" />
+ </interface>
+ <interface name="read" internal="asmi_parallel_0.read" type="conduit" dir="end">
+ <port name="read" internal="read" />
+ </interface>
+ <interface name="rden" internal="asmi_parallel_0.rden" type="conduit" dir="end">
+ <port name="rden" internal="rden" />
+ </interface>
+ <interface name="addr" internal="asmi_parallel_0.addr" type="conduit" dir="end">
+ <port name="addr" internal="addr" />
+ </interface>
+ <interface name="reset" internal="asmi_parallel_0.reset" type="reset" dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface name="sce" internal="asmi_parallel_0.sce" type="conduit" dir="end">
+ <port name="sce" internal="sce" />
+ </interface>
+ <interface
+ name="dataout"
+ internal="asmi_parallel_0.dataout"
+ type="conduit"
+ dir="end">
+ <port name="dataout" internal="dataout" />
+ </interface>
+ <interface name="busy" internal="asmi_parallel_0.busy" type="conduit" dir="end">
+ <port name="busy" internal="busy" />
+ </interface>
+ <interface
+ name="data_valid"
+ internal="asmi_parallel_0.data_valid"
+ type="conduit"
+ dir="end">
+ <port name="data_valid" internal="data_valid" />
+ </interface>
+ <interface name="wren" internal="asmi_parallel_0.wren" type="conduit" dir="end">
+ <port name="wren" internal="wren" />
+ </interface>
+ <interface
+ name="en4b_addr"
+ internal="asmi_parallel_0.en4b_addr"
+ type="conduit"
+ dir="end">
+ <port name="en4b_addr" internal="en4b_addr" />
+ </interface>
+ <interface
+ name="write"
+ internal="asmi_parallel_0.write"
+ type="conduit"
+ dir="end">
+ <port name="write" internal="write" />
+ </interface>
+ <interface
+ name="datain"
+ internal="asmi_parallel_0.datain"
+ type="conduit"
+ dir="end">
+ <port name="datain" internal="datain" />
+ </interface>
+ <interface
+ name="illegal_write"
+ internal="asmi_parallel_0.illegal_write"
+ type="conduit"
+ dir="end">
+ <port name="illegal_write" internal="illegal_write" />
+ </interface>
+ <interface
+ name="sector_erase"
+ internal="asmi_parallel_0.sector_erase"
+ type="conduit"
+ dir="end">
+ <port name="sector_erase" internal="sector_erase" />
+ </interface>
+ <interface
+ name="illegal_erase"
+ internal="asmi_parallel_0.illegal_erase"
+ type="conduit"
+ dir="end">
+ <port name="illegal_erase" internal="illegal_erase" />
+ </interface>
+ <interface name="ex4b_addr" internal="asmi_parallel_0.ex4b_addr" />
+ <interface name="die_erase" internal="asmi_parallel_0.die_erase" />
+ <interface
+ name="shift_bytes"
+ internal="asmi_parallel_0.shift_bytes"
+ type="conduit"
+ dir="end">
+ <port name="shift_bytes" internal="shift_bytes" />
+ </interface>
+ <module
+ kind="altera_asmi_parallel"
+ version="14.0"
+ enabled="1"
+ name="asmi_parallel_0"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="EPCS_TYPE" value="EPCQL1024" />
+ <parameter name="gui_read_sid" value="false" />
+ <parameter name="gui_read_rdid" value="false" />
+ <parameter name="gui_read_status" value="false" />
+ <parameter name="gui_read_address" value="false" />
+ <parameter name="gui_fast_read" value="false" />
+ <parameter name="DATA_WIDTH" value="QUAD" />
+ <parameter name="gui_read_dummyclk" value="false" />
+ <parameter name="gui_write" value="true" />
+ <parameter name="gui_wren" value="true" />
+ <parameter name="gui_single_write" value="false" />
+ <parameter name="gui_page_write" value="true" />
+ <parameter name="PAGE_SIZE" value="256" />
+ <parameter name="gui_use_eab" value="false" />
+ <parameter name="gui_bulk_erase" value="false" />
+ <parameter name="gui_die_erase" value="false" />
+ <parameter name="gui_sector_erase" value="true" />
+ <parameter name="gui_sector_protect" value="false" />
+ <parameter name="gui_ex4b_addr" value="false" />
+ <parameter name="gui_use_asmiblock" value="false" />
+ <parameter name="WRITE_DUMMY_CLK" value="0" />
+ <parameter name="ENABLE_SIM" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>
diff --git a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6bec6e3959df364ebb19ad2888bf8de6aca23f33
--- /dev/null
+++ b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/flash/remote_update/generated/sim"
+
+vlib ./work/
+
+vmap ip_arria10_remote_update_altera_remote_update_140 ./work/
+
+vlog "$IP_DIR/../altera_remote_update_140/sim/ip_arria10_remote_update_altera_remote_update_140_5hyen6i.v" -work ip_arria10_remote_update_altera_remote_update_140
+vcom "$IP_DIR/ip_arria10_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh
new file mode 100644
index 0000000000000000000000000000000000000000..3e96e70f4dabe166befab2a1415fe16439cc3bae
--- /dev/null
+++ b/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_remote_update.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..6e89b0066850acfe4f8d5456a9ef58daeb553b73
--- /dev/null
+++ b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_remote_update
+hdl_library_clause_name = ip_arria10_remote_update_altera_remote_update_140
+hdl_lib_uses =
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
+
+quartus_qip_files =
+ generated/ip_arria10_remote_update.qip
diff --git a/libraries/technology/ip_arria10/flash/remote_update/ip_arria10_remote_update.qsys b/libraries/technology/ip_arria10/flash/remote_update/ip_arria10_remote_update.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..7178ea0b43ff2a0299aced39def4ab2cc7fbc218
--- /dev/null
+++ b/libraries/technology/ip_arria10/flash/remote_update/ip_arria10_remote_update.qsys
@@ -0,0 +1,118 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element remote_update_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="read_param"
+ internal="remote_update_0.read_param"
+ type="conduit"
+ dir="end">
+ <port name="read_param" internal="read_param" />
+ </interface>
+ <interface
+ name="param"
+ internal="remote_update_0.param"
+ type="conduit"
+ dir="end">
+ <port name="param" internal="param" />
+ </interface>
+ <interface
+ name="reconfig"
+ internal="remote_update_0.reconfig"
+ type="conduit"
+ dir="end">
+ <port name="reconfig" internal="reconfig" />
+ </interface>
+ <interface
+ name="reset_timer"
+ internal="remote_update_0.reset_timer"
+ type="conduit"
+ dir="end">
+ <port name="reset_timer" internal="reset_timer" />
+ </interface>
+ <interface name="clock" internal="remote_update_0.clock" type="clock" dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface name="reset" internal="remote_update_0.reset" type="reset" dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface name="busy" internal="remote_update_0.busy" type="conduit" dir="end">
+ <port name="busy" internal="busy" />
+ </interface>
+ <interface
+ name="data_out"
+ internal="remote_update_0.data_out"
+ type="conduit"
+ dir="end">
+ <port name="data_out" internal="data_out" />
+ </interface>
+ <interface
+ name="write_param"
+ internal="remote_update_0.write_param"
+ type="conduit"
+ dir="end">
+ <port name="write_param" internal="write_param" />
+ </interface>
+ <interface
+ name="data_in"
+ internal="remote_update_0.data_in"
+ type="conduit"
+ dir="end">
+ <port name="data_in" internal="data_in" />
+ </interface>
+ <module
+ kind="altera_remote_update"
+ version="14.0"
+ enabled="1"
+ name="remote_update_0"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="operation_mode" value="REMOTE" />
+ <parameter name="GUI_config_device" value="EPCQ512" />
+ <parameter name="m_support_write_config_check" value="true" />
+ <parameter name="check_app_pof" value="false" />
+ <parameter name="AUTO_CLOCK_CLOCK_RATE" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>