diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
index 1642e1e0ebaf9d48882a8b6055963a5bae60cd9e..ec4f28671473375570d764b2d7df883483f142e3 100644
--- a/libraries/base/diag/diag.peripheral.yaml
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -31,22 +31,22 @@ peripherals:
1 = calc, uses WG buffer waveform to output sinus with ampl * sin(freq * t + phase
2 = repeat, outputs WG buffer waveform repeatedly
3 = single, outputs WG buffer waveform once"
- address_offset: 0x0
+ address_offset: 0 * MM_BUS_SIZE
bit_offset: 0
mm_width: 8
- - field_name: phase
field_description: "Phase of WG sinus, phase = int('phase in degrees' * 2**width / 360)."
- address_offset: 0x4
+ address_offset: 1 * MM_BUS_SIZE
bit_offset: 0
mm_width: 16
- - field_name: freq
field_description: "Frequency of WG sinus, freq = int('frequency in range 0 to 1' * f_adc * 2**width), where f_adc is sample frequency in Hz."
- address_offset: 0x8
+ address_offset: 2 * MM_BUS_SIZE
bit_offset: 0
mm_width: 31
- - field_name: ampl
field_description: "Amplitude of WG sinus, ampl = int('amplitude in range 0 to 2' * 2**(width-1), where amplitude > 1 causes clipping."
- address_offset: 0xC
+ address_offset: 3 * MM_BUS_SIZE
bit_offset: 0
mm_width: 17
# MM port for mms_diag_wg_wideband.vhd
@@ -59,7 +59,7 @@ peripherals:
- - field_name: data
field_description: "Waveform default is one sinus period (diag_sin_1024x18.hex)."
number_of_fields: 1024 # = 2**c_wg_buf_addr_w in node_adc_input_and_timing.vhd
- address_offset: 0x0
+ address_offset: 0 * MM_BUS_SIZE
mm_width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd
- peripheral_name: diag_data_buffer # pi_diag_data_buffer.py
@@ -80,11 +80,11 @@ peripherals:
fields:
- - field_name: sync_cnt
field_description: "Number of times the DB has been written."
- address_offset: 0x0
+ address_offset: 0 * MM_BUS_SIZE
access_mode: RO
- - field_name: word_cnt
field_description: "Number data words in the DB."
- address_offset: 0x4
+ address_offset: 1 * MM_BUS_SIZE
access_mode: RO
# MM port for mms_diag_data_buffer.vhd
- mm_port_name: RAM_DIAG_DB
@@ -96,7 +96,7 @@ peripherals:
- - field_name: data
field_description: ""
number_of_fields: g_nof_data
- address_offset: 0x0
+ address_offset: 0 * MM_BUS_SIZE
user_width: g_data_w
- peripheral_name: diag_block_gen # pi_diag_block_gen.py
@@ -111,29 +111,37 @@ peripherals:
- mm_port_name: REG_DIAG_BG
mm_port_type: REG
mm_port_span: 8 * MM_BUS_SIZE
- mm_port_description: "Block gen control."
+ mm_port_description: "Block generator control."
number_of_mm_ports: 1
fields:
- - field_name: enable
- address_offset: 0x0
+ field_description: "Starts the block generator."
+ address_offset: 0 * MM_BUS_SIZE
bit_offset: 0
mm_width: 1
- - field_name: enable_sync
- address_offset: 0x0
+ field_description: "Starts the block generator at the next sync pulse when enable is set to 1."
+ address_offset: 0 * MM_BUS_SIZE
bit_offset: 1
mm_width: 1
- - field_name: samples_per_packet
- address_offset: 0x4
+ field_description: "Number of samples per packet."
+ address_offset: 1 * MM_BUS_SIZE
- - field_name: blocks_per_sync
- address_offset: 0x8
+ field_description: "Number blocks per sync interval."
+ address_offset: 2 * MM_BUS_SIZE
- - field_name: gapsize
- address_offset: 0xc
+ field_description: "The gap size between blocks in clock cycles."
+ address_offset: 3 * MM_BUS_SIZE
- - field_name: mem_low_adrs
- address_offset: 0x10
+ field_description: "Start address of memory to use for block generator"
+ address_offset: 4 * MM_BUS_SIZE
- - field_name: mem_high_adrs
- address_offset: 0x14
+ field_description: "End address of memory to use for block generator."
+ address_offset: 5 * MM_BUS_SIZE
- - field_name: bsn_init
- address_offset: 0x18
+ field_description: "Initial BSN."
+ address_offset: 6 * MM_BUS_SIZE
user_width: 64
radix: uint64
@@ -141,13 +149,13 @@ peripherals:
- mm_port_name: RAM_DIAG_BG
mm_port_type: RAM
mm_port_span: ceil_pow2( 2**g_buf_addr_w * ceil_div(g_buf_dat_w, c_word_w)) * MM_BUS_SIZE
- mm_port_description: "Block gen buffer memory, contains the data patterns to be generated."
+ mm_port_description: "Block generator buffer memory, contains the data patterns to be generated."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
- field_description: ""
+ field_description: "Block generator buffer memory."
number_of_fields: 2**g_buf_addr_w
- address_offset: 0x0
+ address_offset: 0 * MM_BUS_SIZE
user_width: g_buf_dat_w
- peripheral_name: diag_tx_seq # pi_diag_tx_seq.py
@@ -165,15 +173,32 @@ peripherals:
number_of_mm_ports: sel_a_b(g_mm_broadcast, 1, g_nof_streams)
fields:
- - field_name: control
- address_offset: 0x0
+ field_description: |
+ "Control register containing diag_dc = [2], diag_sel = [1], diag_en = [0].
+ diag_en
+ '0' = init and disable output sequence
+ '1' = enable output sequence
+ diag_sel
+ '0' = generate PSRG data
+ '1' = generate CNTR data
+ diag_dc
+ '0' = Output sequence data (as selected by diag_sel)
+ '1' = Output constant data (value as set by diag_init)"
+ address_offset: 0 * MM_BUS_SIZE
mm_width: 3
- - field_name: init
- address_offset: 0x4
+ field_description: "Initial data value."
+ address_offset: 1 * MM_BUS_SIZE
- - field_name: tx_cnt
- address_offset: 0x8
+ field_description: |
+ "Counts the number of valid output data that was transmitted on stream 0
+ since diag_en went active. An incrementing tx_cnt shows that data is
+ being transmitted."
+ address_offset: 2 * MM_BUS_SIZE
access_mode: RO
- - field_name: modulo
- address_offset: 0xc
+ field_description: "A modulo can be used with CNTR data which results in a sequence with values of (cnt MOD modulo)"
+ address_offset: 3 * MM_BUS_SIZE
- peripheral_name: diag_rx_seq # pi_diag_rx_seq.py
peripheral_description: "RX test sequence"
@@ -189,25 +214,52 @@ peripherals:
number_of_mm_ports: g_nof_streams
fields:
- - field_name: control
- address_offset: 0x0
+ field_description: |
+ "Control register containing diag_sel = [1], diag_en = [0].
+ diag_en
+ '0' = stop and reset input sequence verification
+ '1' = enable input sequence verification
+ diag_sel
+ '0' = verify PSRG data
+ '1' = verify CNTR data"
+ address_offset: 0 * MM_BUS_SIZE
mm_width: 2
- - field_name: result
- address_offset: 0x4
+ field_description: |
+ "result register containing res_val_n = [1], res_ok_n = [0].
+ res_val_n
+ '0' = No valid data is being received.
+ '1' = At least two valid data have been received.
+ res_ok_n
+ '0' = All data that has been received so far is correct.
+ '1' = At least 1 data word was received with errors"
+ address_offset: 1 * MM_BUS_SIZE
access_mode: RO
mm_width: 2
- - field_name: rx_cnt
- address_offset: 0x8
+ field_description: |
+ "the number of valid input data that was received since diag_en
+ went active. An incrementing rx_cnt shows that data is being received."
+ address_offset: 2 * MM_BUS_SIZE
access_mode: RO
- - field_name: rx_sample
- address_offset: 0xc
+ field_description: |
+ "The rx_sample keeps the last valid in_dat value. When diag_en='0' it is
+ reset to 0. Reading rx_sample via MM gives an impression of the valid
+ in_dat activity."
+ address_offset: 3 * MM_BUS_SIZE
access_mode: RO
- - field_name: step_0
- address_offset: 0x10
+ field_description: "step_0 = diag_steps_arr[0] which defines the allowed COUNTER increment values"
+ address_offset: 4 * MM_BUS_SIZE
- - field_name: step_1
- address_offset: 0x14
+ field_description: "step_1 = diag_steps_arr[1] which defines the allowed COUNTER increment values"
+ address_offset: 5 * MM_BUS_SIZE
- - field_name: step_2
- address_offset: 0x18
+ field_description: "step_2 = diag_steps_arr[2] which defines the allowed COUNTER increment values"
+ address_offset: 6 * MM_BUS_SIZE
- - field_name: step_3
- address_offset: 0x1c
+ field_description: "step_3 = diag_steps_arr[3] which defines the allowed COUNTER increment values"
+ address_offset: 7 * MM_BUS_SIZE
diff --git a/libraries/base/util/util.peripheral.yaml b/libraries/base/util/util.peripheral.yaml
index 82287d4419242d27790a9cc5a55f3d3639df047f..af6518786578ee1d07ebe520bd7c52c930341cf8 100644
--- a/libraries/base/util/util.peripheral.yaml
+++ b/libraries/base/util/util.peripheral.yaml
@@ -4,20 +4,26 @@ schema_type: peripheral
hdl_library_name: util
hdl_library_description: "Util Heater."
-
peripherals:
- peripheral_name: heater # pi_heater.py
peripheral_description: "Heater component, see util_heater.vhd"
+ parameters:
+ - { name: c_nof_mac4_max, value: 800 }
+ - { name: c_reg_nof_words, value: c_util_heater_nof_mac4_max // 32 } # = 25
mm_ports:
# MM port for util_heater.vhd
- mm_port_name: REG_HEATER
mm_port_type: REG
- mm_port_span: 32 * MM_BUS_SIZE
+ mm_port_span: ceil_pow2(c_reg_nof_words) * MM_BUS_SIZE
mm_port_description: "Heater control."
fields:
- - field_name: enable
- field_description: "Enable"
- number_of_fields: 25
+ field_description: |
+ "The heater elements can be enabled or disabled via this MM register.
+ Each heater element consists of a MAC4. A MAC4 uses 4 18x18 multipliers.
+ The MM register allows enabling 0, 1, more or all MAC4 under SW control.
+ In this way it is possible to vary the power consumption during run time."
+ number_of_fields: c_reg_nof_words
address_offset: 0x0
diff --git a/libraries/io/ddr/ddr.peripheral.yaml b/libraries/io/ddr/ddr.peripheral.yaml
index 779cc9e24106252fadd598ea973ff75024bb76cb..b2cbd21a659e3682d4ca23512caee423de5bbb86 100644
--- a/libraries/io/ddr/ddr.peripheral.yaml
+++ b/libraries/io/ddr/ddr.peripheral.yaml
@@ -16,26 +16,50 @@ peripherals:
mm_port_description: "DDR controller registers."
number_of_mm_ports: 1
fields:
- - - field_name: burstbegin
- address_offset: 0x0
+ - - field_name: reg_io_ddr
+ field_description: |
+ "IO DDR status bits concatenated:
+ ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail & ctlr_tech_miso.cal_ok
+ ctlr_rst_out_i & ctlr_wr_flush_en & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done"
+ address_offset: 0 * MM_BUS_SIZE
+ access_mode: RO
+ - - field_name: reg_rd_fifo_used
+ field_description: "Read FIFO fill level."
+ address_offset: 1 * MM_BUS_SIZE
+ access_mode: RO
+ - - field_name: reg_wr_fifo_used
+ field_description: "Write FIFO fill level."
+ address_offset: 2 * MM_BUS_SIZE
+ access_mode: RO
+ - - field_name: reg_fifo_full
+ field_description: "Read FIFO full bit & Write FIFO full bit"
+ address_offset: 3 * MM_BUS_SIZE
+ access_mode: RO
+ - - field_name: reg_burstbegin
+ field_description: "Start write or read access to DDR when reg_burstbegin = 1."
+ address_offset: 8 * MM_BUS_SIZE
access_mode: WO
- mm_width: 1
- - - field_name: wr_not_rd
- address_offset: 0x4
+ - - field_name: reg_wr_not_rd
+ field_description: "Set read / write mode. reg_wr_not_rd = 1 = write mode, reg_wr_not_rd = 0 = read mode."
+ address_offset: 9 * MM_BUS_SIZE
access_mode: WO
- mm_width: 1
- - - field_name: done
- address_offset: 0x8
+ - - field_name: reg_done
+ field_description: "reg_done = 1 when memory access is finished."
+ address_offset: 10 * MM_BUS_SIZE
access_mode: RO
- mm_width: 1
- - - field_name: address
- address_offset: 0x14
+ - - field_name: reg_address
+ field_description: "Start address for memory access."
+ address_offset: 13 * MM_BUS_SIZE
access_mode: WO
- - - field_name: burstsize
- address_offset: 0x18
+ - - field_name: reg_burstsize
+ field_description: "Access size for memory access"
+ address_offset: 14 * MM_BUS_SIZE
access_mode: WO
- - - field_name: flush
- address_offset: 0x1c
- mm_width: 1
+ - - field_name: reg_flush
+ field_description: |
+ "Flush the write FIFO
+ The user input to the write FIFO sohuld be off. Internally the method waits sufficient us to
+ ensure that the write FIFO is read empty."
+ address_offset: 15 * MM_BUS_SIZE
diff --git a/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml b/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml
index 7615739f1d20fd13b1bfff5cb982e1eaae8ffcac..215c802fa4674c5f8f301d6f47eef4373ddbb760 100644
--- a/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml
+++ b/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml
@@ -2,7 +2,7 @@ schema_name: args
schema_version: 1.0
schema_type: peripheral
-hdl_library_name: tr_10GbE
+hdl_library_name: tr_10GbE # copy of nw_10GbE.
hdl_library_description: "Network peripherals for 10GbE."
peripherals: