From 63de720a808081625ea64bff56269c07d8a603f2 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Fri, 5 Jun 2015 13:20:51 +0000
Subject: [PATCH] qsys additions for all perepherals (address widths to be
specified accurately, now same as in unb1_test)
---
.../unb2_test/quartus/qsys_unb2_test.qsys | 1717 +++++++++++++++--
.../unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd | 579 +++---
2 files changed, 1883 insertions(+), 413 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
index 62428f26f0..1e8ae179e9 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
+++ b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
@@ -29,7 +29,7 @@
{
datum baseAddress
{
- value = "16384";
+ value = "40960";
type = "String";
}
}
@@ -37,11 +37,43 @@
{
datum baseAddress
{
- value = "896";
+ value = "53312";
type = "String";
}
}
element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "32768";
+ type = "String";
+ }
+ }
+ element avs_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ }
+ element avs_eth_1.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "36864";
+ type = "String";
+ }
+ }
+ element avs_eth_1.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "53248";
+ type = "String";
+ }
+ }
+ element avs_eth_1.mms_tse
{
datum baseAddress
{
@@ -85,7 +117,7 @@
{
datum baseAddress
{
- value = "1360";
+ value = "53848";
type = "String";
}
}
@@ -122,7 +154,7 @@
{
datum _sortIndex
{
- value = "10";
+ value = "11";
type = "int";
}
}
@@ -130,7 +162,7 @@
{
datum baseAddress
{
- value = "1352";
+ value = "53840";
type = "String";
}
}
@@ -138,7 +170,7 @@
{
datum _sortIndex
{
- value = "9";
+ value = "10";
type = "int";
}
}
@@ -162,7 +194,7 @@
{
datum baseAddress
{
- value = "1280";
+ value = "53776";
type = "String";
}
}
@@ -174,11 +206,27 @@
type = "String";
}
}
+ element ram_diag_bg_10gbe
+ {
+ datum _sortIndex
+ {
+ value = "41";
+ type = "int";
+ }
+ }
+ element ram_diag_bg_10gbe.mem
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "String";
+ }
+ }
element ram_diag_bg_1gbe
{
datum _sortIndex
{
- value = "32";
+ value = "40";
type = "int";
}
}
@@ -186,7 +234,7 @@
{
datum baseAddress
{
- value = "24576";
+ value = "49152";
type = "String";
}
}
@@ -194,7 +242,7 @@
{
datum _sortIndex
{
- value = "33";
+ value = "42";
type = "int";
}
}
@@ -202,7 +250,23 @@
{
datum baseAddress
{
- value = "20480";
+ value = "45056";
+ type = "String";
+ }
+ }
+ element ram_diag_data_buffer_10gbe
+ {
+ datum _sortIndex
+ {
+ value = "35";
+ type = "int";
+ }
+ }
+ element ram_diag_data_buffer_10gbe.mem
+ {
+ datum baseAddress
+ {
+ value = "65536";
type = "String";
}
}
@@ -210,7 +274,7 @@
{
datum _sortIndex
{
- value = "28";
+ value = "34";
type = "int";
}
}
@@ -218,7 +282,7 @@
{
datum baseAddress
{
- value = "327680";
+ value = "393216";
type = "String";
}
}
@@ -226,7 +290,7 @@
{
datum _sortIndex
{
- value = "29";
+ value = "36";
type = "int";
}
}
@@ -234,7 +298,7 @@
{
datum baseAddress
{
- value = "262144";
+ value = "327680";
type = "String";
}
}
@@ -242,7 +306,7 @@
{
datum _sortIndex
{
- value = "34";
+ value = "43";
type = "int";
}
}
@@ -250,7 +314,23 @@
{
datum baseAddress
{
- value = "65536";
+ value = "262144";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_10GbE
+ {
+ datum _sortIndex
+ {
+ value = "23";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_10GbE.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
type = "String";
}
}
@@ -258,7 +338,7 @@
{
datum _sortIndex
{
- value = "21";
+ value = "22";
type = "int";
}
}
@@ -266,7 +346,7 @@
{
datum baseAddress
{
- value = "1024";
+ value = "53440";
type = "String";
}
}
@@ -274,7 +354,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "24";
type = "int";
}
}
@@ -282,7 +362,23 @@
{
datum baseAddress
{
- value = "960";
+ value = "53376";
+ type = "String";
+ }
+ }
+ element reg_diag_bg_10gbe
+ {
+ datum _sortIndex
+ {
+ value = "38";
+ type = "int";
+ }
+ }
+ element reg_diag_bg_10gbe.mem
+ {
+ datum baseAddress
+ {
+ value = "53536";
type = "String";
}
}
@@ -290,7 +386,7 @@
{
datum _sortIndex
{
- value = "30";
+ value = "37";
type = "int";
}
}
@@ -298,7 +394,7 @@
{
datum baseAddress
{
- value = "1152";
+ value = "53632";
type = "String";
}
}
@@ -306,7 +402,7 @@
{
datum _sortIndex
{
- value = "31";
+ value = "39";
type = "int";
}
}
@@ -314,7 +410,23 @@
{
datum baseAddress
{
- value = "1120";
+ value = "53600";
+ type = "String";
+ }
+ }
+ element reg_diag_data_buffer_10gbe
+ {
+ datum _sortIndex
+ {
+ value = "32";
+ type = "int";
+ }
+ }
+ element reg_diag_data_buffer_10gbe.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
type = "String";
}
}
@@ -322,7 +434,7 @@
{
datum _sortIndex
{
- value = "26";
+ value = "31";
type = "int";
}
}
@@ -330,7 +442,7 @@
{
datum baseAddress
{
- value = "768";
+ value = "13184";
type = "String";
}
}
@@ -338,11 +450,27 @@
{
datum _sortIndex
{
- value = "27";
+ value = "33";
type = "int";
}
}
element reg_diag_data_buffer_ddr.mem
+ {
+ datum baseAddress
+ {
+ value = "13056";
+ type = "String";
+ }
+ }
+ element reg_diag_rx_seq_10gbe
+ {
+ datum _sortIndex
+ {
+ value = "48";
+ type = "int";
+ }
+ }
+ element reg_diag_rx_seq_10gbe.mem
{
datum baseAddress
{
@@ -350,292 +478,420 @@
type = "String";
}
}
- element reg_dp_offload_rx_1gbe_hdr_dat
+ element reg_diag_rx_seq_1gbe
{
datum _sortIndex
{
- value = "25";
+ value = "46";
type = "int";
}
}
- element reg_dp_offload_rx_1gbe_hdr_dat.mem
+ element reg_diag_rx_seq_1gbe.mem
{
datum baseAddress
{
- value = "256";
+ value = "53504";
type = "String";
}
}
- element reg_dp_offload_tx_1gbe
+ element reg_diag_rx_seq_ddr
{
datum _sortIndex
{
- value = "23";
+ value = "50";
type = "int";
}
}
- element reg_dp_offload_tx_1gbe.mem
+ element reg_diag_rx_seq_ddr.mem
{
datum baseAddress
{
- value = "1312";
+ value = "12320";
type = "String";
}
}
- element reg_dp_offload_tx_1gbe_hdr_dat
+ element reg_diag_tx_seq_10gbe
{
datum _sortIndex
{
- value = "24";
+ value = "47";
type = "int";
}
}
- element reg_dp_offload_tx_1gbe_hdr_dat.mem
+ element reg_diag_tx_seq_10gbe.mem
{
datum baseAddress
{
- value = "512";
+ value = "12352";
type = "String";
}
}
- element reg_dpmm_ctrl
+ element reg_diag_tx_seq_1gbe
{
datum _sortIndex
{
- value = "14";
+ value = "45";
type = "int";
}
}
- element reg_dpmm_ctrl.mem
+ element reg_diag_tx_seq_1gbe.mem
{
datum baseAddress
{
- value = "1344";
+ value = "53760";
type = "String";
}
}
- element reg_dpmm_data
+ element reg_diag_tx_seq_ddr
{
datum _sortIndex
{
- value = "15";
+ value = "49";
type = "int";
}
}
- element reg_dpmm_data.mem
+ element reg_diag_tx_seq_ddr.mem
{
datum baseAddress
{
- value = "1336";
+ value = "12304";
type = "String";
}
}
- element reg_epcs
+ element reg_dp_offload_rx_10gbe_hdr_dat
{
datum _sortIndex
{
- value = "13";
+ value = "30";
type = "int";
}
}
- element reg_epcs.mem
+ element reg_dp_offload_rx_10gbe_hdr_dat.mem
{
datum baseAddress
{
- value = "1184";
+ value = "1024";
type = "String";
}
}
- element reg_io_ddr
+ element reg_dp_offload_rx_1gbe_hdr_dat
{
datum _sortIndex
{
- value = "35";
+ value = "29";
type = "int";
}
}
- element reg_io_ddr.mem
+ element reg_dp_offload_rx_1gbe_hdr_dat.mem
{
datum baseAddress
{
- value = "1296";
+ value = "12544";
type = "String";
}
}
- element reg_mmdp_ctrl
+ element reg_dp_offload_tx_10gbe
{
datum _sortIndex
{
- value = "16";
+ value = "26";
type = "int";
}
}
- element reg_mmdp_ctrl.mem
+ element reg_dp_offload_tx_10gbe.mem
{
datum baseAddress
{
- value = "1328";
+ value = "512";
type = "String";
}
}
- element reg_mmdp_data
+ element reg_dp_offload_tx_10gbe_hdr_dat
{
datum _sortIndex
{
- value = "17";
+ value = "28";
type = "int";
}
}
- element reg_mmdp_data.mem
+ element reg_dp_offload_tx_10gbe_hdr_dat.mem
{
datum baseAddress
{
- value = "1320";
+ value = "13312";
type = "String";
}
}
- element reg_remu
+ element reg_dp_offload_tx_1gbe
{
datum _sortIndex
{
- value = "12";
+ value = "25";
type = "int";
}
}
- element reg_remu.mem
+ element reg_dp_offload_tx_1gbe.mem
{
datum baseAddress
{
- value = "1216";
+ value = "12296";
type = "String";
}
}
- element reg_tr_10GbE_back0
+ element reg_dp_offload_tx_1gbe_hdr_dat
{
datum _sortIndex
{
- value = "19";
+ value = "27";
type = "int";
}
}
- element reg_tr_10GbE_back0.mem
+ element reg_dp_offload_tx_1gbe_hdr_dat.mem
{
datum baseAddress
{
- value = "4194304";
+ value = "12800";
type = "String";
}
}
- element reg_tr_10GbE_back1
+ element reg_dpmm_ctrl
{
datum _sortIndex
{
- value = "20";
+ value = "15";
type = "int";
}
}
- element reg_tr_10GbE_back1.mem
+ element reg_dpmm_ctrl.mem
{
datum baseAddress
{
- value = "1048576";
+ value = "53832";
type = "String";
}
}
- element reg_tr_10GbE_qsfp_ring
+ element reg_dpmm_data
{
datum _sortIndex
{
- value = "18";
+ value = "16";
type = "int";
}
}
- element reg_tr_10GbE_qsfp_ring.mem
+ element reg_dpmm_data.mem
{
datum baseAddress
{
- value = "2097152";
+ value = "53824";
type = "String";
}
}
- element reg_unb_sens
+ element reg_epcs
{
datum _sortIndex
{
- value = "7";
+ value = "14";
type = "int";
}
}
- element reg_unb_sens.mem
+ element reg_epcs.mem
{
datum baseAddress
{
- value = "1248";
+ value = "53664";
type = "String";
}
}
- element reg_wdi
+ element reg_io_ddr
{
datum _sortIndex
{
- value = "11";
+ value = "44";
type = "int";
}
}
- element reg_wdi.mem
+ element reg_io_ddr.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "53792";
+ type = "String";
+ }
+ }
+ element reg_mmdp_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
}
+ }
+ element reg_mmdp_ctrl.mem
+ {
datum baseAddress
{
- value = "12288";
+ value = "53816";
type = "String";
}
}
- element rom_system_info
+ element reg_mmdp_data
{
datum _sortIndex
{
- value = "8";
+ value = "18";
type = "int";
}
}
- element rom_system_info.mem
+ element reg_mmdp_data.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "53808";
+ type = "String";
+ }
+ }
+ element reg_remu
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
}
+ }
+ element reg_remu.mem
+ {
datum baseAddress
{
- value = "4096";
+ value = "53696";
type = "String";
}
}
- element timer_0
+ element reg_tr_10GbE_back0
{
datum _sortIndex
{
- value = "5";
+ value = "20";
type = "int";
}
}
- element timer_0.s1
+ element reg_tr_10GbE_back0.mem
{
datum baseAddress
{
- value = "1088";
+ value = "4194304";
type = "String";
}
}
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SGES" />
+ element reg_tr_10GbE_back1
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ }
+ element reg_tr_10GbE_back1.mem
+ {
+ datum baseAddress
+ {
+ value = "1048576";
+ type = "String";
+ }
+ }
+ element reg_tr_10GbE_qsfp_ring
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ }
+ element reg_tr_10GbE_qsfp_ring.mem
+ {
+ datum baseAddress
+ {
+ value = "2097152";
+ type = "String";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "53728";
+ type = "String";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "String";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "String";
+ }
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "53568";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
@@ -748,6 +1004,101 @@
internal="avs_eth_0.tse_writedata"
type="conduit"
dir="end" />
+ <interface
+ name="avs_eth_1_clk"
+ internal="avs_eth_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_irq"
+ internal="avs_eth_1.irq"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_ram_address"
+ internal="avs_eth_1.ram_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_ram_read"
+ internal="avs_eth_1.ram_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_ram_readdata"
+ internal="avs_eth_1.ram_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_ram_write"
+ internal="avs_eth_1.ram_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_ram_writedata"
+ internal="avs_eth_1.ram_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_reg_address"
+ internal="avs_eth_1.reg_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_reg_read"
+ internal="avs_eth_1.reg_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_reg_readdata"
+ internal="avs_eth_1.reg_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_reg_write"
+ internal="avs_eth_1.reg_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_reg_writedata"
+ internal="avs_eth_1.reg_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_reset"
+ internal="avs_eth_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_tse_address"
+ internal="avs_eth_1.tse_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_tse_read"
+ internal="avs_eth_1.tse_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_tse_readdata"
+ internal="avs_eth_1.tse_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_tse_waitrequest"
+ internal="avs_eth_1.tse_waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_tse_write"
+ internal="avs_eth_1.tse_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_1_tse_writedata"
+ internal="avs_eth_1.tse_writedata"
+ type="conduit"
+ dir="end" />
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface
name="pio_pps_address"
@@ -816,6 +1167,41 @@
internal="pio_wdi.external_connection"
type="conduit"
dir="end" />
+ <interface
+ name="ram_diag_bg_10gbe_address"
+ internal="ram_diag_bg_10gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_10gbe_clk"
+ internal="ram_diag_bg_10gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_10gbe_read"
+ internal="ram_diag_bg_10gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_10gbe_readdata"
+ internal="ram_diag_bg_10gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_10gbe_reset"
+ internal="ram_diag_bg_10gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_10gbe_write"
+ internal="ram_diag_bg_10gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_10gbe_writedata"
+ internal="ram_diag_bg_10gbe.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="ram_diag_bg_1gbe_address"
internal="ram_diag_bg_1gbe.address"
@@ -886,6 +1272,41 @@
internal="ram_diag_bg_ddr.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_address"
+ internal="ram_diag_data_buffer_10gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_clk"
+ internal="ram_diag_data_buffer_10gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_read"
+ internal="ram_diag_data_buffer_10gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_readdata"
+ internal="ram_diag_data_buffer_10gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_reset"
+ internal="ram_diag_data_buffer_10gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_write"
+ internal="ram_diag_data_buffer_10gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_writedata"
+ internal="ram_diag_data_buffer_10gbe.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="ram_diag_data_buffer_1gbe_address"
internal="ram_diag_data_buffer_1gbe.address"
@@ -991,6 +1412,41 @@
internal="ram_ss_ss_wide.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_10gbe_address"
+ internal="reg_bsn_monitor_10GbE.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_10gbe_clk"
+ internal="reg_bsn_monitor_10GbE.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_10gbe_read"
+ internal="reg_bsn_monitor_10GbE.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_10gbe_readdata"
+ internal="reg_bsn_monitor_10GbE.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_10gbe_reset"
+ internal="reg_bsn_monitor_10GbE.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_10gbe_write"
+ internal="reg_bsn_monitor_10GbE.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_10gbe_writedata"
+ internal="reg_bsn_monitor_10GbE.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_monitor_1gbe_address"
internal="reg_bsn_monitor_1GbE.address"
@@ -1061,6 +1517,41 @@
internal="reg_bsn_monitor_ddr.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_diag_bg_10gbe_address"
+ internal="reg_diag_bg_10gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_10gbe_clk"
+ internal="reg_diag_bg_10gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_10gbe_read"
+ internal="reg_diag_bg_10gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_10gbe_readdata"
+ internal="reg_diag_bg_10gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_10gbe_reset"
+ internal="reg_diag_bg_10gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_10gbe_write"
+ internal="reg_diag_bg_10gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_10gbe_writedata"
+ internal="reg_diag_bg_10gbe.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_diag_bg_1gbe_address"
internal="reg_diag_bg_1gbe.address"
@@ -1131,6 +1622,41 @@
internal="reg_diag_bg_ddr.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_diag_data_buffer_10gbe_address"
+ internal="reg_diag_data_buffer_10gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_10gbe_clk"
+ internal="reg_diag_data_buffer_10gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_10gbe_read"
+ internal="reg_diag_data_buffer_10gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_10gbe_readdata"
+ internal="reg_diag_data_buffer_10gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_10gbe_reset"
+ internal="reg_diag_data_buffer_10gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_10gbe_write"
+ internal="reg_diag_data_buffer_10gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_10gbe_writedata"
+ internal="reg_diag_data_buffer_10gbe.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_diag_data_buffer_1gbe_address"
internal="reg_diag_data_buffer_1gbe.address"
@@ -1201,6 +1727,251 @@
internal="reg_diag_data_buffer_ddr.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_address"
+ internal="reg_diag_rx_seq_10gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_clk"
+ internal="reg_diag_rx_seq_10gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_read"
+ internal="reg_diag_rx_seq_10gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_readdata"
+ internal="reg_diag_rx_seq_10gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_reset"
+ internal="reg_diag_rx_seq_10gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_write"
+ internal="reg_diag_rx_seq_10gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_writedata"
+ internal="reg_diag_rx_seq_10gbe.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_address"
+ internal="reg_diag_rx_seq_1gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_clk"
+ internal="reg_diag_rx_seq_1gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_read"
+ internal="reg_diag_rx_seq_1gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_readdata"
+ internal="reg_diag_rx_seq_1gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_reset"
+ internal="reg_diag_rx_seq_1gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_write"
+ internal="reg_diag_rx_seq_1gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_writedata"
+ internal="reg_diag_rx_seq_1gbe.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_address"
+ internal="reg_diag_rx_seq_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_clk"
+ internal="reg_diag_rx_seq_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_read"
+ internal="reg_diag_rx_seq_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_readdata"
+ internal="reg_diag_rx_seq_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_reset"
+ internal="reg_diag_rx_seq_ddr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_write"
+ internal="reg_diag_rx_seq_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_writedata"
+ internal="reg_diag_rx_seq_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_address"
+ internal="reg_diag_tx_seq_10gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_clk"
+ internal="reg_diag_tx_seq_10gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_read"
+ internal="reg_diag_tx_seq_10gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_readdata"
+ internal="reg_diag_tx_seq_10gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_reset"
+ internal="reg_diag_tx_seq_10gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_write"
+ internal="reg_diag_tx_seq_10gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_writedata"
+ internal="reg_diag_tx_seq_10gbe.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_address"
+ internal="reg_diag_tx_seq_1gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_clk"
+ internal="reg_diag_tx_seq_1gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_read"
+ internal="reg_diag_tx_seq_1gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_readdata"
+ internal="reg_diag_tx_seq_1gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_reset"
+ internal="reg_diag_tx_seq_1gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_write"
+ internal="reg_diag_tx_seq_1gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_writedata"
+ internal="reg_diag_tx_seq_1gbe.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_address"
+ internal="reg_diag_tx_seq_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_clk"
+ internal="reg_diag_tx_seq_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_read"
+ internal="reg_diag_tx_seq_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_readdata"
+ internal="reg_diag_tx_seq_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_reset"
+ internal="reg_diag_tx_seq_ddr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_write"
+ internal="reg_diag_tx_seq_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_writedata"
+ internal="reg_diag_tx_seq_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_10gbe_hdr_dat_address"
+ internal="reg_dp_offload_rx_10gbe_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_10gbe_hdr_dat_clk"
+ internal="reg_dp_offload_rx_10gbe_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_10gbe_hdr_dat_read"
+ internal="reg_dp_offload_rx_10gbe_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_10gbe_hdr_dat_readdata"
+ internal="reg_dp_offload_rx_10gbe_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_10gbe_hdr_dat_reset"
+ internal="reg_dp_offload_rx_10gbe_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_10gbe_hdr_dat_write"
+ internal="reg_dp_offload_rx_10gbe_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_10gbe_hdr_dat_writedata"
+ internal="reg_dp_offload_rx_10gbe_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dp_offload_rx_1gbe_hdr_dat_address"
internal="reg_dp_offload_rx_1gbe_hdr_dat.address"
@@ -1217,23 +1988,93 @@
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_readdata"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.readdata"
+ name="reg_dp_offload_rx_1gbe_hdr_dat_readdata"
+ internal="reg_dp_offload_rx_1gbe_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_reset"
+ internal="reg_dp_offload_rx_1gbe_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_write"
+ internal="reg_dp_offload_rx_1gbe_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_writedata"
+ internal="reg_dp_offload_rx_1gbe_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_address"
+ internal="reg_dp_offload_tx_10gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_clk"
+ internal="reg_dp_offload_tx_10gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_hdr_dat_address"
+ internal="reg_dp_offload_tx_10gbe_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_hdr_dat_clk"
+ internal="reg_dp_offload_tx_10gbe_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_hdr_dat_read"
+ internal="reg_dp_offload_tx_10gbe_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_hdr_dat_readdata"
+ internal="reg_dp_offload_tx_10gbe_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_hdr_dat_reset"
+ internal="reg_dp_offload_tx_10gbe_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_hdr_dat_write"
+ internal="reg_dp_offload_tx_10gbe_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_hdr_dat_writedata"
+ internal="reg_dp_offload_tx_10gbe_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_read"
+ internal="reg_dp_offload_tx_10gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_10gbe_readdata"
+ internal="reg_dp_offload_tx_10gbe.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_reset"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.reset"
+ name="reg_dp_offload_tx_10gbe_reset"
+ internal="reg_dp_offload_tx_10gbe.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_write"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.write"
+ name="reg_dp_offload_tx_10gbe_write"
+ internal="reg_dp_offload_tx_10gbe.write"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_writedata"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.writedata"
+ name="reg_dp_offload_tx_10gbe_writedata"
+ internal="reg_dp_offload_tx_10gbe.writedata"
type="conduit"
dir="end" />
<interface
@@ -1762,6 +2603,7 @@
type="conduit"
dir="end" />
<module name="avs_eth_0" kind="avs2_eth_coe" version="1.0" enabled="1" />
+ <module name="avs_eth_1" kind="avs2_eth_coe" version="1.0" enabled="1" />
<module name="clk_0" kind="clock_source" version="15.0" enabled="1">
<parameter name="clockFrequency" value="125000000" />
<parameter name="clockFrequencyKnown" value="true" />
@@ -1788,7 +2630,7 @@
<parameter name="dataAddrWidth" value="23" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_rx_1gbe_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_1gbe_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x300' end='0x380' /><slave name='avs_eth_0.mms_reg' start='0x380' end='0x3C0' /><slave name='reg_bsn_monitor_ddr.mem' start='0x3C0' end='0x400' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x400' end='0x440' /><slave name='timer_0.s1' start='0x440' end='0x460' /><slave name='reg_diag_bg_ddr.mem' start='0x460' end='0x480' /><slave name='reg_diag_bg_1gbe.mem' start='0x480' end='0x4A0' /><slave name='reg_epcs.mem' start='0x4A0' end='0x4C0' /><slave name='reg_remu.mem' start='0x4C0' end='0x4E0' /><slave name='reg_unb_sens.mem' start='0x4E0' end='0x500' /><slave name='pio_wdi.s1' start='0x500' end='0x510' /><slave name='reg_io_ddr.mem' start='0x510' end='0x520' /><slave name='reg_dp_offload_tx_1gbe.mem' start='0x520' end='0x528' /><slave name='reg_mmdp_data.mem' start='0x528' end='0x530' /><slave name='reg_mmdp_ctrl.mem' start='0x530' end='0x538' /><slave name='reg_dpmm_data.mem' start='0x538' end='0x540' /><slave name='reg_dpmm_ctrl.mem' start='0x540' end='0x548' /><slave name='pio_pps.mem' start='0x548' end='0x550' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x550' end='0x558' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='ram_diag_bg_ddr.mem' start='0x5000' end='0x6000' /><slave name='ram_diag_bg_1gbe.mem' start='0x6000' end='0x7000' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x40000' end='0x50000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0x50000' end='0x60000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_10gbe.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_10gbe_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='reg_dp_offload_tx_1gbe.mem' start='0x3008' end='0x3010' /><slave name='reg_diag_tx_seq_ddr.mem' start='0x3010' end='0x3020' /><slave name='reg_diag_rx_seq_ddr.mem' start='0x3020' end='0x3040' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3040' end='0x3080' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x3080' end='0x3100' /><slave name='reg_dp_offload_rx_1gbe_hdr_dat.mem' start='0x3100' end='0x3200' /><slave name='reg_dp_offload_tx_1gbe_hdr_dat.mem' start='0x3200' end='0x3300' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x3300' end='0x3380' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3380' end='0x3400' /><slave name='reg_dp_offload_tx_10gbe_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='ram_diag_bg_10gbe.mem' start='0x4000' end='0x8000' /><slave name='avs_eth_0.mms_tse' start='0x8000' end='0x9000' /><slave name='avs_eth_1.mms_ram' start='0x9000' end='0xA000' /><slave name='avs_eth_0.mms_ram' start='0xA000' end='0xB000' /><slave name='ram_diag_bg_ddr.mem' start='0xB000' end='0xC000' /><slave name='ram_diag_bg_1gbe.mem' start='0xC000' end='0xD000' /><slave name='avs_eth_1.mms_reg' start='0xD000' end='0xD040' /><slave name='avs_eth_0.mms_reg' start='0xD040' end='0xD080' /><slave name='reg_bsn_monitor_ddr.mem' start='0xD080' end='0xD0C0' /><slave name='reg_bsn_monitor_1GbE.mem' start='0xD0C0' end='0xD100' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0xD100' end='0xD120' /><slave name='reg_diag_bg_10gbe.mem' start='0xD120' end='0xD140' /><slave name='timer_0.s1' start='0xD140' end='0xD160' /><slave name='reg_diag_bg_ddr.mem' start='0xD160' end='0xD180' /><slave name='reg_diag_bg_1gbe.mem' start='0xD180' end='0xD1A0' /><slave name='reg_epcs.mem' start='0xD1A0' end='0xD1C0' /><slave name='reg_remu.mem' start='0xD1C0' end='0xD1E0' /><slave name='reg_unb_sens.mem' start='0xD1E0' end='0xD200' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0xD200' end='0xD210' /><slave name='pio_wdi.s1' start='0xD210' end='0xD220' /><slave name='reg_io_ddr.mem' start='0xD220' end='0xD230' /><slave name='reg_mmdp_data.mem' start='0xD230' end='0xD238' /><slave name='reg_mmdp_ctrl.mem' start='0xD238' end='0xD240' /><slave name='reg_dpmm_data.mem' start='0xD240' end='0xD248' /><slave name='reg_dpmm_ctrl.mem' start='0xD248' end='0xD250' /><slave name='pio_pps.mem' start='0xD250' end='0xD258' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xD258' end='0xD260' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_ss_ss_wide.mem' start='0x40000' end='0x50000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x50000' end='0x60000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0x60000' end='0x70000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@@ -1834,7 +2676,7 @@
<parameter name="instruction_master_high_performance_paddr_size" value="0" />
<parameter name="instruction_master_paddr_base" value="0" />
<parameter name="instruction_master_paddr_size" value="0" />
- <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="internalIrqMaskSystemInfo" value="15" />
<parameter name="io_regionbase" value="0" />
<parameter name="io_regionsize" value="0" />
<parameter name="master_addr_map" value="false" />
@@ -2016,6 +2858,15 @@
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="1" />
</module>
+ <module
+ name="ram_diag_bg_10gbe"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="12" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module
name="ram_diag_bg_1gbe"
kind="avs_common_mm"
@@ -2030,6 +2881,15 @@
<parameter name="g_adr_w" value="10" />
<parameter name="g_dat_w" value="32" />
</module>
+ <module
+ name="ram_diag_data_buffer_10gbe"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="14" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module
name="ram_diag_data_buffer_1gbe"
kind="avs_common_mm"
@@ -2053,6 +2913,15 @@
<parameter name="g_adr_w" value="14" />
<parameter name="g_dat_w" value="32" />
</module>
+ <module
+ name="reg_bsn_monitor_10GbE"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module
name="reg_bsn_monitor_1GbE"
kind="avs_common_mm"
@@ -2071,6 +2940,15 @@
<parameter name="g_adr_w" value="4" />
<parameter name="g_dat_w" value="32" />
</module>
+ <module
+ name="reg_diag_bg_10gbe"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module
name="reg_diag_bg_1gbe"
kind="avs_common_mm"
@@ -2085,6 +2963,15 @@
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
</module>
+ <module
+ name="reg_diag_data_buffer_10gbe"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module
name="reg_diag_data_buffer_1gbe"
kind="avs_common_mm"
@@ -2103,6 +2990,69 @@
<parameter name="g_adr_w" value="5" />
<parameter name="g_dat_w" value="32" />
</module>
+ <module
+ name="reg_diag_rx_seq_10gbe"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_diag_rx_seq_1gbe"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_diag_rx_seq_ddr"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_diag_tx_seq_10gbe"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="4" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_diag_tx_seq_1gbe"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="2" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_diag_tx_seq_ddr"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="2" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_dp_offload_rx_10gbe_hdr_dat"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="8" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module
name="reg_dp_offload_rx_1gbe_hdr_dat"
kind="avs_common_mm"
@@ -2112,6 +3062,24 @@
<parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
</module>
+ <module
+ name="reg_dp_offload_tx_10gbe"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="7" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_dp_offload_tx_10gbe_hdr_dat"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="8" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module
name="reg_dp_offload_tx_1gbe"
kind="avs_common_mm"
@@ -2225,7 +3193,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0550" />
+ <parameter name="baseAddress" value="0xd258" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2241,286 +3209,439 @@
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_unb_sens.mem">
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd1e0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd250" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_remu.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd1c0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_epcs.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd1a0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_dpmm_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd248" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_dpmm_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd240" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_mmdp_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd238" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_mmdp_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd230" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_tr_10GbE_qsfp_ring.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00200000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_1GbE.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd0c0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx_1gbe.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3008" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx_1gbe_hdr_dat.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3200" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_rx_1gbe_hdr_dat.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3100" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_diag_data_buffer_1gbe.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3380" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="ram_diag_data_buffer_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x04e0" />
+ <parameter name="baseAddress" value="0x00060000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="rom_system_info.mem">
+ end="reg_diag_bg_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x1000" />
+ <parameter name="baseAddress" value="0xd180" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="pio_system_info.mem">
+ end="ram_diag_bg_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
+ <parameter name="baseAddress" value="0xc000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="pio_pps.mem">
+ end="reg_tr_10GbE_back0.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0548" />
+ <parameter name="baseAddress" value="0x00400000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_wdi.mem">
+ end="reg_tr_10GbE_back1.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3000" />
+ <parameter name="baseAddress" value="0x00100000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_remu.mem">
+ end="reg_bsn_monitor_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x04c0" />
+ <parameter name="baseAddress" value="0xd080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_epcs.mem">
+ end="reg_diag_bg_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x04a0" />
+ <parameter name="baseAddress" value="0xd160" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_dpmm_ctrl.mem">
+ end="ram_diag_bg_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0540" />
+ <parameter name="baseAddress" value="0xb000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_dpmm_data.mem">
+ end="reg_diag_data_buffer_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0538" />
+ <parameter name="baseAddress" value="0x3300" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_mmdp_ctrl.mem">
+ end="ram_diag_data_buffer_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0530" />
+ <parameter name="baseAddress" value="0x00050000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_mmdp_data.mem">
+ end="ram_ss_ss_wide.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0528" />
+ <parameter name="baseAddress" value="0x00040000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_tr_10GbE_qsfp_ring.mem">
+ end="reg_io_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00200000" />
+ <parameter name="baseAddress" value="0xd220" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_bsn_monitor_1GbE.mem">
+ end="reg_bsn_monitor_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x0100" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_dp_offload_tx_1gbe.mem">
+ end="reg_dp_offload_tx_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0520" />
+ <parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_dp_offload_tx_1gbe_hdr_dat.mem">
+ end="reg_dp_offload_tx_10gbe_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
+ <parameter name="baseAddress" value="0x3400" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_dp_offload_rx_1gbe_hdr_dat.mem">
+ end="reg_dp_offload_rx_10gbe_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x0400" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_diag_data_buffer_1gbe.mem">
+ end="reg_diag_data_buffer_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0300" />
+ <parameter name="baseAddress" value="0x3080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="ram_diag_data_buffer_1gbe.mem">
+ end="ram_diag_data_buffer_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00050000" />
+ <parameter name="baseAddress" value="0x00010000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_diag_bg_1gbe.mem">
+ end="reg_diag_bg_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0480" />
+ <parameter name="baseAddress" value="0xd120" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="ram_diag_bg_1gbe.mem">
+ end="ram_diag_bg_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x6000" />
+ <parameter name="baseAddress" value="0x4000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_tr_10GbE_back0.mem">
+ end="reg_diag_tx_seq_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00400000" />
+ <parameter name="baseAddress" value="0xd200" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_tr_10GbE_back1.mem">
+ end="reg_diag_rx_seq_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00100000" />
+ <parameter name="baseAddress" value="0xd100" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_bsn_monitor_ddr.mem">
+ end="reg_diag_tx_seq_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x03c0" />
+ <parameter name="baseAddress" value="0x3040" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_diag_bg_ddr.mem">
+ end="reg_diag_rx_seq_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0460" />
+ <parameter name="baseAddress" value="0x0080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="ram_diag_bg_ddr.mem">
+ end="reg_diag_tx_seq_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x5000" />
+ <parameter name="baseAddress" value="0x3010" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_diag_data_buffer_ddr.mem">
+ end="reg_diag_rx_seq_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0080" />
+ <parameter name="baseAddress" value="0x3020" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="ram_diag_data_buffer_ddr.mem">
+ end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00040000" />
+ <parameter name="baseAddress" value="0xa000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="ram_ss_ss_wide.mem">
+ end="avs_eth_1.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00010000" />
+ <parameter name="baseAddress" value="0x9000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="reg_io_ddr.mem">
+ end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0510" />
+ <parameter name="baseAddress" value="0xd040" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="avs_eth_0.mms_ram">
+ end="avs_eth_1.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x4000" />
+ <parameter name="baseAddress" value="0xd000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="avs_eth_0.mms_reg">
+ end="avs_eth_0.mms_tse">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0380" />
+ <parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
- end="avs_eth_0.mms_tse">
+ end="avs_eth_1.mms_tse">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x2000" />
<parameter name="defaultConnection" value="false" />
@@ -2540,7 +3661,7 @@
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0500" />
+ <parameter name="baseAddress" value="0xd210" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2549,7 +3670,7 @@
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0440" />
+ <parameter name="baseAddress" value="0xd140" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2580,6 +3701,7 @@
start="clk_0.clk"
end="onchip_memory2_0.clk1" />
<connection kind="clock" version="15.0" start="clk_0.clk" end="avs_eth_0.mm" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="avs_eth_1.mm" />
<connection
kind="clock"
version="15.0"
@@ -2705,6 +3827,76 @@
start="clk_0.clk"
end="ram_ss_ss_wide.system" />
<connection kind="clock" version="15.0" start="clk_0.clk" end="reg_io_ddr.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_10GbE.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_dp_offload_tx_10gbe.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_dp_offload_tx_10gbe_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_dp_offload_rx_10gbe_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_diag_data_buffer_10gbe.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="ram_diag_data_buffer_10gbe.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_diag_bg_10gbe.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="ram_diag_bg_10gbe.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_diag_tx_seq_1gbe.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_diag_rx_seq_1gbe.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_diag_tx_seq_10gbe.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_diag_rx_seq_10gbe.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_diag_tx_seq_ddr.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_diag_rx_seq_ddr.system" />
<connection
kind="interrupt"
version="15.0"
@@ -2716,17 +3908,29 @@
kind="interrupt"
version="15.0"
start="cpu_0.irq"
- end="jtag_uart_0.irq">
+ end="avs_eth_1.interrupt">
<parameter name="irqNumber" value="1" />
</connection>
- <connection kind="interrupt" version="15.0" start="cpu_0.irq" end="timer_0.irq">
+ <connection
+ kind="interrupt"
+ version="15.0"
+ start="cpu_0.irq"
+ end="jtag_uart_0.irq">
<parameter name="irqNumber" value="2" />
</connection>
+ <connection kind="interrupt" version="15.0" start="cpu_0.irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="3" />
+ </connection>
<connection
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="avs_eth_1.mm_reset" />
<connection
kind="reset"
version="15.0"
@@ -2893,11 +4097,86 @@
version="15.0"
start="clk_0.clk_reset"
end="reg_io_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_tx_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_tx_10gbe_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_rx_10gbe_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_diag_data_buffer_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="ram_diag_data_buffer_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_diag_bg_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="ram_diag_bg_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_diag_tx_seq_1gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_diag_rx_seq_1gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_diag_tx_seq_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_diag_rx_seq_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_diag_tx_seq_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_diag_rx_seq_ddr.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="avs_eth_1.mm_reset" />
<connection
kind="reset"
version="15.0"
@@ -3068,6 +4347,76 @@
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_io_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_bsn_monitor_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_dp_offload_tx_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_dp_offload_tx_10gbe_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_dp_offload_rx_10gbe_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_data_buffer_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="ram_diag_data_buffer_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_bg_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="ram_diag_bg_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_tx_seq_1gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_rx_seq_1gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_tx_seq_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_rx_seq_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_tx_seq_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_rx_seq_ddr.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 5d631e953a..858ea33864 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -27,236 +27,357 @@ PACKAGE qsys_unb2_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v15 QSYS builder
-----------------------------------------------------------------------------
+
component qsys_unb2_test is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_ddr_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_ddr_clk_export : out std_logic; -- export
- ram_diag_bg_ddr_read_export : out std_logic; -- export
- ram_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_ddr_reset_export : out std_logic; -- export
- ram_diag_bg_ddr_write_export : out std_logic; -- export
- ram_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_ddr_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_ddr_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_ddr_clk_export : out std_logic; -- export
- reg_bsn_monitor_ddr_read_export : out std_logic; -- export
- reg_bsn_monitor_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_ddr_reset_export : out std_logic; -- export
- reg_bsn_monitor_ddr_write_export : out std_logic; -- export
- reg_bsn_monitor_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_ddr_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_ddr_clk_export : out std_logic; -- export
- reg_diag_bg_ddr_read_export : out std_logic; -- export
- reg_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_ddr_reset_export : out std_logic; -- export
- reg_diag_bg_ddr_write_export : out std_logic; -- export
- reg_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
- reg_io_ddr_clk_export : out std_logic; -- export
- reg_io_ddr_read_export : out std_logic; -- export
- reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_reset_export : out std_logic; -- export
- reg_io_ddr_write_export : out std_logic; -- export
- reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_ddr_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_ddr_clk_export : out std_logic; -- export
+ ram_diag_bg_ddr_read_export : out std_logic; -- export
+ ram_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_ddr_reset_export : out std_logic; -- export
+ ram_diag_bg_ddr_write_export : out std_logic; -- export
+ ram_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_ddr_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_ddr_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_ddr_clk_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_read_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_ddr_reset_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_write_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_ddr_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_ddr_clk_export : out std_logic; -- export
+ reg_diag_bg_ddr_read_export : out std_logic; -- export
+ reg_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_ddr_reset_export : out std_logic; -- export
+ reg_diag_bg_ddr_write_export : out std_logic; -- export
+ reg_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_io_ddr_clk_export : out std_logic; -- export
+ reg_io_ddr_read_export : out std_logic; -- export
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_reset_export : out std_logic; -- export
+ reg_io_ddr_write_export : out std_logic; -- export
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_reset_export : out std_logic -- export
);
- end component qsys_unb2_test;
+ end component qsys_unb2_test;
+
+
END qsys_unb2_test_pkg;
+
--
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