diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 6704cc7938baad357396d03a0a0b2242514bcf33..52cbfe039acb011af2e3803dddca2335b422e72b 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -49,7 +49,8 @@ ENTITY unb2_test IS
g_factory_image : BOOLEAN := FALSE;
g_nof_streams_qsfp : NATURAL := 4;--c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
g_nof_streams_ring : NATURAL := 0; --FIXME
- g_nof_streams_back : NATURAL := 24 --FIXME
+ g_nof_streams_back0: NATURAL := c_unb2_board_tr_back.bus_w;
+ g_nof_streams_back1: NATURAL := c_unb2_board_tr_back.bus_w
);
PORT (
-- GENERAL
@@ -79,8 +80,8 @@ ENTITY unb2_test IS
BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
-- back transceivers
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
- BCK_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
+ BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
@@ -128,9 +129,9 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_use_lpbk : BOOLEAN := FALSE; --g_design_name = "unb2_test_lpbk";
CONSTANT c_use_1GbE : BOOLEAN := FALSE; --g_design_name = "unb2_test_1GbE";
CONSTANT c_use_10GbE : BOOLEAN := TRUE; --g_design_name = "unb2_test_10GbE";
- CONSTANT g_nof_streams : NATURAL := (g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back);
+ CONSTANT g_nof_streams : NATURAL := (g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back0 + g_nof_streams_back1);
CONSTANT g_nof_qsfp_bus : NATURAL := ceil_div(g_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w);
- CONSTANT g_nof_back_bus : NATURAL := ceil_div(g_nof_streams_back,c_unb2_board_tr_back.bus_w);
+ CONSTANT g_nof_back_bus : NATURAL := ceil_div(g_nof_streams_back0,c_unb2_board_tr_back.bus_w) + ceil_div(g_nof_streams_back1,c_unb2_board_tr_back.bus_w);
CONSTANT c_data_w : NATURAL := sel_a_b(c_use_lpbk, c_lpbk_data_w, -- Select correct c_data_w when one interface is used
sel_a_b(c_use_1GbE, c_eth_data_w,
sel_a_b(c_use_10GbE, c_xgmii_data_w, 0)));
@@ -272,20 +273,24 @@ ARCHITECTURE str OF unb2_test IS
-- 10GbE
SIGNAL i_serial_10G_tx_qsfp_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO 0);
SIGNAL i_serial_10G_rx_qsfp_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO 0);
- SIGNAL i_serial_10G_tx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back-1 DOWNTO 0);
- SIGNAL i_serial_10G_rx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back-1 DOWNTO 0);
+ SIGNAL i_serial_10G_tx_back0_arr : STD_LOGIC_VECTOR(g_nof_streams_back0-1 DOWNTO 0);
+ SIGNAL i_serial_10G_rx_back0_arr : STD_LOGIC_VECTOR(g_nof_streams_back0-1 DOWNTO 0);
+ SIGNAL i_serial_10G_tx_back1_arr : STD_LOGIC_VECTOR(g_nof_streams_back1-1 DOWNTO 0);
+ SIGNAL i_serial_10G_rx_back1_arr : STD_LOGIC_VECTOR(g_nof_streams_back1-1 DOWNTO 0);
SIGNAL serial_10G_tx_qsfp_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_qsfp_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp-1 DOWNTO 0);
SIGNAL serial_10G_tx_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_ring-1 DOWNTO 0);
- SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 DOWNTO 0);
+ SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back0+g_nof_streams_back1-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back0+g_nof_streams_back1-1 DOWNTO 0);
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso;
SIGNAL reg_tr_10GbE_mosi2 : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso2 : t_mem_miso;
+ SIGNAL reg_tr_10GbE_mosi3 : t_mem_mosi;
+ SIGNAL reg_tr_10GbE_miso3 : t_mem_miso;
SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
@@ -806,38 +811,57 @@ BEGIN
serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
);
- u_tr_10GbE_back: ENTITY unb2_board_lib.unb2_board_10gbe
+ u_tr_10GbE_back0: ENTITY unb2_board_lib.unb2_board_10gbe -- Lower Back lines
GENERIC MAP (
g_technology => g_technology,
g_sim => g_sim,
g_sim_level => 1,
- g_nof_macs => g_nof_streams_back,
+ g_nof_macs => g_nof_streams_back0,
g_tx_fifo_fill => c_def_10GbE_block_size,
g_tx_fifo_size => c_def_10GbE_block_size*2
)
PORT MAP (
- tr_ref_clk => BCK_REF_CLK,--SB_CLK,
-
- -- MM interface
+ tr_ref_clk => BCK_REF_CLK,
mm_rst => mm_rst,
mm_clk => mm_clk,
-
reg_mac_mosi => reg_tr_10GbE_mosi2, -- FIXME use separate
reg_mac_miso => reg_tr_10GbE_miso2,
-
- -- DP interface
dp_rst => dp_rst,
dp_clk => dp_clk,
- src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
- src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
+ src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
+ src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
+ snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
+ snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
+
+ serial_tx_arr => i_serial_10G_tx_back0_arr,
+ serial_rx_arr => i_serial_10G_rx_back0_arr
+ );
+ u_tr_10GbE_back1: ENTITY unb2_board_lib.unb2_board_10gbe -- Upper Back lines
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => g_nof_streams_back1,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size*2
+ )
+ PORT MAP (
+ tr_ref_clk => SB_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_mosi3, -- FIXME use separate
+ reg_mac_miso => reg_tr_10GbE_miso3,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
- snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
+ src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
+ src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
+ snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
+ snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
- -- Serial IO
- serial_tx_arr => i_serial_10G_tx_back_arr,
- serial_rx_arr => i_serial_10G_rx_back_arr
+ serial_tx_arr => i_serial_10G_tx_back1_arr,
+ serial_rx_arr => i_serial_10G_rx_back1_arr
);
@@ -917,9 +941,14 @@ BEGIN
red_led_arr => user_red_led_arr(g_nof_qsfp_bus-1 DOWNTO 0)
);
- gen_back_wires: FOR i IN 0 TO g_nof_streams_back-1 GENERATE
- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back_arr(i);
- i_serial_10G_rx_back_arr(i) <= serial_10G_rx_back_arr(i);
+
+ gen_back0_wires: FOR i IN 0 TO g_nof_streams_back0-1 GENERATE
+ serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ END GENERATE;
+ gen_back1_wires: FOR i IN 0 TO g_nof_streams_back1-1 GENERATE
+ serial_10G_tx_back_arr(i+g_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+g_nof_streams_back0);
END GENERATE;
u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
@@ -932,8 +961,10 @@ BEGIN
-- Serial I/O
-- back transceivers
- BCK_RX(0) => BCK_RX,--(g_nof_streams_back-1 downto 0),
- BCK_TX(0) => BCK_TX,--(g_nof_streams_back-1 downto 0),
+ BCK_RX(0) => BCK_RX(g_nof_streams_back0-1 downto 0),
+ BCK_TX(0) => BCK_TX(g_nof_streams_back0-1 downto 0),
+ BCK_RX(1) => BCK_RX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0),
+ BCK_TX(1) => BCK_TX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0),
BCK_SDA => BCK_SDA,
BCK_SCL => BCK_SCL,
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
index f36d411a4d55568626dad35839c8d17f723ca4d5..6f2ae0779ec89dea2384da08a7a5c4899e499e9e 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
@@ -29,9 +29,9 @@ create_clock -name {ETH_CLK} -period 8.000 -waveform { 0.000 4.000 } [get_ports
#create_clock -name {SB_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SB_CLK}]
#create_clock -name {SA_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SA_CLK}]
-# from Jonathan:
create_clock -period 1.552 -name {SA_CLK} { SA_CLK }
create_clock -period 1.552 -name {SB_CLK} { SB_CLK }
+create_clock -period 1.552 -name {BCK_REF_CLK} { BCK_REF_CLK }
@@ -41,6 +41,7 @@ derive_clock_uncertainty
# Effectively set false path from this clock to all other clocks
set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]
+set_clock_groups -asynchronous -group [get_clocks BCK_REF_CLK]
set_clock_groups -asynchronous -group [get_clocks SB_CLK]
set_clock_groups -asynchronous -group [get_clocks SA_CLK]
set_clock_groups -asynchronous -group [get_clocks ETH_CLK]
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
index 45c2bc2b81fa76d2fe9906c847506e78a3e9bbfe..aa129fd5a7272e017580884b1f486e5df498ba96 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
@@ -71,9 +71,7 @@ PACKAGE unb2_board_pkg IS
i2c_w : NATURAL;
END RECORD;
- --CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 48, 3); -- per node: 1 bus with 48 channels
- --CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 4, 3); -- per node: 1 bus with 48 channels
- CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 24, 3); -- per node: 1 bus with 48 channels
+ CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 24, 3); -- per node: 2 buses with 24 channels
CONSTANT c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
CONSTANT c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
CONSTANT c_unb2_board_tr_qsfp_nof_leds : NATURAL := c_unb2_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp