From 627a0e48c378a03ce5cd2351106c992c30202230 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Mon, 17 Nov 2014 14:31:36 +0000
Subject: [PATCH] -Added support for Verilog files (both synth and TB files);
-Added support for .vho files (TB files only); -Updated hdltool_readme.txt
accordingly.
---
tools/hdltool_readme.txt | 2 ++
tools/oneclick/base/modelsim_config.py | 39 ++++++++++++++++++++++----
2 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/tools/hdltool_readme.txt b/tools/hdltool_readme.txt
index 8999ef8a96..2b6af0f619 100644
--- a/tools/hdltool_readme.txt
+++ b/tools/hdltool_readme.txt
@@ -301,10 +301,12 @@ d) hdllib.cfg key descriptions
- synth_files =
All HDL files that are needed for synthesis. For Modelsim they need to be in compile order and they areplaced in the 'synth_files' project folder.
For Quartus synthesis these files get included in the HDL library qip file.
+ Both Verilog and VHDL files are supported.
- test_bench_files =
All HDL files that are needed only for simulation. These are typically test bench files, but also HDL models. For Modelsim they need to
be in compile order and they are placed in the 'test_bench_files' project folder.
+ Both Verilog and VHDL files are supported.
- synth_top_level_entity =
When this key exists then a Quartus project file (QPF) and Quartus settings file (QSF) will be created for this HDL library. If this key does
diff --git a/tools/oneclick/base/modelsim_config.py b/tools/oneclick/base/modelsim_config.py
index d10a5731ed..4a71ede224 100644
--- a/tools/oneclick/base/modelsim_config.py
+++ b/tools/oneclick/base/modelsim_config.py
@@ -178,22 +178,51 @@ class ModelsimConfig(hdl_config.HdlConfig):
for i, fn in enumerate(project_files):
filePathName = cm.expand_file_path_name(fn, lib_path)
fp.write('Project_File_%d = %s\n' % (i, filePathName))
- project_file_p_defaults_vhdl = 'vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 vlog_1995compat 0 last_compile 0 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn3 1 vlog_vopt {} cover_optlevel 3 voptflow 1 vhdl_options {} vhdl_warn4 1 toggle - ood 0 vhdl_warn5 1 cover_noshort 0 compile_to work cover_nosub 0 dont_compile 0 vhdl_use93 2002 cover_stmt 1'
- project_file_p_defaults_tcl = 'last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1'
+
+ project_file_p_defaults_hdl = 'vhdl_novitalcheck 0 group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 vlog_1995compat 0 last_compile 0 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn3 1 vlog_vopt {} cover_optlevel 3 voptflow 1 vhdl_options {} vhdl_warn4 1 toggle - ood 0 vhdl_warn5 1 cover_noshort 0 compile_to work cover_nosub 0 dont_compile 0 vhdl_use93 2002 cover_stmt 1'
+ project_file_p_defaults_vhdl = 'file_type vhdl'
+ project_file_p_defaults_verilog = 'file_type verilog'
+ project_file_p_defaults_tcl = 'last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1'
+
project_folders = []
offset = 0
+
nof_synth_files = len(synth_files)
if nof_synth_files>0:
project_folders.append('synth_files')
- for i in range(nof_synth_files):
- fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (offset+i, project_folders[-1], offset+i, project_file_p_defaults_vhdl))
+ for i in range(nof_synth_files):
+
+ # Add file type specific settings
+ file_ext = synth_files[i].split('.')[-1]
+ if file_ext=='vhd' or file_ext=='vhdl':
+ project_file_p_defaults_file_specific = project_file_p_defaults_vhdl
+ elif file_ext=='v':
+ project_file_p_defaults_file_specific = project_file_p_defaults_verilog
+ else:
+ print '\nERROR - Undefined file extension in synth_files:', synth_files[i]
+ sys.exit()
+
+ fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (offset+i, project_folders[-1], offset+i, project_file_p_defaults_hdl+' '+project_file_p_defaults_file_specific))
offset = nof_synth_files
+
nof_test_bench_files = len(test_bench_files)
if nof_test_bench_files>0:
project_folders.append('test_bench_files')
for i in range(nof_test_bench_files):
- fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (offset+i, project_folders[-1], offset+i, project_file_p_defaults_vhdl))
+
+ # Add file type specific settings
+ file_ext = test_bench_files[i].split('.')[-1]
+ if file_ext=='vhd' or file_ext=='vho' or file_ext=='vhdl':
+ project_file_p_defaults_file_specific = project_file_p_defaults_vhdl
+ elif file_ext=='v':
+ project_file_p_defaults_file_specific = project_file_p_defaults_verilog
+ else:
+ print '\nERROR - Undefined file extension in test_bench_files:', test_bench_files[i]
+ sys.exit()
+
+ fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (offset+i, project_folders[-1], offset+i, project_file_p_defaults_hdl+' '+project_file_p_defaults_file_specific))
offset += nof_test_bench_files
+
if 'modelsim_compile_ip_files' in lib_dict:
nof_compile_ip_files = len(compile_ip_files)
if nof_compile_ip_files>0:
--
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