From 6240452f80523138074c00c2512613879ddb75c0 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Thu, 28 May 2015 16:25:09 +0000
Subject: [PATCH] Made a lot of changes.
---
tools/oneclick/base/mmm_gen.py | 346 +++++++++++++++++----------------
1 file changed, 179 insertions(+), 167 deletions(-)
diff --git a/tools/oneclick/base/mmm_gen.py b/tools/oneclick/base/mmm_gen.py
index c44865ca3e..0a2fa62429 100644
--- a/tools/oneclick/base/mmm_gen.py
+++ b/tools/oneclick/base/mmm_gen.py
@@ -31,7 +31,9 @@ import sys
import os
import os.path
import shutil
+import argparse
import entity
+import hdl_config
s_header = """--------------------------------------------------------------------------------
--
@@ -55,16 +57,26 @@ s_header = """------------------------------------------------------------------
--------------------------------------------------------------------------------
"""
-s_libraries = """LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE unb1_board_lib.unb1_board_pkg.ALL;
-USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
-USE mm_lib.mm_file_pkg.ALL;
-USE mm_lib.mm_file_unb_pkg.ALL;
-"""
+
+s_libraries = "LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;\n\
+USE IEEE.STD_LOGIC_1164.ALL;\n\
+USE IEEE.NUMERIC_STD.ALL;\n\
+USE common_lib.common_pkg.ALL;\n\
+USE common_lib.common_mem_pkg.ALL;\n\
+USE common_lib.tb_common_mem_pkg.ALL;\n\
+USE common_lib.common_field_pkg.ALL;\n\
+USE common_lib.common_network_total_header_pkg.ALL;\n\
+USE common_lib.common_network_layers_pkg.ALL;\n\
+USE common_lib.common_mem_pkg.ALL;\n\
+USE unb1_board_lib.unb1_board_pkg.ALL;\n\
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;\n\
+USE mm_lib.mm_file_pkg.ALL;\n\
+USE mm_lib.mm_file_unb_pkg.ALL;\n\
+USE eth_lib.eth_pkg.ALL;\n\
+USE technology_lib.technology_pkg.ALL;\n\
+USE tech_tse_lib.tech_tse_pkg.ALL;\n\
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;\n\n"
+
s_signals_clk = "SIGNAL i_mm_clk : STD_LOGIC := '1';\n\
SIGNAL i_dp_clk : STD_LOGIC := '1';\n"
@@ -81,6 +93,32 @@ i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;\n"
s_fileio_dp_clk = "i_dp_clk <= NOT i_dp_clk AFTER c_dp_clk_period/2;\n"
+s_fileio_eth_init = "----------------------------------------------------------------------------\n\
+-- 1GbE setup sequence normally performed by unb_os@NIOS\n\
+----------------------------------------------------------------------------\n\
+p_eth_setup : PROCESS\n\
+BEGIN\n\
+ sim_eth_mm_bus_switch <= '1';\n\
+ eth1g_tse_mosi.wr <= '0';\n\
+ eth1g_tse_mosi.rd <= '0';\n\
+ WAIT FOR 400 ns;\n\
+ WAIT UNTIL rising_edge(mm_clk);\n\
+ proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);\n\
+ -- Enable RX\n\
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en\n\
+ sim_eth_mm_bus_switch <= '0';\n\
+ WAIT;\n\
+END PROCESS;\n\
+\n\
+p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)\n\
+BEGIN\n\
+ IF sim_eth_mm_bus_switch = '1' THEN\n\
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;\n\
+ ELSE\n\
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;\n\
+ END IF;\n\
+END PROCESS;\n"
+
s_fileio_poll = "----------------------------------------------------------------------------\n\
-- Procedure that polls a sim control file that can be used to e.g. get\n\
-- the simulation time in ns\n\
@@ -101,12 +139,11 @@ peripherals_vhdl2python = { 'reg_wdi' : "reg_wdi",\
'rom_unb_system_info' : "rom_system_info",\
'reg_unb_sens' : "reg_unb_sens",\
'reg_ppsh' : "pio_pps",\
- 'reg_eth' : "avs_eth_0_mms_reg"}
-
+ 'eth1g_reg' : "avs_eth_0_mms_reg"}
class QsysEntity(entity.Entity):
- def make_qsys_instance(self, peripherals):
+ def make_qsys_instance(self, mmm_conf):
s_start = "u_" + self.name + " : " + self.name + "\n" + self.s_port_map_start
self.portNames.sort()
s_port_connects = ""
@@ -121,7 +158,7 @@ class QsysEntity(entity.Entity):
else:
s_connect = s_reg_name + "_mosi.address("
- span = self.find_span(s_reg_name, peripherals)
+ span = self.find_span(s_reg_name, mmm_conf.peripherals)
if span == 1:
s_connect = s_connect + "0),"
else:
@@ -150,9 +187,9 @@ class QsysEntity(entity.Entity):
if s_reg_name[-1].isdigit():
s_index = s_reg_name.rsplit("_", 1)[1]
s_reg_name = s_reg_name.rsplit("_", 1)[0]
- s_connect = s_reg_name + "_mosi_arr(" + s_index + ").rddata(c_word_w-1 DOWNTO 0),"
+ s_connect = s_reg_name + "_miso_arr(" + s_index + ").rddata(c_word_w-1 DOWNTO 0),"
else:
- s_connect = s_reg_name + "_mosi.rddata(c_word_w-1 DOWNTO 0),"
+ s_connect = s_reg_name + "_miso.rddata(c_word_w-1 DOWNTO 0),"
if "_writedata_export" in s:
s_reg_name = self.name_convert(s.split("_writedata_export")[0])
@@ -190,43 +227,16 @@ class QsysEntity(entity.Entity):
if "out_port_from_the_pio_wdi" in s:
s_connect = "pout_wdi,"
- # mm_clk + PLL's
- if "mm_clk" in s:
- s_connect = "i_mm_clk,"
-
- if "epcs_clk" in s:
- s_connect = "OPEN,"
-
- if s == "reset_n":
- s_connect = "xo_rst_n,"
+ # mm_clk
+ if "clk_in_clk" in s:
+ s_connect = "mm_clk,"
- if "altpll_0_locked_export" in s:
- s_connect = "mm_locked,"
-
- if "altpll_1_locked_export" in s:
- s_connect = "OPEN,"
-
- if "altpll_1_c0_clk" in s:
- s_connect = "i_dp_clk,"
-
- if "_areset_export" in s:
- s_connect = "xo_rst,"
+ if s == "reset_in_reset_n":
+ s_connect = "mm_rst,"
if "_phasedone_export" in s:
s_connect = "OPEN,"
- if "clk_0" in s:
- s_connect = "xo_clk,"
-
- if "board_clk_clk" in s:
- s_connect = "board_clk,"
-
- if "board_reset_reset" in s:
- s_connect = "board_reset_n,"
-
- if "altpll_0_c3_clk" in s:
- s_connect = "OPEN,"
-
s_port_connects = s_port_connects + " " + s.ljust(self.longestPortName) + " => " + s_connect + "\n"
s_port_connects = s_port_connects.rsplit(",",1)[0] + "\n"
@@ -247,21 +257,74 @@ class QsysEntity(entity.Entity):
span = int(peripherals[i][2])
return span
+class MmmEntity(entity.Entity):
+
+ def __init__(self, mmm_conf):
+ entity.Entity.__init__(self, mmm_conf.mmmName)
+ # Add default generics
+ self.add_generic( "g_sim", "BOOLEAN", "FALSE")
+ self.add_generic( "g_sim_unb_nr", "NATURAL", "0")
+ self.add_generic( "g_sim_node_nr", "NATURAL", "0")
+
+ # Add input clks
+ if "mm_clk" in mmm_conf.input_clks:
+ self.add_port("mm_clk", "IN", "STD_LOGIC", "\'1\'")
+ self.add_port("mm_rst", "IN", "STD_LOGIC", "\'1\'")
+
+ # Add UNB1 board peripherals
+ for s in mmm_conf.unb1_board_peripherals:
+
+ # Extra signals for ethernet peripheral
+ if(s[0] == "eth1g_ram"):
+ self.add_port("eth1g_tse_clk", "OUT", "STD_LOGIC")
+ self.add_port("eth1g_mm_rst", "OUT", "STD_LOGIC")
+ self.add_port("eth1g_reg_interrupt", "IN", "STD_LOGIC")
+
+ # Extra signal for Watchdog interface
+ if(s[0] == "reg_wdi"):
+ self.add_port("pout_wdi", "OUT", "STD_LOGIC", "\'1\'")
+
+ if(int(s[1]) == 1):
+ self.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
+ self.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
+ elif(int(s[1]) > 1):
+ self.add_port(s[0] + "_mosi_arr", "OUT", "t_mem_mosi_arr(" + str(int(s[1])-1) + " DOWNTO 0)")
+ self.add_port(s[0] + "_miso_arr", "IN", "t_mem_miso_arr(" + str(int(s[1])-1) + " DOWNTO 0)", "(others => c_mem_miso_rst)")
+
+ # Add custom peripherals
+ for s in mmm_conf.custom_peripherals:
+ if(int(s[1]) == 1):
+ self.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
+ self.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
+ elif(int(s[1]) > 1):
+ self.add_port(s[0] + "_mosi_arr", "OUT", "t_mem_mosi_arr(" + str(int(s[1])-1) + " DOWNTO 0)")
+ self.add_port(s[0] + "_miso_arr", "IN", "t_mem_miso_arr(" + str(int(s[1])-1) + " DOWNTO 0)", "(others => c_mem_miso_rst)")
+
class MmmGenerate:
- def __init__(self, mmmDir, mmmFileName='mmm.cfg'):
+ def __init__(self, mmmRootDir, mmmFileName='mmm.cfg', mmmLibraryName=''):
"""
"""
- self.mmmDir = mmmDir
+ self.mmmRootDir = mmmRootDir
self.mmmFileName = mmmFileName
-
+ self.mmmLibraryName = mmmLibraryName
# mmm config files
- self.mmm = common_dict_file.CommonDictFile(mmmDir, mmmFileName) # library dict files
+ self.mmm = common_dict_file.CommonDictFile(mmmRootDir, mmmFileName) # library dict files
if self.mmm.nof_dicts==0: sys.exit('Error : No mmm config file found')
+ if self.mmmLibraryName=='': sys.exit('Error: No mmmLibraryName specified');
+
+ for d in self.mmm.dicts:
+ name = self.mmm.get_key_value('mmm_name', d)
+ if name == mmmLibraryName:
+ self.mmm.remove_all_but_the_dict_from_list(d)
# Keep list of HDL library names
- self.mmm_name = "mmm_" + self.mmm.get_key_values('mmm_name')
- self.VhdlFileName = self.mmm_name + '.vhd'
+ self.designName = self.mmm.get_key_values('mmm_name')
+ self.mmmName = "mmm_" + self.mmm.get_key_values('mmm_name')
+ self.VhdlFilePath = self.mmm.filePaths[0] + '/../vhdl/'
+ self.VhdlFileName = self.mmmName + '.vhd'
+ self.QsysName = "qsys_" + self.designName
+ self.QsysFileName = self.QsysName + '.vhd'
self.input_clks = self.mmm.get_key_values('input_clks')
self.output_clks = self.mmm.get_key_values('output_clks')
self.unb1_board_peripherals_temp = self.mmm.get_key_values('unb1_board_peripherals').split()
@@ -271,25 +334,11 @@ class MmmGenerate:
self.peripherals = self.unb1_board_peripherals + self.custom_peripherals
self.mm_clk_period = self.mmm.get_key_values('sim_mm_clk_period')
self.dp_clk_period = self.mmm.get_key_values('sim_dp_clk_period')
- self.QsysName = "qsys_" + self.mmm.get_key_values('mmm_name')
- self.QsysFileName = self.QsysName + '.vhd'
def chunks(self, l, n):
n = max(1, n)
return [l[i:i + n] for i in range(0, len(l), n)]
- def make_mm_port_map_string(self, peripheral):
- print peripheral
- if(int(peripheral[1]) == 1):
- port_mosi = "\n" + peripheral[0] + "_mosi : OUT t_mem_mosi;\n"
- port_miso = "" + peripheral[0] + "_miso : IN t_mem_miso;\n"
- port_string = port_mosi + port_miso
- elif(int(peripheral[1]) > 1):
- port_mosi = "\n" + peripheral[0] + "_mosi_arr : OUT t_mem_mosi_arr(" + str(int(peripheral[1])-1) + " DOWNTO 0);\n"
- port_miso = "" + peripheral[0] + "_miso_arr : IN t_mem_miso_arr(" + str(int(peripheral[1])-1) + " DOWNTO 0);\n"
- port_string = port_mosi + port_miso
- return port_string
-
def make_mm_file_io_entry(self, peripheral):
if peripheral[0] in peripherals_vhdl2python:
python_name = peripherals_vhdl2python[peripheral[0]].upper()
@@ -297,150 +346,113 @@ class MmmGenerate:
python_name = peripheral[0].upper()
file_io_entry = ""
if(int(peripheral[1]) == 1):
- file_io_entry = "u_mm_file_" + peripheral[0] + " : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & " + r'"' + python_name + r'"' + ")\n PORT MAP(mm_rst, i_mm_clk, " + peripheral[0] + "_mosi, " + peripheral[0] + "_miso );\n"
+ file_io_entry = "u_mm_file_" + peripheral[0] + " : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & " + r'"' + python_name + r'"' + ")\n PORT MAP(mm_rst, mm_clk, " + peripheral[0] + "_mosi, " + peripheral[0] + "_miso );\n"
return file_io_entry
- def read_entity_from_file(self, path, name):
- f = file((path + name + ".vhd"), "r")
- s_return = ""
- s = ""
- while not('entity ' + name) in s:
- s = f.readline()
- s_return = s_return + s
- while not('end entity') in s:
- s = f.readline()
- # remove comments
- i = s.find('--')
- if i != -1:
- s=s[0:i] + "\n"
- s_return = s_return + s
- f.close()
- return s_return
-
if __name__ == '__main__':
- mmmDir = '../../../applications/apertif/designs/apertif_unb1_correlator/src/python/'
- buildDir = '../../../build/quartus/apertif_unb1_correlator/qsys_apertif_unb1_correlator/simulation/'
- mm_dir = '../../../../../UniBoard/trunk/Firmware/modules/mm/tb/vhdl/'
- mm_file = "mm_file"
+
+ # Parse command line arguments
+ toolsetSelect = ['unb1', 'unb2']
+
+ argparser = argparse.ArgumentParser(description='Create Memory Mapped Master entity for specified design name')
+ argparser.add_argument('-t','--toolset', help='choose toolset %s (default: %s)' % (toolsetSelect,toolsetSelect[0]), default=toolsetSelect[0], required=False)
+ argparser.add_argument('-v','--verbosity', help='verbosity >= 0 for more info', type=int, default=0, required=False)
+ argparser.add_argument('-l','--library', help='specify the library name of the design', default='', required=True)
+ args = vars(argparser.parse_args())
+ arg_verbosity = args['verbosity']
+ arg_library = args['library']
+ arg_toolset = args['toolset']
+ if arg_toolset not in toolsetSelect:
+ print 'Toolset %s is not supported' % arg_toolset
+ print 'Hint: give argument -h for possible options'
+ sys.exit(1)
+ toolFileName = 'hdltool_' + arg_toolset + '.cfg'
+
+
+ designName = arg_library # "unb1_terminal_bg_mesh_db"
+ libRootDir = 'RADIOHDL'
+ mmmRootDir = os.environ['RADIOHDL']
mmmFileName = 'mmm.cfg'
- mmm_conf = MmmGenerate( mmmDir = mmmDir, mmmFileName=mmmFileName)
+ mm_dir = '../../../../../UniBoard/trunk/Firmware/modules/mm/tb/vhdl/'
+ mm_file = "mm_file"
+
+ mmm_conf = MmmGenerate( mmmRootDir = mmmRootDir, mmmFileName=mmmFileName, mmmLibraryName = designName)
+ QsysBuildDir = os.environ['RADIOHDL']+'/build/' + arg_toolset + '/quartus/' + designName +'/qsys_' + designName + '/simulation/'
###################################
# Define the entity definitions
###################################
ent_qsys = QsysEntity()
- ent_mmm = entity.Entity(name = mmm_conf.mmm_name)
+ ent_mmm = MmmEntity(mmm_conf)
ent_mm_file = entity.Entity()
###################################
# Read the Qsys entity definition
###################################
- ent_qsys.read_entity_from_file(buildDir, mmm_conf.QsysName)
- s_qsys_comp = ent_qsys.make_component_instance(indend = 0)
+ ent_qsys.read_entity_from_file(QsysBuildDir, mmm_conf.QsysName)
+ ent_qsys.replace_std_logic_vector_with_std_logic()
+ s_qsys_comp = ent_qsys.make_component_definition(indend = 0)
###################################
# Read the mm_file entity definition
###################################
ent_mm_file.read_entity_from_file(mm_dir, mm_file)
- s_mm_file_comp = ent_mm_file.make_component_instance(indend = 0)
+ s_mm_file_comp = ent_mm_file.make_component_definition(indend = 0)
###################################
- # Make the entity definition
+ # Make the entity definition and a
+ # commented instantiation.
###################################
- # Start with entity header
- s_arch_content = ""
- s_arch_file = ""
-
- # Add input clks
- if "xo_clk" in mmm_conf.input_clks:
- ent_mmm.add_port("xo_clk", "IN", "STD_LOGIC", "1")
- ent_mmm.add_port("xo_rst_n", "IN", "STD_LOGIC", "0")
- ent_mmm.add_port("xo_rst", "IN", "STD_LOGIC", "0")
- if "board_clk" in mmm_conf.input_clks:
- ent_mmm.add_port("board_clk", "IN", "STD_LOGIC", "1")
- ent_mmm.add_port("board_reset_n", "IN", "STD_LOGIC", "1")
-
- # Add output clks
- if "mm_clk" in mmm_conf.output_clks:
- ent_mmm.add_port("mm_clk", "OUT", "STD_LOGIC")
- ent_mmm.add_port("mm_rst", "IN" , "STD_LOGIC", "1")
- ent_mmm.add_port("mm_locked", "OUT", "STD_LOGIC" )
- s_arch_content = s_arch_content + s_connect_mm_clk
- s_arch_file = s_arch_file + s_fileio_mm_clk
- if "dp_clk" in mmm_conf.output_clks:
- ent_mmm.add_port("dp_clk", "OUT", "STD_LOGIC", "1")
- s_arch_content = s_arch_content + s_connect_dp_clk
- s_arch_file = s_arch_file + s_fileio_dp_clk
-
- # Add UNB1 board peripherals
- # 1GbE control interface always:
- ent_mmm.add_port("eth1g_tse_clk", "OUT", "STD_LOGIC")
- ent_mmm.add_port("eth1g_mm_rst", "OUT", "STD_LOGIC")
- ent_mmm.add_port("eth1g_tse_mosi", "OUT", "t_mem_mosi")
- ent_mmm.add_port("eth1g_tse_miso", "IN" , "t_mem_miso", "c_mem_miso_rst")
- ent_mmm.add_port("eth1g_reg_mosi", "OUT", "t_mem_mosi")
- ent_mmm.add_port("eth1g_reg_miso", "IN" , "t_mem_miso", "c_mem_miso_rst")
- ent_mmm.add_port("eth1g_reg_interrupt", "IN", "STD_LOGIC")
- ent_mmm.add_port("eth1g_ram_mosi", "OUT", "t_mem_mosi")
- ent_mmm.add_port("eth1g_ram_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
-
- for s in mmm_conf.unb1_board_peripherals:
- if(int(s[1]) == 1):
- ent_mmm.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
- ent_mmm.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
- elif(int(s[1]) > 1):
- ent_mmm.add_port(s[0] + "_mosi_arr", "OUT", "t_mem_mosi_arr(" + str(int(s[1])-1) + " DOWNTO 0)")
- ent_mmm.add_port(s[0] + "_miso_arr", "IN", "t_mem_miso_arr(" + str(int(s[1])-1) + " DOWNTO 0)", "(others => c_mem_miso_rst)")
- s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(s)
-
- # Add reg_wdi port if included
- if "reg_wdi" in mmm_conf.unb1_board_peripherals:
- ent_mmm.add_port("pout_wdi", "OUT", "STD_LOGIC", "1")
-
- # Add custom peripherals
- for s in mmm_conf.custom_peripherals:
- if(int(s[1]) == 1):
- ent_mmm.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
- ent_mmm.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
- elif(int(s[1]) > 1):
- ent_mmm.add_port(s[0] + "_mosi_arr", "OUT", "t_mem_mosi_arr(" + str(int(s[1])-1) + " DOWNTO 0)")
- ent_mmm.add_port(s[0] + "_miso_arr", "IN", "t_mem_miso_arr(" + str(int(s[1])-1) + " DOWNTO 0)", "(others => c_mem_miso_rst)")
- s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(s)
-
- s_entity = ent_mmm.make_entity_instance()
-
+ s_entity = ent_mmm.make_entity_definition()
+ s_instantiation = ent_mmm.comment(ent_mmm.make_instantiation())
+
###################################
# Make the architecture header
###################################
- s_arch_start = "ARCHITECTURE str OF "+ str(mmm_conf.mmm_name) + " IS\n\n"
+ s_arch_start = "ARCHITECTURE str OF "+ str(mmm_conf.mmmName) + " IS\n\n"
s_arch_constants = ""
s_arch_constants = s_arch_constants + "CONSTANT c_mm_clk_period : TIME := " + str(mmm_conf.mm_clk_period) + " ns;\n"
s_arch_constants = s_arch_constants + "CONSTANT c_dp_clk_period : TIME := " + str(mmm_conf.dp_clk_period) + " ns;\n"
s_arch_constants = s_arch_constants + "CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, " + r'"FN", "BN"' + ");\n"
s_arch_constants = s_arch_constants + "CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type=" + r'"BN"' +", g_sim_node_nr-4, g_sim_node_nr);\n"
+ s_arch_constants = s_arch_constants + "CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X\"00228608\" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);"
+ s_arch_constants = s_arch_constants + "CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;"
+
+ s_arch_signals = ""
+ s_arch_signals = s_arch_signals + "SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;\n"
+ s_arch_signals = s_arch_signals + "SIGNAL sim_eth_psc_access : STD_LOGIC;\n"
+ s_arch_signals = s_arch_signals + "SIGNAL i_eth1g_reg_mosi : t_mem_mosi;\n"
+ s_arch_signals = s_arch_signals + "SIGNAL i_eth1g_reg_miso : t_mem_miso;\n"
+ s_arch_signals = s_arch_signals + "SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;\n"
+
s_arch_components = s_mm_file_comp + s_qsys_comp
- s_arch_header = s_arch_start + ent_qsys.apply_indend(s_arch_constants + "\n" + s_arch_components + s_signals_clk, 2)
+ s_arch_header = s_arch_start + ent_qsys.apply_indend(s_arch_constants + "\n" + s_arch_signals + "\n" + s_arch_components, 2)
###################################
# Make the architecture content
###################################
+ s_arch_file = ""
+ for s in mmm_conf.unb1_board_peripherals:
+ s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(s)
+ for s in mmm_conf.custom_peripherals:
+ s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(s)
+
# Make File I/O master
- eth_peripheral = ['reg_eth', '1', '8']
- s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(eth_peripheral)
- s_file = s_fileio_start + ent_qsys.apply_indend(s_arch_file + s_fileio_poll, 2) + s_end_generate + "\n"
+ s_file = s_fileio_start + ent_qsys.apply_indend(s_arch_file + s_fileio_eth_init + s_fileio_poll, 2) + s_end_generate + "\n"
# Make QSYS master
s_master_start = s_master_header + "gen_" + ent_qsys.name + " : IF g_sim = FALSE GENERATE\n"
- s_master = s_master_start + ent_qsys.apply_indend(ent_qsys.make_qsys_instance(mmm_conf.peripherals), 2) + s_end_generate + "\n"
+ s_master = s_master_start + ent_qsys.apply_indend(ent_qsys.make_qsys_instance(mmm_conf), 2) + s_end_generate + "\n"
- s_arch_total = s_arch_begin + ent_qsys.apply_indend(s_arch_content + s_file + s_master, 2) + s_arch_end
- string_elements = [s_header, s_libraries, s_entity, s_arch_header, s_arch_total ]
+ s_arch_total = s_arch_begin + ent_qsys.apply_indend(s_file + s_master, 2) + s_arch_end
+ string_elements = [s_header, s_instantiation, s_libraries, s_entity, s_arch_header, s_arch_total ]
###################################
# Write the whole string to a file
###################################
- f = file(mmm_conf.VhdlFileName, "w")
+ fileName = mmm_conf.VhdlFilePath + mmm_conf.VhdlFileName
+ f = file(fileName, "w")
for s in string_elements:
f.write(s)
f.close()
--
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