diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index d81af35df4ab5f3cefa898b3df8664bbc1f4f821..4a1e54c46bed030a4ae613518e16590e61adf506 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -399,7 +399,7 @@ peripherals:
peripheral_group: ring_rx_bf
number_of_peripherals: c_N_beamsets
parameter_overrides:
- - { name: g_nof_streams, value: c_lane_nof_rx_monitors }
+ - { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_RING_RX_BF
@@ -407,7 +407,7 @@ peripherals:
peripheral_group: ring_tx_bf
number_of_peripherals: c_N_beamsets
parameter_overrides:
- - { name: g_nof_streams, value: c_lane_nof_tx_monitors }
+ - { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_RING_TX_BF
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
index 000138c5c188f46e1979d9d6ca447d8076b6f60f..4b6c9fffb9a9e31af03621f421bc35602d71864e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
@@ -34,7 +34,7 @@ number_of_columns = 13
- - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
+ - - - - design_note 0x00008014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00010000 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - -
@@ -542,7 +542,7 @@ number_of_columns = 13
- - - - latency 0x001a8008 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2
- - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - -
@@ -551,7 +551,7 @@ number_of_columns = 13
- - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - -
- - - - latency 0x001b8008 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - -
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
index bfc94ce8760a37cf31647ac9bbcaa952a8208549..285520e5ff934775956cbe638728d49176b2fa59 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
@@ -34,53 +34,53 @@ number_of_columns = 13
- - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
+ - - - - design_note 0x00000014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043498 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00043450 6 RO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x000432b8 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00043270 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
- AVS_ETH_0_REG 1 1 REG status 0x000433e0 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x000434c8 1 RO uint32 b[29:0] - - -
- - - - - stable 0x000434c8 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x000434c8 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x000434c9 1 RW uint32 b[27:0] - - -
- - - - - edge 0x000434c9 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x000434ca 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x000434a0 1 WO uint32 b[31:0] - - -
- - - - - rden 0x000434a1 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x000434a2 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x000434a3 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x000434a4 1 WO uint32 b[0:0] - - -
- - - - - busy 0x000434a5 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x000434a6 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x000434e2 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x000434e0 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x000434de 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x000434df 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x000434dc 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x000434a8 1 WO uint32 b[31:0] - - -
- - - - - param 0x000434a9 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x000434aa 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x000434ab 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x000434ac 1 RO uint32 b[31:0] - - -
- - - - - data_in 0x000434ad 1 WO uint32 b[31:0] - - -
- - - - - busy 0x000434ae 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG block_period 0x00043440 1 RO uint32 b[15:0] - - -
- - - - - beam_repositioning_flag 0x00043441 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x00043442 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x00043443 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x00043444 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x00043445 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x00043446 1 RW uint32 b[0:0] - - -
- - - - - station_id 0x00043447 1 RW uint32 b[15:0] - - -
- REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x000434b4 1 RW uint32 b[0:0] - - -
- - - - - use_cable_to_next_rn 0x000434b5 1 RW uint32 b[0:0] - - -
- - - - - n_rn 0x000434b6 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x000434b7 1 RW uint32 b[7:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x000434d2 1 RW uint32 b[30:0] - - -
- - - - - reset 0x000434d2 1 RW uint32 b[31:31] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x000432e8 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x000432e8 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x000432e8 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x000432e9 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x000432e9 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x000432ea 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x000432c0 1 WO uint32 b[31:0] - - -
+ - - - - rden 0x000432c1 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x000432c2 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x000432c3 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x000432c4 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x000432c5 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x000432c6 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043302 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00043300 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x000432fe 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x000432ff 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x000432fc 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x000432c8 1 WO uint32 b[31:0] - - -
+ - - - - param 0x000432c9 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x000432ca 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x000432cb 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x000432cc 1 RO uint32 b[31:0] - - -
+ - - - - data_in 0x000432cd 1 WO uint32 b[31:0] - - -
+ - - - - busy 0x000432ce 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x00043260 1 RO uint32 b[15:0] - - -
+ - - - - beam_repositioning_flag 0x00043261 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x00043262 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x00043263 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x00043264 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x00043265 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x00043266 1 RW uint32 b[0:0] - - -
+ - - - - station_id 0x00043267 1 RW uint32 b[15:0] - - -
+ REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x000432d4 1 RW uint32 b[0:0] - - -
+ - - - - use_cable_to_next_rn 0x000432d5 1 RW uint32 b[0:0] - - -
+ - - - - n_rn 0x000432d6 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x000432d7 1 RW uint32 b[7:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x000432f2 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x000432f2 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - -
@@ -118,47 +118,47 @@ number_of_columns = 13
- - - - rx_status5 0x0004203d 1 RW uint32 b[15:0] - - -
- - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x000433c0 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043490 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x00043490 1 RW uint32 b[1:1] - - -
- - - - - nof_clk_per_sync 0x00043491 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x00043492 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043493 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x00043494 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x000434d8 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000434d9 - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00043000 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00043000 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043000 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043002 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043003 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043004 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043005 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00043006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043007 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00043008 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x00043280 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x00043280 1 RW uint32 b[31:16] - - -
- - - - - phase 0x00043281 1 RW uint32 b[15:0] - - -
- - - - - freq 0x00043282 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x00043283 1 RW uint32 b[16:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x000431c0 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x000432b0 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x000432b0 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x000432b1 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x000432b2 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000432b3 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x000432b4 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x000432f8 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000432f9 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x00043080 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x00043080 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x00043081 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x00043082 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x00043083 1 RW uint32 b[16:0] - - -
RAM_WG 1 12 RAM data 0x00034000 1024 RW uint32 b[17:0] - - 1024
RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x000432c0 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x000432c1 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x000432c2 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x000432c3 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x000433a0 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x000433a1 1 RO uint32 b[31:0] - - -
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x000430c0 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x000430c1 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x000430c2 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x000430c3 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x000431a0 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x000431a1 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
- REG_SI 1 1 REG enable 0x000434da 1 RW uint32 b[0:0] - - -
+ REG_SI 1 1 REG enable 0x000432fa 1 RW uint32 b[0:0] - - -
RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x000434d6 1 RW uint32 b[0:0] - - -
+ REG_DP_SELECTOR 1 1 REG input_select 0x000432f6 1 RW uint32 b[0:0] - - -
RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x000434d0 1 RW uint32 b[0:0] - - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x000432f0 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
@@ -205,36 +205,36 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
- REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00043470 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00043470 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043470 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043471 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043472 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043473 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043474 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043475 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043478 1 RO uint32 b[31:0] - - -
- REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00043420 1 RW uint32 b[0:0] - - -
- - - - - ctrl_interval_size 0x00043421 1 RW uint32 b[30:0] - - -
- - - - - ctrl_start_bsn 0x00043422 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043423 - - - b[31:0] b[63:32] - -
- - - - - mon_current_input_bsn 0x00043424 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043425 - - - b[31:0] b[63:32] - -
- - - - - mon_input_bsn_at_sync 0x00043426 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043427 - - - b[31:0] b[63:32] - -
- - - - - mon_output_enable 0x00043428 1 RO uint32 b[0:0] - - -
- - - - - mon_output_sync_bsn 0x00043429 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004342a - - - b[31:0] b[63:32] - -
- - - - - block_size 0x0004342b 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00043290 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043290 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043290 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043291 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043292 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043293 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043294 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043295 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043298 1 RO uint32 b[31:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00043240 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x00043241 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x00043242 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043243 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x00043244 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043245 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x00043246 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043247 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x00043248 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x00043249 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004324a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x0004324b 1 RO uint32 b[31:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00010001 - - - b[31:0] b[63:32] - -
- - - - - 0x00010002 - - - b[31:0] b[95:64] - -
- - - - - 0x00010003 - - - b[31:0] b[127:96] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x00043430 15 RW uint32 b[31:0] - - -
- - - - - step 0x0004343f 1 RW uint32 b[31:0] - - -
- REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x000434cc 1 RW uint32 b[31:0] - - -
- - - - - unused 0x000434cd 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x000434ce 1 RW uint32 b[0:0] - - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00043250 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0004325f 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x000432ec 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x000432ed 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x000432ee 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
@@ -283,35 +283,35 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0000006a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
- REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043380 1 RW uint32 b[0:0] - - 2
- - - - - replaced_pkt_cnt 0x00043381 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00043100 1 RO uint32 b[0:0] - - 8
- - - - - ready_stable 0x00043100 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043100 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043102 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043103 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043104 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043105 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043108 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00043488 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00043488 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043488 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043489 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004348a - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x0004348b 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x0004348c 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x0004348d 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043490 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00043480 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00043480 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043480 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043481 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043482 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043483 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043484 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043485 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043488 1 RO uint32 b[31:0] - - -
+ REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043180 1 RW uint32 b[0:0] - - 2
+ - - - - replaced_pkt_cnt 0x00043181 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - - 8
+ - - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000d02 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x000432a8 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x000432a8 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000432a8 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000432a9 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000432aa - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000432ab 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000432ac 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000432ad 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000432b0 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x000432a0 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x000432a0 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000432a0 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000432a1 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000432a2 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000432a3 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000432a4 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000432a5 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000432a8 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - -
- - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8
@@ -332,13 +332,13 @@ number_of_columns = 13
- - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000088 1 RO uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043410 8 RO uint32 b[31:0] - - -
- - - - - total_discarded_blocks 0x00043418 1 RO uint32 b[31:0] - - -
- - - - - total_block_count 0x00043419 1 RO uint32 b[31:0] - - -
- - - - - clear 0x0004341a 1 RW uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x000434b8 1 RO uint32 b[31:0] - - -
- - - - - nof_sync 0x000434b9 1 RO uint32 b[31:0] - - -
- - - - - clear 0x000434ba 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043230 8 RO uint32 b[31:0] - - -
+ - - - - total_discarded_blocks 0x00043238 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x00043239 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0004323a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x000432d8 1 RO uint32 b[31:0] - - -
+ - - - - nof_sync 0x000432d9 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x000432da 1 RW uint32 b[31:0] - - -
REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - -
@@ -515,13 +515,13 @@ number_of_columns = 13
- - - - - 0x00021c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00021c3d - - - b[31:0] b[31:0] - -
- REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043478 1 RO uint32 b[0:0] - - 1
- - - - - xgmii_tx_ready 0x00043478 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x00043478 1 RO uint32 b[3:2] - - -
+ REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043298 1 RO uint32 b[0:0] - - 1
+ - - - - xgmii_tx_ready 0x00043298 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00043298 1 RO uint32 b[3:2] - - -
RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024
RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00043460 1 RW uint32 b[0:0] - 1 2
- - - - - replaced_pkt_cnt 0x00043461 1 RO uint32 b[31:0] - - -
+ REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00043288 1 RW uint32 b[0:0] - 1 2
+ - - - - replaced_pkt_cnt 0x00043289 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000c20 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c20 1 RO uint32 b[2:2] - - -
@@ -531,154 +531,154 @@ number_of_columns = 13
- - - - nof_valid 0x00000c24 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c25 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c28 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00000c10 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00000c10 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000c10 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000c11 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c12 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000c13 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000c14 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000c15 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000c18 1 RO uint32 b[31:0] - - -
- REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x00000c04 1 RO uint32 b[0:0] - 1 2
- - - - - transport_nof_hops 0x00000c05 1 RW uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000d02 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00043200 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043200 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043200 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043201 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043202 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043203 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043204 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043205 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043208 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x000432d0 1 RO uint32 b[0:0] - 1 2
+ - - - - transport_nof_hops 0x000432d1 1 RW uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x000431f0 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x000431f0 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000431f0 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000431f1 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431f2 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000431f3 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000431f4 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000431f5 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000431f8 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x000431e0 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x000431e0 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000431e0 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000431e1 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431e2 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000431e3 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000431e4 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000431e5 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000431e8 1 RO uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 1 16
- - - - total_discarded_blocks 0x00000028 1 RO uint32 b[31:0] - - -
- - - - total_block_count 0x00000029 1 RO uint32 b[31:0] - - -
- - - - clear 0x0000002a 1 RW uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00000c08 1 RO uint32 b[31:0] - 1 4
- - - - - nof_sync 0x00000c09 1 RO uint32 b[31:0] - - -
- - - - - clear 0x00000c0a 1 RW uint32 b[31:0] - - -
- REG_BF_SCALE 2 1 REG scale 0x000434c4 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x000434c5 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x00043200 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00043201 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00043202 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x00043203 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x00043204 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x00043205 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x00043206 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x00043207 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043208 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x00043209 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0004320a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0004320b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0004320c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0004320d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0004320e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0004320f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00043210 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00043211 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00043212 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00043213 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00043214 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00043215 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00043216 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00043217 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00043218 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00043219 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0004321a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0004321b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0004321c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0004321d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0004321e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0004321f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00043220 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00043221 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00043222 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00043223 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00043224 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00043225 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00043226 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043227 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00043228 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043229 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x000434c0 1 RW uint32 b[0:0] - 2 2
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00043280 1 RO uint32 b[31:0] - 1 4
+ - - - - nof_sync 0x00043281 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x00043282 1 RW uint32 b[31:0] - - -
+ REG_BF_SCALE 2 1 REG scale 0x000432e4 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x000432e5 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00043000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00043001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00043002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00043003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00043004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00043005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00043006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00043007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00043009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0004300a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0004300b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004300c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004300d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004300e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004300f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00043010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00043011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00043012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00043013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00043014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00043015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00043016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00043017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00043018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00043019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004301a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004301b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004301c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004301d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004301e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004301f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00043020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00043021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00043022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00043023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00043024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00043025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00043026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00043028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x000432e0 1 RW uint32 b[0:0] - 2 2
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00001001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x000434bc 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00043180 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00043181 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00043182 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00043183 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00043184 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00043185 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00043186 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x00043186 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x00043186 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x00043187 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00043188 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00043189 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0004318a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_weighted_subbands_flag 0x0004318b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0004318c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0004318d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0004318e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0004318f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00043190 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00043191 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00043192 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00043193 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00043194 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00043195 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00043196 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00043197 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00043198 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00043199 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0004319a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0004319b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0004319c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0004319d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0004319e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0004319f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x000431a0 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x000431a1 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x000431a2 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x000431a3 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x000431a4 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x000431a5 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x000431a6 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x000431a7 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431a8 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x000431a9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431aa - - - b[15:0] b[47:32] - -
- - - - - word_align 0x000431ab 1 RW uint32 b[15:0] - - -
- REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043400 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00043400 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043400 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043401 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043402 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043403 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043404 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043405 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043408 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x000433f0 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x000433f0 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x000433f0 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x000433f1 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000433f2 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x000433f3 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x000433f4 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x000433f5 1 RO uint32 b[31:0] - - -
- - - - - latency 0x000433f8 1 RO uint32 b[31:0] - - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x000432dc 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000d80 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00000d81 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000d82 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000d83 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000d84 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000d85 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000d86 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00000d86 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00000d86 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00000d87 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000d88 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000d89 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x00000d8a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x00000d8b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x00000d8c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000d8d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000d8e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000d8f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000d90 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000d91 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000d92 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000d93 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000d94 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000d95 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000d96 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000d97 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000d98 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000d99 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000d9a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000d9b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000d9c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000d9d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000d9e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000d9f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000da0 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000da1 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000da2 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000da3 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000da4 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000da5 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000da6 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000da7 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000da8 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000da9 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000daa - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x00000dab 1 RW uint32 b[15:0] - - -
+ REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043220 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043220 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043220 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043221 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043222 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043223 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043224 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043225 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043228 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00043210 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043210 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043210 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043211 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043212 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043213 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043214 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043215 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043218 1 RO uint32 b[31:0] - - -
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
- - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
@@ -855,6 +855,6 @@ number_of_columns = 13
- - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x000434d4 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x000434d4 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x000434d4 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x000432f4 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x000432f4 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x000432f4 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index f1f05baafbd66243f24abbd85ec4da4299f1c00c..315748f4e8d056f843cd3507837d5e3b8d3116af 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10CC00' end='0x10CD00' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10CD00' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CE00' end='0x10CE80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CE80' end='0x10CF00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CF00' end='0x10CF80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CF80' end='0x10CFC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CFC0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10D000' end='0x10D040' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10D040' end='0x10D080' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10D080' end='0x10D0C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10D0C0' end='0x10D100' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10D100' end='0x10D140' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10D140' end='0x10D180' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10D180' end='0x10D1A0' datawidth='32' /><slave name='timer_0.s1' start='0x10D1A0' end='0x10D1C0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10D1C0' end='0x10D1E0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10D1E0' end='0x10D200' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D200' end='0x10D220' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D220' end='0x10D240' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D240' end='0x10D260' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D260' end='0x10D280' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D280' end='0x10D2A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D2A0' end='0x10D2C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D2C0' end='0x10D2D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D2D0' end='0x10D2E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D2E0' end='0x10D2F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D2F0' end='0x10D300' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D300' end='0x10D310' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D310' end='0x10D320' datawidth='32' /><slave name='pio_pps.mem' start='0x10D320' end='0x10D330' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D330' end='0x10D338' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D338' end='0x10D340' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D340' end='0x10D348' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D348' end='0x10D350' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D350' end='0x10D358' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D358' end='0x10D360' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D360' end='0x10D368' datawidth='32' /><slave name='reg_si.mem' start='0x10D368' end='0x10D370' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D370' end='0x10D378' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D378' end='0x10D380' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D380' end='0x10D388' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D388' end='0x10D390' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D390' end='0x10D398' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10CC00' end='0x10CD00' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10CD00' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CE00' end='0x10CE80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CE80' end='0x10CF00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CF00' end='0x10CF80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CF80' end='0x10CFC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CFC0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10D000' end='0x10D040' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10D040' end='0x10D080' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10D080' end='0x10D0C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10D0C0' end='0x10D100' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10D100' end='0x10D140' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10D140' end='0x10D180' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10D180' end='0x10D1A0' datawidth='32' /><slave name='timer_0.s1' start='0x10D1A0' end='0x10D1C0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10D1C0' end='0x10D1E0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10D1E0' end='0x10D200' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D200' end='0x10D220' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D220' end='0x10D240' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D240' end='0x10D260' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D260' end='0x10D280' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D280' end='0x10D2A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D2A0' end='0x10D2C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D2C0' end='0x10D2D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D2D0' end='0x10D2E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D2E0' end='0x10D2F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D2F0' end='0x10D300' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D300' end='0x10D310' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D310' end='0x10D320' datawidth='32' /><slave name='pio_pps.mem' start='0x10D320' end='0x10D330' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D330' end='0x10D338' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D338' end='0x10D340' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D340' end='0x10D348' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D348' end='0x10D350' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D350' end='0x10D358' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D358' end='0x10D360' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D360' end='0x10D368' datawidth='32' /><slave name='reg_si.mem' start='0x10D368' end='0x10D370' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D370' end='0x10D378' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D378' end='0x10D380' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D380' end='0x10D388' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D388' end='0x10D390' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D390' end='0x10D398' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
index 9a7f8d8df10e5068ef1d11ad2d442e8d2d12433c..e03b1af11b07cb1604ed451d2755134f83129e48 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">1024</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>7</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>7</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">8</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
index 8e01451caf0cf229c34d10c1bd3b4530611e30a2..b1de8a539b14a5fdd880a57ad51fd1e44e2ce282 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">1024</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>7</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>7</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">8</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index c1ca3431cd546ea3828beb71d0d9d948b6cb7487..3af0670df7e000d7e6e95a9c15e6c7dcd2b7eeeb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -30,7 +30,7 @@
{
datum baseAddress
{
- value = "1101696";
+ value = "12352";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "1102736";
+ value = "1100816";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "1102664";
+ value = "1100744";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "1102624";
+ value = "1100704";
type = "String";
}
}
@@ -202,7 +202,7 @@
{
datum baseAddress
{
- value = "1102528";
+ value = "12304";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "1100544";
+ value = "1098496";
type = "String";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "1102608";
+ value = "1100688";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "1102208";
+ value = "1100320";
type = "String";
}
}
@@ -442,7 +442,7 @@
{
datum baseAddress
{
- value = "1101312";
+ value = "1099264";
type = "String";
}
}
@@ -458,7 +458,7 @@
{
datum baseAddress
{
- value = "1097728";
+ value = "1024";
type = "String";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "1099776";
type = "String";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "1102368";
+ value = "1100448";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "1101760";
+ value = "1099840";
type = "String";
}
}
@@ -522,7 +522,7 @@
{
datum baseAddress
{
- value = "1101824";
+ value = "1099904";
type = "String";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "13312";
+ value = "1099712";
type = "String";
}
}
@@ -570,7 +570,7 @@
{
datum baseAddress
{
- value = "1024";
+ value = "1099648";
type = "String";
}
}
@@ -618,7 +618,7 @@
{
datum baseAddress
{
- value = "1098752";
+ value = "13312";
type = "String";
}
}
@@ -634,7 +634,7 @@
{
datum baseAddress
{
- value = "1102272";
+ value = "1100352";
type = "String";
}
}
@@ -650,7 +650,7 @@
{
datum baseAddress
{
- value = "1102336";
+ value = "1100416";
type = "String";
}
}
@@ -666,7 +666,7 @@
{
datum baseAddress
{
- value = "1102688";
+ value = "1100768";
type = "String";
}
}
@@ -682,7 +682,7 @@
{
datum baseAddress
{
- value = "1102400";
+ value = "1100480";
type = "String";
}
}
@@ -698,7 +698,7 @@
{
datum baseAddress
{
- value = "1101952";
+ value = "1100032";
type = "String";
}
}
@@ -714,7 +714,7 @@
{
datum baseAddress
{
- value = "1102016";
+ value = "1100096";
type = "String";
}
}
@@ -730,7 +730,7 @@
{
datum baseAddress
{
- value = "1101440";
+ value = "1099392";
type = "String";
}
}
@@ -746,7 +746,7 @@
{
datum baseAddress
{
- value = "12320";
+ value = "1100288";
type = "String";
}
}
@@ -762,7 +762,7 @@
{
datum baseAddress
{
- value = "1102560";
+ value = "1100640";
type = "String";
}
}
@@ -794,7 +794,7 @@
{
datum baseAddress
{
- value = "1101888";
+ value = "1099968";
type = "String";
}
}
@@ -810,7 +810,7 @@
{
datum baseAddress
{
- value = "1102680";
+ value = "1100760";
type = "String";
}
}
@@ -826,7 +826,7 @@
{
datum baseAddress
{
- value = "1101568";
+ value = "1099520";
type = "String";
}
}
@@ -842,7 +842,7 @@
{
datum baseAddress
{
- value = "1102592";
+ value = "1100672";
type = "String";
}
}
@@ -863,7 +863,7 @@
{
datum baseAddress
{
- value = "1102728";
+ value = "1100808";
type = "String";
}
}
@@ -884,7 +884,7 @@
{
datum baseAddress
{
- value = "1102720";
+ value = "1100800";
type = "String";
}
}
@@ -905,7 +905,7 @@
{
datum baseAddress
{
- value = "1102464";
+ value = "1100544";
type = "String";
}
}
@@ -921,7 +921,7 @@
{
datum baseAddress
{
- value = "1102432";
+ value = "1100512";
type = "String";
}
}
@@ -942,7 +942,7 @@
{
datum baseAddress
{
- value = "1102144";
+ value = "1100224";
type = "String";
}
}
@@ -958,7 +958,7 @@
{
datum baseAddress
{
- value = "1099776";
+ value = "1097728";
type = "String";
}
}
@@ -979,7 +979,7 @@
{
datum baseAddress
{
- value = "1102712";
+ value = "1100792";
type = "String";
}
}
@@ -1000,7 +1000,7 @@
{
datum baseAddress
{
- value = "1102704";
+ value = "1100784";
type = "String";
}
}
@@ -1016,7 +1016,7 @@
{
datum baseAddress
{
- value = "1102640";
+ value = "1100720";
type = "String";
}
}
@@ -1032,7 +1032,7 @@
{
datum baseAddress
{
- value = "1102672";
+ value = "1100752";
type = "String";
}
}
@@ -1069,7 +1069,7 @@
{
datum baseAddress
{
- value = "1102496";
+ value = "1100576";
type = "String";
}
}
@@ -1085,7 +1085,7 @@
{
datum baseAddress
{
- value = "1102544";
+ value = "1100624";
type = "String";
}
}
@@ -1101,7 +1101,7 @@
{
datum baseAddress
{
- value = "12304";
+ value = "1100608";
type = "String";
}
}
@@ -1133,7 +1133,7 @@
{
datum baseAddress
{
- value = "1102080";
+ value = "1100160";
type = "String";
}
}
@@ -1149,7 +1149,7 @@
{
datum baseAddress
{
- value = "1102696";
+ value = "1100776";
type = "String";
}
}
@@ -1165,7 +1165,7 @@
{
datum baseAddress
{
- value = "1102576";
+ value = "1100656";
type = "String";
}
}
@@ -1181,7 +1181,7 @@
{
datum baseAddress
{
- value = "1102656";
+ value = "1100736";
type = "String";
}
}
@@ -1197,7 +1197,7 @@
{
datum baseAddress
{
- value = "1102648";
+ value = "1100728";
type = "String";
}
}
@@ -1213,7 +1213,7 @@
{
datum baseAddress
{
- value = "1099264";
+ value = "13824";
type = "String";
}
}
@@ -1261,7 +1261,7 @@
{
datum baseAddress
{
- value = "1102304";
+ value = "1100384";
type = "String";
}
}
@@ -1293,7 +1293,7 @@
{
datum baseAddress
{
- value = "1100800";
+ value = "1098752";
type = "String";
}
}
@@ -1309,7 +1309,7 @@
{
datum baseAddress
{
- value = "1101056";
+ value = "1099008";
type = "String";
}
}
@@ -1351,7 +1351,7 @@
{
datum baseAddress
{
- value = "1100288";
+ value = "1098240";
type = "String";
}
}
@@ -1393,7 +1393,7 @@
{
datum baseAddress
{
- value = "1102240";
+ value = "12320";
type = "String";
}
}
@@ -7029,7 +7029,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10CC00' end='0x10CD00' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10CD00' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CE00' end='0x10CE80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CE80' end='0x10CF00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CF00' end='0x10CF80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CF80' end='0x10CFC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CFC0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10D000' end='0x10D040' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10D040' end='0x10D080' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10D080' end='0x10D0C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10D0C0' end='0x10D100' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10D100' end='0x10D140' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10D140' end='0x10D180' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10D180' end='0x10D1A0' datawidth='32' /><slave name='timer_0.s1' start='0x10D1A0' end='0x10D1C0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10D1C0' end='0x10D1E0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10D1E0' end='0x10D200' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D200' end='0x10D220' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D220' end='0x10D240' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D240' end='0x10D260' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D260' end='0x10D280' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D280' end='0x10D2A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D2A0' end='0x10D2C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D2C0' end='0x10D2D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D2D0' end='0x10D2E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D2E0' end='0x10D2F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D2F0' end='0x10D300' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D300' end='0x10D310' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D310' end='0x10D320' datawidth='32' /><slave name='pio_pps.mem' start='0x10D320' end='0x10D330' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D330' end='0x10D338' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D338' end='0x10D340' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D340' end='0x10D348' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D348' end='0x10D350' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D350' end='0x10D358' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D358' end='0x10D360' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D360' end='0x10D368' datawidth='32' /><slave name='reg_si.mem' start='0x10D368' end='0x10D370' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D370' end='0x10D378' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D378' end='0x10D380' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D380' end='0x10D388' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D388' end='0x10D390' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D390' end='0x10D398' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -23852,7 +23852,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23916,7 +23916,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23985,7 +23985,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24391,11 +24391,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25084,7 +25084,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25148,7 +25148,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25217,7 +25217,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25623,11 +25623,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -55364,7 +55364,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x0010d390" />
+ <parameter name="baseAddress" value="0x0010cc10" />
</connection>
<connection
kind="avalon"
@@ -55378,7 +55378,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="baseAddress" value="0x0010cd00" />
+ <parameter name="baseAddress" value="0x0010c500" />
</connection>
<connection
kind="avalon"
@@ -55399,7 +55399,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x0010d320" />
+ <parameter name="baseAddress" value="0x0010cba0" />
</connection>
<connection
kind="avalon"
@@ -55413,63 +55413,63 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x0010d2a0" />
+ <parameter name="baseAddress" value="0x0010cb20" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x0010d280" />
+ <parameter name="baseAddress" value="0x0010cb00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x0010d388" />
+ <parameter name="baseAddress" value="0x0010cc08" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x0010d380" />
+ <parameter name="baseAddress" value="0x0010cc00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x0010d378" />
+ <parameter name="baseAddress" value="0x0010cbf8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x0010d370" />
+ <parameter name="baseAddress" value="0x0010cbf0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x0010d260" />
+ <parameter name="baseAddress" value="0x0010cae0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_unb_pmbus.mem">
- <parameter name="baseAddress" value="0x0010cc00" />
+ <parameter name="baseAddress" value="0x0010c400" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x0010d140" />
+ <parameter name="baseAddress" value="0x0010c9c0" />
</connection>
<connection
kind="avalon"
@@ -55483,7 +55483,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x0010d368" />
+ <parameter name="baseAddress" value="0x0010cbe8" />
</connection>
<connection
kind="avalon"
@@ -55504,7 +55504,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x0010cb00" />
+ <parameter name="baseAddress" value="0x0010c300" />
</connection>
<connection
kind="avalon"
@@ -55518,35 +55518,35 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_shiftram.mem">
- <parameter name="baseAddress" value="0x0010cf00" />
+ <parameter name="baseAddress" value="0x0010c700" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x0010d360" />
+ <parameter name="baseAddress" value="0x0010cbe0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x0010d240" />
+ <parameter name="baseAddress" value="0x0010cac0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_wg.mem">
- <parameter name="baseAddress" value="0x0010ca00" />
+ <parameter name="baseAddress" value="0x0010c200" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_input.mem">
- <parameter name="baseAddress" value="0x0010c000" />
+ <parameter name="baseAddress" value="0x0400" />
</connection>
<connection
kind="avalon"
@@ -55560,7 +55560,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x0010d358" />
+ <parameter name="baseAddress" value="0x0010cbd8" />
</connection>
<connection
kind="avalon"
@@ -55588,21 +55588,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x0010d310" />
+ <parameter name="baseAddress" value="0x0010cb90" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
- <parameter name="baseAddress" value="0x0010c800" />
+ <parameter name="baseAddress" value="0x0010c000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x0010d300" />
+ <parameter name="baseAddress" value="0x0010cb80" />
</connection>
<connection
kind="avalon"
@@ -55616,14 +55616,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x0010d100" />
+ <parameter name="baseAddress" value="0x0010c980" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x0010d350" />
+ <parameter name="baseAddress" value="0x0010cbd0" />
</connection>
<connection
kind="avalon"
@@ -55637,7 +55637,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_diag_data_buffer_bsn.mem">
- <parameter name="baseAddress" value="0x0010ce80" />
+ <parameter name="baseAddress" value="0x0010c680" />
</connection>
<connection
kind="avalon"
@@ -55651,14 +55651,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x0010d348" />
+ <parameter name="baseAddress" value="0x0010cbc8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x0010d340" />
+ <parameter name="baseAddress" value="0x0010cbc0" />
</connection>
<connection
kind="avalon"
@@ -55672,21 +55672,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
- <parameter name="baseAddress" value="0x0010d2f0" />
+ <parameter name="baseAddress" value="0x0010cb70" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_hdr_dat_bst.mem">
- <parameter name="baseAddress" value="0x0010c600" />
+ <parameter name="baseAddress" value="0x3600" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x0010d0c0" />
+ <parameter name="baseAddress" value="0x0010c940" />
</connection>
<connection
kind="avalon"
@@ -55700,7 +55700,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
- <parameter name="baseAddress" value="0x0010d338" />
+ <parameter name="baseAddress" value="0x0010cbb8" />
</connection>
<connection
kind="avalon"
@@ -55714,7 +55714,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
- <parameter name="baseAddress" value="0x0010d080" />
+ <parameter name="baseAddress" value="0x0010c900" />
</connection>
<connection
kind="avalon"
@@ -55728,35 +55728,35 @@
version="18.0"
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
- <parameter name="baseAddress" value="0x0010d330" />
+ <parameter name="baseAddress" value="0x0010cbb0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_align_v2_xsub.mem">
- <parameter name="baseAddress" value="0x0010ce00" />
+ <parameter name="baseAddress" value="0x0010c600" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_rx_align_xsub.mem">
- <parameter name="baseAddress" value="0x0010c400" />
+ <parameter name="baseAddress" value="0x3400" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_xsub.mem">
- <parameter name="baseAddress" value="0x0010d220" />
+ <parameter name="baseAddress" value="0x0010caa0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_xst_offload.mem">
- <parameter name="baseAddress" value="0x0010d200" />
+ <parameter name="baseAddress" value="0x0010ca80" />
</connection>
<connection
kind="avalon"
@@ -55784,28 +55784,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
- <parameter name="baseAddress" value="0x0010d040" />
+ <parameter name="baseAddress" value="0x0010c8c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
- <parameter name="baseAddress" value="0x0010d2e0" />
+ <parameter name="baseAddress" value="0x0010cb60" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_info.mem">
- <parameter name="baseAddress" value="0x0010d2d0" />
+ <parameter name="baseAddress" value="0x0010cb50" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_tr_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x0010d1e0" />
+ <parameter name="baseAddress" value="0x0010ca60" />
</connection>
<connection
kind="avalon"
@@ -55819,28 +55819,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_sst_offload.mem">
- <parameter name="baseAddress" value="0x0010d1c0" />
+ <parameter name="baseAddress" value="0x0010ca40" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_bst_offload.mem">
- <parameter name="baseAddress" value="0x0010d000" />
+ <parameter name="baseAddress" value="0x0010c880" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_beamlet_output.mem">
- <parameter name="baseAddress" value="0x0010cfc0" />
+ <parameter name="baseAddress" value="0x0010c840" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_align_v2_bf.mem">
- <parameter name="baseAddress" value="0x0010d180" />
+ <parameter name="baseAddress" value="0x0010ca20" />
</connection>
<connection
kind="avalon"
@@ -55854,28 +55854,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_bf.mem">
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x0010c800" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_lane_info_bf.mem">
- <parameter name="baseAddress" value="0x3010" />
+ <parameter name="baseAddress" value="0x0010cb40" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx_bf.mem">
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x0010c7c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_tx_bf.mem">
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x0010c780" />
</connection>
<connection
kind="avalon"
@@ -55889,7 +55889,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_bf.mem">
- <parameter name="baseAddress" value="0x3020" />
+ <parameter name="baseAddress" value="0x0010ca00" />
</connection>
<connection
kind="avalon"
@@ -55903,7 +55903,7 @@
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
- <parameter name="baseAddress" value="0x0010cf80" />
+ <parameter name="baseAddress" value="0x3040" />
</connection>
<connection
kind="avalon"
@@ -55924,14 +55924,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_wdi.s1">
- <parameter name="baseAddress" value="0x0010d2c0" />
+ <parameter name="baseAddress" value="0x3010" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="timer_0.s1">
- <parameter name="baseAddress" value="0x0010d1a0" />
+ <parameter name="baseAddress" value="0x3020" />
</connection>
<connection
kind="avalon"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index db07ef0b19d1226822182895094b7cb64e2b3dbf..9537b5c59308a8b7f8dc686e7be8a8fb6945c730 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -217,7 +217,7 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
@@ -231,7 +231,7 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index 03e63ea22fe31b0eb7fc282bac32b9dcf305a75f..751f16099e932392bf770b5203193847d771ec5a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -399,7 +399,7 @@ peripherals:
peripheral_group: ring_rx_bf
number_of_peripherals: c_N_beamsets
parameter_overrides:
- - { name: g_nof_streams, value: c_lane_nof_rx_monitors }
+ - { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_RING_RX_BF
@@ -407,7 +407,7 @@ peripherals:
peripheral_group: ring_tx_bf
number_of_peripherals: c_N_beamsets
parameter_overrides:
- - { name: g_nof_streams, value: c_lane_nof_tx_monitors }
+ - { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_RING_TX_BF
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
index 7f34570bd94e1593b53bcac4633a5ec2b45dfc78..69273a6077bb1b683d940528b9ade583dd7d9423 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
@@ -34,7 +34,7 @@ number_of_columns = 13
- - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
+ - - - - design_note 0x00008014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00010000 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - -
@@ -542,7 +542,7 @@ number_of_columns = 13
- - - - latency 0x001a8008 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2
- - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - -
@@ -551,7 +551,7 @@ number_of_columns = 13
- - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - -
- - - - latency 0x001b8008 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - -
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
index b15cb41cfd1fe6f9e60fc8f13b65837b1335251b..c06a5a7ca701657c1967ecc67a5b1c705ca4b407 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
@@ -34,53 +34,53 @@ number_of_columns = 13
- - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
+ - - - - design_note 0x00000014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043418 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x000433d0 6 RO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043238 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x000431f0 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
- AVS_ETH_0_REG 1 1 REG status 0x00043360 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x00043448 1 RO uint32 b[29:0] - - -
- - - - - stable 0x00043448 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x00043448 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x00043449 1 RW uint32 b[27:0] - - -
- - - - - edge 0x00043449 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x0004344a 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x00043420 1 WO uint32 b[31:0] - - -
- - - - - rden 0x00043421 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x00043422 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x00043423 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x00043424 1 WO uint32 b[0:0] - - -
- - - - - busy 0x00043425 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x00043426 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043462 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x00043460 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x0004345e 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x0004345f 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x0004345c 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x00043428 1 WO uint32 b[31:0] - - -
- - - - - param 0x00043429 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x0004342a 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x0004342b 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x0004342c 1 RO uint32 b[31:0] - - -
- - - - - data_in 0x0004342d 1 WO uint32 b[31:0] - - -
- - - - - busy 0x0004342e 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG block_period 0x000433c0 1 RO uint32 b[15:0] - - -
- - - - - beam_repositioning_flag 0x000433c1 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x000433c2 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x000433c3 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x000433c4 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x000433c5 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x000433c6 1 RW uint32 b[0:0] - - -
- - - - - station_id 0x000433c7 1 RW uint32 b[15:0] - - -
- REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x00043434 1 RW uint32 b[0:0] - - -
- - - - - use_cable_to_next_rn 0x00043435 1 RW uint32 b[0:0] - - -
- - - - - n_rn 0x00043436 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x00043437 1 RW uint32 b[7:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x00043452 1 RW uint32 b[30:0] - - -
- - - - - reset 0x00043452 1 RW uint32 b[31:31] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x00043268 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x00043268 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x00043268 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x00043269 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x00043269 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x0004326a 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00043240 1 WO uint32 b[31:0] - - -
+ - - - - rden 0x00043241 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x00043242 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x00043243 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x00043244 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x00043245 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x00043246 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043282 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00043280 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x0004327e 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x0004327f 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x0004327c 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x00043248 1 WO uint32 b[31:0] - - -
+ - - - - param 0x00043249 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0004324a 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0004324b 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0004324c 1 RO uint32 b[31:0] - - -
+ - - - - data_in 0x0004324d 1 WO uint32 b[31:0] - - -
+ - - - - busy 0x0004324e 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x000431e0 1 RO uint32 b[15:0] - - -
+ - - - - beam_repositioning_flag 0x000431e1 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x000431e2 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x000431e3 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x000431e4 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x000431e5 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x000431e6 1 RW uint32 b[0:0] - - -
+ - - - - station_id 0x000431e7 1 RW uint32 b[15:0] - - -
+ REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x00043254 1 RW uint32 b[0:0] - - -
+ - - - - use_cable_to_next_rn 0x00043255 1 RW uint32 b[0:0] - - -
+ - - - - n_rn 0x00043256 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x00043257 1 RW uint32 b[7:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x00043272 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x00043272 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - -
@@ -118,47 +118,47 @@ number_of_columns = 13
- - - - rx_status5 0x0004203d 1 RW uint32 b[15:0] - - -
- - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00043340 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043410 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x00043410 1 RW uint32 b[1:1] - - -
- - - - - nof_clk_per_sync 0x00043411 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x00043412 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043413 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x00043414 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00043458 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043459 - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00043000 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00043000 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043000 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043002 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043003 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043004 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043005 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00043006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043007 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00043008 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x00043280 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x00043280 1 RW uint32 b[31:16] - - -
- - - - - phase 0x00043281 1 RW uint32 b[15:0] - - -
- - - - - freq 0x00043282 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x00043283 1 RW uint32 b[16:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00043140 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043230 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00043230 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x00043231 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00043232 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043233 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00043234 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00043278 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043279 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x00043080 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x00043080 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x00043081 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x00043082 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x00043083 1 RW uint32 b[16:0] - - -
RAM_WG 1 12 RAM data 0x00034000 1024 RW uint32 b[17:0] - - 1024
RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x000432c0 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x000432c1 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x000432c2 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x000432c3 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00043320 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x00043321 1 RO uint32 b[31:0] - - -
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x000430c0 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x000430c1 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x000430c2 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x000430c3 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00043120 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x00043121 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
- REG_SI 1 1 REG enable 0x0004345a 1 RW uint32 b[0:0] - - -
+ REG_SI 1 1 REG enable 0x0004327a 1 RW uint32 b[0:0] - - -
RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x00043456 1 RW uint32 b[0:0] - - -
+ REG_DP_SELECTOR 1 1 REG input_select 0x00043276 1 RW uint32 b[0:0] - - -
RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x00043450 1 RW uint32 b[0:0] - - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x00043270 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
@@ -205,36 +205,36 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
- REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x000433f0 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x000433f0 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x000433f0 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x000433f1 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000433f2 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x000433f3 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x000433f4 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x000433f5 1 RO uint32 b[31:0] - - -
- - - - - latency 0x000433f8 1 RO uint32 b[31:0] - - -
- REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000433a0 1 RW uint32 b[0:0] - - -
- - - - - ctrl_interval_size 0x000433a1 1 RW uint32 b[30:0] - - -
- - - - - ctrl_start_bsn 0x000433a2 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000433a3 - - - b[31:0] b[63:32] - -
- - - - - mon_current_input_bsn 0x000433a4 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000433a5 - - - b[31:0] b[63:32] - -
- - - - - mon_input_bsn_at_sync 0x000433a6 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000433a7 - - - b[31:0] b[63:32] - -
- - - - - mon_output_enable 0x000433a8 1 RO uint32 b[0:0] - - -
- - - - - mon_output_sync_bsn 0x000433a9 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000433aa - - - b[31:0] b[63:32] - -
- - - - - block_size 0x000433ab 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00043210 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043210 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043210 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043211 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043212 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043213 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043214 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043215 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043218 1 RO uint32 b[31:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000431c0 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x000431c1 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x000431c2 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431c3 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x000431c4 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431c5 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x000431c6 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431c7 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x000431c8 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x000431c9 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431ca - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x000431cb 1 RO uint32 b[31:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00010001 - - - b[31:0] b[63:32] - -
- - - - - 0x00010002 - - - b[31:0] b[95:64] - -
- - - - - 0x00010003 - - - b[31:0] b[127:96] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x000433b0 15 RW uint32 b[31:0] - - -
- - - - - step 0x000433bf 1 RW uint32 b[31:0] - - -
- REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x0004344c 1 RW uint32 b[31:0] - - -
- - - - - unused 0x0004344d 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x0004344e 1 RW uint32 b[0:0] - - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x000431d0 15 RW uint32 b[31:0] - - -
+ - - - - step 0x000431df 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x0004326c 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x0004326d 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x0004326e 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
@@ -283,8 +283,8 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0000006a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
- REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043300 1 RW uint32 b[0:0] - - 2
- - - - - replaced_pkt_cnt 0x00043301 1 RO uint32 b[31:0] - - -
+ REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043100 1 RW uint32 b[0:0] - - 2
+ - - - - replaced_pkt_cnt 0x00043101 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00000080 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00000080 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000080 1 RO uint32 b[2:2] - - -
@@ -294,35 +294,35 @@ number_of_columns = 13
- - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000088 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00043408 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00043408 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043408 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043409 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004340a - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x0004340b 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x0004340c 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x0004340d 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043410 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00043400 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00043400 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043400 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043401 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043402 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043403 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043404 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043405 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043408 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00043228 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043228 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043228 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043229 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004322a - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004322b 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004322c 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004322d 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043230 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00043220 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043220 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043220 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043221 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043222 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043223 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043224 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043225 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043228 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - -
- - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00043100 1 RO uint32 b[0:0] - - 8
- - - - - ready_stable 0x00043100 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043100 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043102 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043103 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043104 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043105 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043108 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - - 8
+ - - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000d02 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00000c80 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c80 1 RO uint32 b[2:2] - - -
@@ -332,13 +332,13 @@ number_of_columns = 13
- - - - nof_valid 0x00000c84 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c85 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c88 1 RO uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043390 8 RO uint32 b[31:0] - - -
- - - - - total_discarded_blocks 0x00043398 1 RO uint32 b[31:0] - - -
- - - - - total_block_count 0x00043399 1 RO uint32 b[31:0] - - -
- - - - - clear 0x0004339a 1 RW uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x00043438 1 RO uint32 b[31:0] - - -
- - - - - nof_sync 0x00043439 1 RO uint32 b[31:0] - - -
- - - - - clear 0x0004343a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x000431b0 8 RO uint32 b[31:0] - - -
+ - - - - total_discarded_blocks 0x000431b8 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x000431b9 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x000431ba 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x00043258 1 RO uint32 b[31:0] - - -
+ - - - - nof_sync 0x00043259 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0004325a 1 RW uint32 b[31:0] - - -
REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - -
@@ -515,13 +515,13 @@ number_of_columns = 13
- - - - - 0x00021c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00021c3d - - - b[31:0] b[31:0] - -
- REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x000433f8 1 RO uint32 b[0:0] - - 1
- - - - - xgmii_tx_ready 0x000433f8 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x000433f8 1 RO uint32 b[3:2] - - -
+ REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043218 1 RO uint32 b[0:0] - - 1
+ - - - - xgmii_tx_ready 0x00043218 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00043218 1 RO uint32 b[3:2] - - -
RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024
RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x000433e0 1 RW uint32 b[0:0] - 1 2
- - - - - replaced_pkt_cnt 0x000433e1 1 RO uint32 b[31:0] - - -
+ REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00043208 1 RW uint32 b[0:0] - 1 2
+ - - - - replaced_pkt_cnt 0x00043209 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000c20 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c20 1 RO uint32 b[2:2] - - -
@@ -531,154 +531,154 @@ number_of_columns = 13
- - - - nof_valid 0x00000c24 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c25 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c28 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00000c10 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00000c10 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000c10 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000c11 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c12 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000c13 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000c14 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000c15 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000c18 1 RO uint32 b[31:0] - - -
- REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x00000c04 1 RO uint32 b[0:0] - 1 2
- - - - - transport_nof_hops 0x00000c05 1 RW uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000d02 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00043180 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043180 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043180 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043181 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043182 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043183 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043184 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043185 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043188 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x00043250 1 RO uint32 b[0:0] - 1 2
+ - - - - transport_nof_hops 0x00043251 1 RW uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x00043170 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043170 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043170 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043171 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043172 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043173 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043174 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043175 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043178 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x00043160 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043160 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043160 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043161 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043162 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043163 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043164 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043165 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043168 1 RO uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 1 16
- - - - total_discarded_blocks 0x00000028 1 RO uint32 b[31:0] - - -
- - - - total_block_count 0x00000029 1 RO uint32 b[31:0] - - -
- - - - clear 0x0000002a 1 RW uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00000c08 1 RO uint32 b[31:0] - 1 4
- - - - - nof_sync 0x00000c09 1 RO uint32 b[31:0] - - -
- - - - - clear 0x00000c0a 1 RW uint32 b[31:0] - - -
- REG_BF_SCALE 2 1 REG scale 0x00043444 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x00043445 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x00043200 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00043201 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00043202 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x00043203 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x00043204 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x00043205 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x00043206 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x00043207 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043208 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x00043209 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0004320a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0004320b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0004320c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0004320d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0004320e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0004320f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00043210 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00043211 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00043212 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00043213 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00043214 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00043215 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00043216 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00043217 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00043218 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00043219 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0004321a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0004321b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0004321c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0004321d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0004321e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0004321f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00043220 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00043221 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00043222 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00043223 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00043224 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00043225 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00043226 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043227 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00043228 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043229 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x00043440 1 RW uint32 b[0:0] - 2 2
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00043200 1 RO uint32 b[31:0] - 1 4
+ - - - - nof_sync 0x00043201 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x00043202 1 RW uint32 b[31:0] - - -
+ REG_BF_SCALE 2 1 REG scale 0x00043264 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00043265 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00043000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00043001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00043002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00043003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00043004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00043005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00043006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00043007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00043009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0004300a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0004300b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004300c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004300d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004300e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004300f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00043010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00043011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00043012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00043013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00043014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00043015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00043016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00043017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00043018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00043019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004301a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004301b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004301c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004301d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004301e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004301f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00043020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00043021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00043022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00043023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00043024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00043025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00043026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00043028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x00043260 1 RW uint32 b[0:0] - 2 2
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00001001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x0004343c 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00043180 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00043181 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00043182 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00043183 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00043184 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00043185 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00043186 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x00043186 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x00043186 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x00043187 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00043188 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00043189 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0004318a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_weighted_subbands_flag 0x0004318b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0004318c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0004318d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0004318e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0004318f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00043190 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00043191 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00043192 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00043193 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00043194 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00043195 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00043196 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00043197 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00043198 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00043199 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0004319a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0004319b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0004319c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0004319d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0004319e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0004319f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x000431a0 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x000431a1 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x000431a2 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x000431a3 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x000431a4 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x000431a5 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x000431a6 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x000431a7 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431a8 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x000431a9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431aa - - - b[15:0] b[47:32] - -
- - - - - word_align 0x000431ab 1 RW uint32 b[15:0] - - -
- REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043380 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00043380 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043380 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043381 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043382 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043383 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043384 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043385 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043388 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00043370 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00043370 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043370 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043371 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043372 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043373 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043374 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043375 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043378 1 RO uint32 b[31:0] - - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x0004325c 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000d80 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00000d81 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000d82 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000d83 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000d84 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000d85 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000d86 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00000d86 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00000d86 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00000d87 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000d88 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000d89 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x00000d8a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x00000d8b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x00000d8c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000d8d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000d8e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000d8f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000d90 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000d91 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000d92 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000d93 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000d94 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000d95 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000d96 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000d97 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000d98 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000d99 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000d9a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000d9b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000d9c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000d9d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000d9e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000d9f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000da0 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000da1 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000da2 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000da3 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000da4 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000da5 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000da6 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000da7 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000da8 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000da9 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000daa - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x00000dab 1 RW uint32 b[15:0] - - -
+ REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x000431a0 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x000431a0 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000431a0 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000431a1 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431a2 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000431a3 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000431a4 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000431a5 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000431a8 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00043190 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043190 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043190 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043191 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043192 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043193 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043194 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043195 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043198 1 RO uint32 b[31:0] - - -
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
- - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
@@ -855,6 +855,6 @@ number_of_columns = 13
- - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00043454 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x00043454 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x00043454 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00043274 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00043274 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00043274 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
index 141c75ef1a08e4ba734a8b622fb3997ced78c182..27ebe7b474d4bf7c960fb007244ae1c1ce45f538 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CC00' end='0x10CC80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CC80' end='0x10CD00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CD00' end='0x10CD80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CD80' end='0x10CDC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CDC0' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10CE00' end='0x10CE40' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10CE40' end='0x10CE80' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10CE80' end='0x10CEC0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10CEC0' end='0x10CF00' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10CF00' end='0x10CF40' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10CF40' end='0x10CF80' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CF80' end='0x10CFA0' datawidth='32' /><slave name='timer_0.s1' start='0x10CFA0' end='0x10CFC0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CFC0' end='0x10CFE0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CFE0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D000' end='0x10D020' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D020' end='0x10D040' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D040' end='0x10D060' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D060' end='0x10D080' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D080' end='0x10D0A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D0A0' end='0x10D0C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D0C0' end='0x10D0D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D0D0' end='0x10D0E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D0E0' end='0x10D0F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D0F0' end='0x10D100' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D100' end='0x10D110' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D110' end='0x10D120' datawidth='32' /><slave name='pio_pps.mem' start='0x10D120' end='0x10D130' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D130' end='0x10D138' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D138' end='0x10D140' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D140' end='0x10D148' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D148' end='0x10D150' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D150' end='0x10D158' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D158' end='0x10D160' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D160' end='0x10D168' datawidth='32' /><slave name='reg_si.mem' start='0x10D168' end='0x10D170' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D170' end='0x10D178' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D178' end='0x10D180' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D180' end='0x10D188' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D188' end='0x10D190' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D190' end='0x10D198' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /><slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /><slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3589,7 +3589,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x10C400' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x10CC00' end='0x10CC80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x10CC80' end='0x10CD00' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10CD00' end='0x10CD80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x10CD80' end='0x10CDC0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CDC0' end='0x10CE00' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10CE00' end='0x10CE40' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10CE40' end='0x10CE80' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10CE80' end='0x10CEC0' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10CEC0' end='0x10CF00' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10CF00' end='0x10CF40' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10CF40' end='0x10CF80' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x10CF80' end='0x10CFA0' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x10CFA0' end='0x10CFC0' datawidth='16' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CFC0' end='0x10CFE0' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10CFE0' end='0x10D000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D000' end='0x10D020' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D020' end='0x10D040' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10D040' end='0x10D060' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10D060' end='0x10D080' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10D080' end='0x10D0A0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10D0A0' end='0x10D0C0' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x10D0C0' end='0x10D0D0' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10D0D0' end='0x10D0E0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D0E0' end='0x10D0F0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10D0F0' end='0x10D100' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10D100' end='0x10D110' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10D110' end='0x10D120' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10D120' end='0x10D130' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10D130' end='0x10D138' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10D138' end='0x10D140' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10D140' end='0x10D148' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10D148' end='0x10D150' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10D150' end='0x10D158' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10D158' end='0x10D160' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10D160' end='0x10D168' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10D168' end='0x10D170' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10D170' end='0x10D178' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10D178' end='0x10D180' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10D180' end='0x10D188' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10D188' end='0x10D190' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D190' end='0x10D198' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
index 3606904580dff38374f462b7ace6f5f5619be314..8e3f450531f1d536646dfeb6f83fcf0907041423 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>1024</ipxact:value>
+ <ipxact:value>64</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>7</ipxact:right>
+ <ipxact:right>3</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>7</ipxact:right>
+ <ipxact:right>3</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
+ <ipxact:value>4</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
index 80b7d3e2f45777c4710834eb2e19c881514b10aa..8546c4311a68c74ae8f8ec70aa476e015e244558 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>1024</ipxact:value>
+ <ipxact:value>64</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>7</ipxact:right>
+ <ipxact:right>3</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>7</ipxact:right>
+ <ipxact:right>3</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
+ <ipxact:value>4</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index 2e75dcd2bc2112f9245128b5a5df872dfb59304f..2f21adc476694f163bbf3133fbee6ce9e475035e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -30,7 +30,7 @@
{
datum baseAddress
{
- value = "1101184";
+ value = "12352";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "1102224";
+ value = "1100304";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "1102152";
+ value = "1100232";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "1102112";
+ value = "1100192";
type = "String";
}
}
@@ -202,7 +202,7 @@
{
datum baseAddress
{
- value = "1102016";
+ value = "12304";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "1100544";
+ value = "1098496";
type = "String";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "1102096";
+ value = "1100176";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "1101696";
+ value = "1099808";
type = "String";
}
}
@@ -442,7 +442,7 @@
{
datum baseAddress
{
- value = "1100800";
+ value = "1098752";
type = "String";
}
}
@@ -458,7 +458,7 @@
{
datum baseAddress
{
- value = "1097728";
+ value = "1024";
type = "String";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "1099264";
type = "String";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "1101856";
+ value = "1099936";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "1101248";
+ value = "1099328";
type = "String";
}
}
@@ -522,7 +522,7 @@
{
datum baseAddress
{
- value = "1101312";
+ value = "1099392";
type = "String";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "13312";
+ value = "1099200";
type = "String";
}
}
@@ -554,7 +554,7 @@
{
datum baseAddress
{
- value = "1098752";
+ value = "13312";
type = "String";
}
}
@@ -570,7 +570,7 @@
{
datum baseAddress
{
- value = "1024";
+ value = "1099136";
type = "String";
}
}
@@ -634,7 +634,7 @@
{
datum baseAddress
{
- value = "1101760";
+ value = "1099840";
type = "String";
}
}
@@ -650,7 +650,7 @@
{
datum baseAddress
{
- value = "1101824";
+ value = "1099904";
type = "String";
}
}
@@ -666,7 +666,7 @@
{
datum baseAddress
{
- value = "1102176";
+ value = "1100256";
type = "String";
}
}
@@ -682,7 +682,7 @@
{
datum baseAddress
{
- value = "1101888";
+ value = "1099968";
type = "String";
}
}
@@ -698,7 +698,7 @@
{
datum baseAddress
{
- value = "1101440";
+ value = "1099520";
type = "String";
}
}
@@ -714,7 +714,7 @@
{
datum baseAddress
{
- value = "1101504";
+ value = "1099584";
type = "String";
}
}
@@ -730,7 +730,7 @@
{
datum baseAddress
{
- value = "1100928";
+ value = "1098880";
type = "String";
}
}
@@ -746,7 +746,7 @@
{
datum baseAddress
{
- value = "12320";
+ value = "1099776";
type = "String";
}
}
@@ -762,7 +762,7 @@
{
datum baseAddress
{
- value = "1102048";
+ value = "1100128";
type = "String";
}
}
@@ -794,7 +794,7 @@
{
datum baseAddress
{
- value = "1101376";
+ value = "1099456";
type = "String";
}
}
@@ -810,7 +810,7 @@
{
datum baseAddress
{
- value = "1102168";
+ value = "1100248";
type = "String";
}
}
@@ -826,7 +826,7 @@
{
datum baseAddress
{
- value = "1101056";
+ value = "1099008";
type = "String";
}
}
@@ -842,7 +842,7 @@
{
datum baseAddress
{
- value = "1102080";
+ value = "1100160";
type = "String";
}
}
@@ -863,7 +863,7 @@
{
datum baseAddress
{
- value = "1102216";
+ value = "1100296";
type = "String";
}
}
@@ -884,7 +884,7 @@
{
datum baseAddress
{
- value = "1102208";
+ value = "1100288";
type = "String";
}
}
@@ -905,7 +905,7 @@
{
datum baseAddress
{
- value = "1101952";
+ value = "1100032";
type = "String";
}
}
@@ -921,7 +921,7 @@
{
datum baseAddress
{
- value = "1101920";
+ value = "1100000";
type = "String";
}
}
@@ -942,7 +942,7 @@
{
datum baseAddress
{
- value = "1101632";
+ value = "1099712";
type = "String";
}
}
@@ -958,7 +958,7 @@
{
datum baseAddress
{
- value = "1099776";
+ value = "1097728";
type = "String";
}
}
@@ -979,7 +979,7 @@
{
datum baseAddress
{
- value = "1102200";
+ value = "1100280";
type = "String";
}
}
@@ -1000,7 +1000,7 @@
{
datum baseAddress
{
- value = "1102192";
+ value = "1100272";
type = "String";
}
}
@@ -1016,7 +1016,7 @@
{
datum baseAddress
{
- value = "1102128";
+ value = "1100208";
type = "String";
}
}
@@ -1032,7 +1032,7 @@
{
datum baseAddress
{
- value = "1102160";
+ value = "1100240";
type = "String";
}
}
@@ -1069,7 +1069,7 @@
{
datum baseAddress
{
- value = "1101984";
+ value = "1100064";
type = "String";
}
}
@@ -1085,7 +1085,7 @@
{
datum baseAddress
{
- value = "1102032";
+ value = "1100112";
type = "String";
}
}
@@ -1101,7 +1101,7 @@
{
datum baseAddress
{
- value = "12304";
+ value = "1100096";
type = "String";
}
}
@@ -1133,7 +1133,7 @@
{
datum baseAddress
{
- value = "1101568";
+ value = "1099648";
type = "String";
}
}
@@ -1149,7 +1149,7 @@
{
datum baseAddress
{
- value = "1102184";
+ value = "1100264";
type = "String";
}
}
@@ -1165,7 +1165,7 @@
{
datum baseAddress
{
- value = "1102064";
+ value = "1100144";
type = "String";
}
}
@@ -1181,7 +1181,7 @@
{
datum baseAddress
{
- value = "1102144";
+ value = "1100224";
type = "String";
}
}
@@ -1197,7 +1197,7 @@
{
datum baseAddress
{
- value = "1102136";
+ value = "1100216";
type = "String";
}
}
@@ -1213,7 +1213,7 @@
{
datum baseAddress
{
- value = "1099264";
+ value = "13824";
type = "String";
}
}
@@ -1261,7 +1261,7 @@
{
datum baseAddress
{
- value = "1101792";
+ value = "1099872";
type = "String";
}
}
@@ -1319,7 +1319,7 @@
{
datum baseAddress
{
- value = "1100288";
+ value = "1098240";
type = "String";
}
}
@@ -1361,7 +1361,7 @@
{
datum baseAddress
{
- value = "1101728";
+ value = "12320";
type = "String";
}
}
@@ -8497,7 +8497,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CC00' end='0x10CC80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CC80' end='0x10CD00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CD00' end='0x10CD80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CD80' end='0x10CDC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CDC0' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10CE00' end='0x10CE40' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10CE40' end='0x10CE80' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10CE80' end='0x10CEC0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10CEC0' end='0x10CF00' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10CF00' end='0x10CF40' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10CF40' end='0x10CF80' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CF80' end='0x10CFA0' datawidth='32' /><slave name='timer_0.s1' start='0x10CFA0' end='0x10CFC0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CFC0' end='0x10CFE0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CFE0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D000' end='0x10D020' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D020' end='0x10D040' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D040' end='0x10D060' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D060' end='0x10D080' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D080' end='0x10D0A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D0A0' end='0x10D0C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D0C0' end='0x10D0D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D0D0' end='0x10D0E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D0E0' end='0x10D0F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D0F0' end='0x10D100' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D100' end='0x10D110' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D110' end='0x10D120' datawidth='32' /><slave name='pio_pps.mem' start='0x10D120' end='0x10D130' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D130' end='0x10D138' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D138' end='0x10D140' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D140' end='0x10D148' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D148' end='0x10D150' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D150' end='0x10D158' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D158' end='0x10D160' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D160' end='0x10D168' datawidth='32' /><slave name='reg_si.mem' start='0x10D168' end='0x10D170' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D170' end='0x10D178' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D178' end='0x10D180' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D180' end='0x10D188' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D188' end='0x10D190' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D190' end='0x10D198' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /><slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /><slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -40095,7 +40095,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40164,7 +40164,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40393,7 +40393,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40571,11 +40571,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -40675,7 +40675,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40744,7 +40744,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40973,7 +40973,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42377,7 +42377,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42446,7 +42446,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42675,7 +42675,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42853,11 +42853,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -42957,7 +42957,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42996,21 +42996,17 @@
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -43026,7 +43022,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43050,7 +43046,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -43255,7 +43250,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -96093,7 +96088,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d190" />
+ <parameter name="baseAddress" value="0x0010ca10" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96173,7 +96168,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d120" />
+ <parameter name="baseAddress" value="0x0010c9a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96213,7 +96208,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d0a0" />
+ <parameter name="baseAddress" value="0x0010c920" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96233,7 +96228,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d080" />
+ <parameter name="baseAddress" value="0x0010c900" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96253,7 +96248,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d188" />
+ <parameter name="baseAddress" value="0x0010ca08" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96273,7 +96268,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d180" />
+ <parameter name="baseAddress" value="0x0010ca00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96293,7 +96288,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d178" />
+ <parameter name="baseAddress" value="0x0010c9f8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96313,7 +96308,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d170" />
+ <parameter name="baseAddress" value="0x0010c9f0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96333,7 +96328,7 @@
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d060" />
+ <parameter name="baseAddress" value="0x0010c8e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96353,7 +96348,7 @@
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cf40" />
+ <parameter name="baseAddress" value="0x0010c7c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96393,7 +96388,7 @@
start="cpu_0.data_master"
end="reg_si.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d168" />
+ <parameter name="baseAddress" value="0x0010c9e8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96453,7 +96448,7 @@
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cb00" />
+ <parameter name="baseAddress" value="0x0010c300" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96493,7 +96488,7 @@
start="cpu_0.data_master"
end="reg_dp_shiftram.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cd00" />
+ <parameter name="baseAddress" value="0x0010c500" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96513,7 +96508,7 @@
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d160" />
+ <parameter name="baseAddress" value="0x0010c9e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96533,7 +96528,7 @@
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d040" />
+ <parameter name="baseAddress" value="0x0010c8c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96553,7 +96548,7 @@
start="cpu_0.data_master"
end="reg_wg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010ca00" />
+ <parameter name="baseAddress" value="0x0010c200" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96573,7 +96568,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_input.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c000" />
+ <parameter name="baseAddress" value="0x0400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96613,7 +96608,7 @@
start="cpu_0.data_master"
end="reg_dp_selector.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d158" />
+ <parameter name="baseAddress" value="0x0010c9d8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96693,7 +96688,7 @@
start="cpu_0.data_master"
end="reg_bf_scale.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d110" />
+ <parameter name="baseAddress" value="0x0010c990" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96713,7 +96708,7 @@
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c800" />
+ <parameter name="baseAddress" value="0x0010c000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96733,7 +96728,7 @@
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d100" />
+ <parameter name="baseAddress" value="0x0010c980" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96773,7 +96768,7 @@
start="cpu_0.data_master"
end="reg_sdp_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cf00" />
+ <parameter name="baseAddress" value="0x0010c780" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96793,7 +96788,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d150" />
+ <parameter name="baseAddress" value="0x0010c9d0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96833,7 +96828,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_bsn.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cc80" />
+ <parameter name="baseAddress" value="0x0010c480" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96873,7 +96868,7 @@
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d148" />
+ <parameter name="baseAddress" value="0x0010c9c8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96893,7 +96888,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d140" />
+ <parameter name="baseAddress" value="0x0010c9c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96933,7 +96928,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d0f0" />
+ <parameter name="baseAddress" value="0x0010c970" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96953,7 +96948,7 @@
start="cpu_0.data_master"
end="reg_stat_hdr_dat_bst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c600" />
+ <parameter name="baseAddress" value="0x3600" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96973,7 +96968,7 @@
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cec0" />
+ <parameter name="baseAddress" value="0x0010c740" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97013,7 +97008,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d138" />
+ <parameter name="baseAddress" value="0x0010c9b8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97053,7 +97048,7 @@
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010ce80" />
+ <parameter name="baseAddress" value="0x0010c700" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97093,7 +97088,7 @@
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d130" />
+ <parameter name="baseAddress" value="0x0010c9b0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97113,7 +97108,7 @@
start="cpu_0.data_master"
end="reg_bsn_align_v2_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cc00" />
+ <parameter name="baseAddress" value="0x0010c400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97133,7 +97128,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d020" />
+ <parameter name="baseAddress" value="0x0010c8a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97153,7 +97148,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_xst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d000" />
+ <parameter name="baseAddress" value="0x0010c880" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97193,7 +97188,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c400" />
+ <parameter name="baseAddress" value="0x3400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97233,7 +97228,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010ce40" />
+ <parameter name="baseAddress" value="0x0010c6c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97253,7 +97248,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d0e0" />
+ <parameter name="baseAddress" value="0x0010c960" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97273,7 +97268,7 @@
start="cpu_0.data_master"
end="reg_ring_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d0d0" />
+ <parameter name="baseAddress" value="0x0010c950" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97293,7 +97288,7 @@
start="cpu_0.data_master"
end="reg_tr_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cfe0" />
+ <parameter name="baseAddress" value="0x0010c860" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97353,7 +97348,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_sst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cfc0" />
+ <parameter name="baseAddress" value="0x0010c840" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97373,7 +97368,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_bst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010ce00" />
+ <parameter name="baseAddress" value="0x0010c680" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97393,7 +97388,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_beamlet_output.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cdc0" />
+ <parameter name="baseAddress" value="0x0010c640" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97413,7 +97408,7 @@
start="cpu_0.data_master"
end="reg_bsn_align_v2_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cf80" />
+ <parameter name="baseAddress" value="0x0010c820" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97453,7 +97448,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x0010c600" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97473,7 +97468,7 @@
start="cpu_0.data_master"
end="reg_ring_lane_info_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3010" />
+ <parameter name="baseAddress" value="0x0010c940" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97493,7 +97488,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x0010c5c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97513,7 +97508,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_tx_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x0010c580" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97553,7 +97548,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3020" />
+ <parameter name="baseAddress" value="0x0010c800" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97593,7 +97588,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cd80" />
+ <parameter name="baseAddress" value="0x3040" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97653,7 +97648,7 @@
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010d0c0" />
+ <parameter name="baseAddress" value="0x3010" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97673,7 +97668,7 @@
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010cfa0" />
+ <parameter name="baseAddress" value="0x3020" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index b702216d0617f1ba897f4c9165cee418ce2afcc3..12f93299f3749dd70aeada6cd42e001a944071d7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -220,7 +220,7 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
@@ -234,7 +234,7 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 294fbe0f43ca72b0086a13d98e67469fb971ce98..ed38675826507b02c97ade53c867aa9b538aa56e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -468,8 +468,8 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_dual) + c_sdp_reg_bsn_monitor_v2_addr_w;
CONSTANT c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
CONSTANT c_sdp_reg_ring_lane_info_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
CONSTANT c_sdp_reg_dp_block_validate_err_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 4;
CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 2;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 3c2752619b4bd714de592fc2be94539d9c2c003e..66a11b4e304f6867f5a6ecc7b256b317515d3117 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -382,8 +382,6 @@ ARCHITECTURE str OF sdp_station IS
CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
CONSTANT c_addr_w_reg_bsn_align_v2_bf : NATURAL := ceil_log2(c_dual) + c_sdp_reg_bsn_align_v2_addr_w;
CONSTANT c_addr_w_reg_bsn_monitor_v2_rx_align_bf : NATURAL := ceil_log2(c_dual) + c_sdp_reg_bsn_monitor_v2_addr_w;
- CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_rx_bf : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
- CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_tx_bf : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
CONSTANT c_addr_w_reg_ring_lane_info_bf : NATURAL := 1;
-- Read only sdp_info values
@@ -1131,8 +1129,8 @@ BEGIN
g_lane_data_w => c_longword_w,
g_lane_packet_length => c_lane_packet_length_bf,
g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_sdp_N_pn_max,
- g_nof_tx_monitors => c_sdp_N_pn_max,
+ g_nof_rx_monitors => 1,
+ g_nof_tx_monitors => 1,
g_err_bi => c_err_bi,
g_nof_err_counts => c_nof_err_counts,
g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
@@ -1188,7 +1186,7 @@ BEGIN
u_mem_mux_reg_bsn_monitor_v2_ring_rx_bf : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx_bf
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
)
PORT MAP (
mosi => reg_bsn_monitor_v2_ring_rx_bf_copi,
@@ -1200,7 +1198,7 @@ BEGIN
u_mem_mux_reg_bsn_monitor_v2_ring_tx_bf : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx_bf
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
)
PORT MAP (
mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,