diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
index c24bea31456171432cf41cd6ef2d4cb5f254ea29..b0735df70e176860bbdac885b0bd4531e2c0bda7 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -65,12 +65,12 @@ ENTITY tr_10GbE IS
g_sim : BOOLEAN;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
g_nof_macs : NATURAL;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_use_mdio : BOOLEAN := FALSE;
g_mdio_epcs_dis : BOOLEAN := FALSE; -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
g_tx_fifo_fill : NATURAL := 10; -- Release tx packet only when sufficiently data is available,
g_tx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
g_rx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
- g_link_status_check : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
g_word_alignment_padding : BOOLEAN := FALSE
);
PORT (
@@ -231,7 +231,7 @@ BEGIN
g_sim => g_sim,
g_sim_level => g_sim_level, -- 0 = use IP; 1 = use fast serdes model
g_nof_channels => g_nof_macs,
- g_link_status_check => g_link_status_check,
+ g_direction => g_direction,
g_pre_header_padding => g_word_alignment_padding
)
PORT MAP (
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
index 4b4fa7bfa4413e5354d7f613ab4589e30f885726..04ad76a309d24ac814410eb5b6e8aa723572ba97 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
@@ -53,17 +53,19 @@ BEGIN
-- g_dp_clk_period : TIME := 5 ns; -- 200 MHz
-- g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
-- g_nof_channels : NATURAL := 1;
+-- g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
-- g_ref_clk_644_period : TIME := tech_pll_clk_644_period; -- for 10GBASE-R
-- g_ref_clk_156_period : TIME := 6.4 ns; -- for XAUI
-- g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
-- g_verify_link_recovery : BOOLEAN := TRUE;
--- g_link_status_check : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11"
- u_no_dut : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, TRUE, 5 ns, 0, 1, c_644, c_156, c_data_type, TRUE, "11") PORT MAP (tb_end_vec(0));
- u_tr_10GbE : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 1, c_644, c_156, c_data_type, TRUE, "11") PORT MAP (tb_end_vec(1));
- u_tr_10GbE_dp_clk_6_5ns : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 6.5 ns, 0, 1, c_644, c_156, c_data_type, TRUE, "11") PORT MAP (tb_end_vec(2));
- u_tr_10GbE_nof_channels_is_2 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 2, c_644, c_156, c_data_type, TRUE, "11") PORT MAP (tb_end_vec(3));
- u_tr_10GbE_sim_level_is_1 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 1, 1, c_644, c_156, c_data_type, TRUE, "11") PORT MAP (tb_end_vec(4));
+ u_no_dut : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, TRUE, 5 ns, 0, 1, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(0));
+ u_tr_10GbE : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 1, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(1));
+ u_tr_10GbE_tx_only : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 1, "TX_ONLY", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(2));
+ u_tr_10GbE_rx_only : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 1, "RX_ONLY", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(3));
+ u_tr_10GbE_dp_clk_6_5ns : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 6.5 ns, 0, 1, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(4));
+ u_tr_10GbE_nof_channels_is_2 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 2, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(5));
+ u_tr_10GbE_sim_level_is_1 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 1, 1, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(6));
p_tb_end : PROCESS
BEGIN
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
index 20720844e430f383d7bc73f92e9b4efbaeb8ac68..03af83e74fd1ab9488bcc18b9150c76ebab43a9f 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
@@ -31,6 +31,12 @@
-- Usage:
-- > as 10
-- > run -all
+--
+-- Remarks:
+-- . g_direction = "TX_RX" and "TX_ONLY" are verified properly by
+-- c_tx_rx_loopback = TRUE.
+-- g_direction = "RX_ONLY" is verified somehwat by c_tx_rx_loopback = FALSE,
+-- but to properly verify is would require using two DUTs.
LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
@@ -56,11 +62,11 @@ ENTITY tb_tr_10GbE IS
g_dp_clk_period : TIME := 5 ns; -- must be ~< 9000/(9000-c_tx_fifo_fill) * g_ref_clk_156_period
g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_ref_clk_644_period : TIME := tech_pll_clk_644_period; -- for 10GBASE-R
g_ref_clk_156_period : TIME := 6.4 ns; -- for XAUI
g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
- g_verify_link_recovery : BOOLEAN := TRUE;
- g_link_status_check : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "00"
+ g_verify_link_recovery : BOOLEAN := TRUE
);
PORT (
tb_end : OUT STD_LOGIC
@@ -74,7 +80,8 @@ ARCHITECTURE tb OF tb_tr_10GbE IS
CONSTANT cal_clk_period : TIME := 25 ns; -- 40 MHz
- CONSTANT phy_delay : TIME := sel_a_b(g_sim_level=0, 1 ns, 0 ns);
+ CONSTANT phy_delay : TIME := sel_a_b(g_sim_level=0, 0 ns, 0 ns);
+ CONSTANT c_tx_rx_loopback : BOOLEAN := g_direction/="TX_ONLY";
CONSTANT c_tx_fifo_fill : NATURAL := 100;
@@ -241,11 +248,11 @@ BEGIN
g_sim => c_sim,
g_sim_level => g_sim_level, -- 0 = use IP; 1 = use fast serdes model
g_nof_macs => g_nof_channels,
+ g_direction => g_direction,
g_use_mdio => TRUE,
g_mdio_epcs_dis => TRUE, -- TRUE disables Enhanced PCS on init; e.g. to target a 10GbE card in PC that does not support it
g_tx_fifo_fill => c_tx_fifo_fill,
g_tx_fifo_size => 256,
- g_link_status_check => g_link_status_check,
g_word_alignment_padding => TRUE
)
PORT MAP (
@@ -300,7 +307,7 @@ BEGIN
gen_link_connect : FOR I IN 0 TO g_nof_channels-1 GENERATE
u_link_connect : ENTITY tech_mac_10g_lib.tb_tech_mac_10g_link_connect
GENERIC MAP (
- g_loopback => TRUE,
+ g_loopback => c_tx_rx_loopback,
g_link_delay => phy_delay
)
PORT MAP (