diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index 249cc7e367dad6cc05f57115a68cab5e88e3ac62..3c334bd9e2fa1ac0cb2ee6aadfb08ebabaa575cb 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -65,7 +65,11 @@ ENTITY ddr3 IS
dvr_done : OUT STD_LOGIC;
wr_clk : IN STD_LOGIC;
- wr_rst : IN STD_LOGIC;
+ wr_rst : IN STD_LOGIC;
+
+ -- MM register map for DDR controller status info
+ reg_io_ddr_mosi : IN t_mem_mosi;
+ reg_io_ddr_miso : OUT t_mem_miso;
flush_ena : IN STD_LOGIC; -- When toggled '1' the write-fifo flusher is enabled and stops flushing when configured trigger condition is met.
@@ -95,39 +99,45 @@ END ddr3;
ARCHITECTURE str OF ddr3 IS
- CONSTANT c_wr_fifo_depth : NATURAL := g_wr_fifo_depth * (c_ddr3_ctlr_data_w/g_wr_data_w); -- Multiply fifo depth by the fifo's rd/wr width ratio to get write side depth
-
- CONSTANT c_latency : NATURAL := 1;
-
- SIGNAL ctlr_burst : STD_LOGIC;
- SIGNAL ctlr_burst_size : STD_LOGIC_VECTOR(c_ddr3_ctlr_maxburstsize_w-1 DOWNTO 0);
- SIGNAL ctlr_address : STD_LOGIC_VECTOR(ceil_log2(g_ddr.cs_w-1) + g_ddr.ba_w + g_ddr.a_w + g_ddr.a_col_w - c_ddr3_ctlr_rsl_w-1 DOWNTO 0); -- ceil_log2(..-1) because the chip select lines are converted to a logical address
- SIGNAL ctlr_rd_req : STD_LOGIC;
- SIGNAL ctlr_wr_req : STD_LOGIC;
-
- SIGNAL ctlr_rst_n : STD_LOGIC;
- SIGNAL ctlr_gen_rst_n : STD_LOGIC;
-
- SIGNAL i_ctlr_gen_clk : STD_LOGIC;
- SIGNAL i_ctlr_gen_rst : STD_LOGIC;
- SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC;
- SIGNAL i_ctlr_init_done : STD_LOGIC;
- SIGNAL i_ctlr_rdy : STD_LOGIC;
- SIGNAL i_dvr_done : STD_LOGIC;
-
- SIGNAL dvr_cur_addr : t_ddr3_addr;
- SIGNAL dvr_flush : STD_LOGIC := '0';
-
- SIGNAL ctlr_wr_siso : t_dp_siso := c_dp_siso_rdy; -- default xon='1'
- SIGNAL ctlr_wr_sosi : t_dp_sosi;
-
- SIGNAL flush_wr_siso : t_dp_siso;
- SIGNAL flush_wr_sosi : t_dp_sosi;
-
- SIGNAL ctlr_rd_siso : t_dp_siso;
- SIGNAL ctlr_rd_sosi : t_dp_sosi;
+ CONSTANT c_wr_fifo_depth : NATURAL := g_wr_fifo_depth * (c_ddr3_ctlr_data_w/g_wr_data_w); -- Multiply fifo depth by the fifo's rd/wr width ratio to get write side depth
+
+ CONSTANT c_latency : NATURAL := 1;
+
+ SIGNAL ctlr_burst : STD_LOGIC;
+ SIGNAL ctlr_burst_size : STD_LOGIC_VECTOR(c_ddr3_ctlr_maxburstsize_w-1 DOWNTO 0);
+ SIGNAL ctlr_address : STD_LOGIC_VECTOR(ceil_log2(g_ddr.cs_w-1) + g_ddr.ba_w + g_ddr.a_w + g_ddr.a_col_w - c_ddr3_ctlr_rsl_w-1 DOWNTO 0); -- ceil_log2(..-1) because the chip select lines are converted to a logical address
+ SIGNAL ctlr_rd_req : STD_LOGIC;
+ SIGNAL ctlr_wr_req : STD_LOGIC;
+
+ SIGNAL ctlr_rst_n : STD_LOGIC;
+ SIGNAL ctlr_gen_rst_n : STD_LOGIC;
+
+ SIGNAL i_ctlr_gen_clk : STD_LOGIC;
+ SIGNAL i_ctlr_gen_rst : STD_LOGIC;
+ SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC;
+ SIGNAL i_ctlr_init_done : STD_LOGIC;
+ SIGNAL i_ctlr_rdy : STD_LOGIC;
+ SIGNAL i_dvr_done : STD_LOGIC;
+
+ SIGNAL dvr_cur_addr : t_ddr3_addr;
+ SIGNAL dvr_flush : STD_LOGIC := '0';
+
+ SIGNAL ctlr_wr_siso : t_dp_siso := c_dp_siso_rdy; -- default xon='1'
+ SIGNAL ctlr_wr_sosi : t_dp_sosi;
+
+ SIGNAL flush_wr_siso : t_dp_siso;
+ SIGNAL flush_wr_sosi : t_dp_sosi;
+
+ SIGNAL ctlr_rd_siso : t_dp_siso;
+ SIGNAL ctlr_rd_sosi : t_dp_sosi;
+
+ SIGNAL wr_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth)-1 DOWNTO 0); -- read side depth of the write FIFO
+
+ SIGNAL local_cal_success : STD_LOGIC;
+ SIGNAL local_cal_fail : STD_LOGIC;
- SIGNAL wr_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth)-1 DOWNTO 0); -- read side depth of the write FIFO
+ CONSTANT c_mem_reg_io_ddr : t_c_mem := (c_mem_reg_rd_latency, 1 , 32 , 1, 'X');
+ SIGNAL mm_reg_io_ddr : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
@@ -269,6 +279,35 @@ BEGIN
wr_fifo_usedw => wr_fifo_usedw
);
+ u_reg_map : ENTITY common_lib.common_reg_r_w_dc
+ GENERIC MAP (
+ g_cross_clock_domain => TRUE, -- : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_in_new_latency => 0, -- : NATURAL := 0; -- >= 0
+ g_readback => FALSE, -- : BOOLEAN := FALSE; -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_reg => c_mem_reg_io_ddr, -- : t_c_mem := c_mem_reg;
+ g_init_reg => (OTHERS => '0') -- : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst, --: IN STD_LOGIC; -- reset synchronous with mm_clk
+ mm_clk => mm_clk, --: IN STD_LOGIC; -- memory-mapped bus clock
+ st_rst => i_ctlr_gen_rst, --: IN STD_LOGIC; -- reset synchronous with st_clk
+ st_clk => i_ctlr_gen_clk, --: IN STD_LOGIC; -- other clock domain clock
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_io_ddr_mosi, --: IN t_mem_mosi; -- actual ranges defined by g_reg
+ sla_out => reg_io_ddr_miso, --: OUT t_mem_miso; -- actual ranges defined by g_reg
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN, -- : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
+ reg_rd_arr => OPEN, -- : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
+ in_new => '1', -- : IN STD_LOGIC := '1';
+ in_reg => mm_reg_io_ddr, -- : IN STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0);
+ out_reg => OPEN -- : OUT STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0)
+ );
+
+ mm_reg_io_ddr <= RESIZE_UVEC(local_cal_fail & local_cal_success & i_ctlr_gen_rst & flush_ena & i_ctlr_rdy & i_ctlr_init_done, 32);
+
ctlr_address <= dvr_cur_addr.chip & dvr_cur_addr.bank & dvr_cur_addr.row(g_ddr.a_w-1 DOWNTO 0) & dvr_cur_addr.column(g_ddr.a_col_w -1 DOWNTO c_ddr3_ctlr_rsl_w);
gen_uphy_4g_800_master : IF g_mts = 800 AND g_phy = 1 GENERATE
@@ -306,8 +345,8 @@ BEGIN
avl_write_req => ctlr_wr_req,
avl_size => ctlr_burst_size,
local_init_done => i_ctlr_init_done,
- local_cal_success => OPEN,
- local_cal_fail => OPEN,
+ local_cal_success => local_cal_success,
+ local_cal_fail => local_cal_fail,
oct_rdn => phy_in.oct_rdn,
oct_rup => phy_in.oct_rup,
seriesterminationcontrol => ser_term_ctrl_out,
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
index c6bd89c7aa4de48f6491329d2b6d0ecb2c5fb67f..268570eab351480a68af8775fcbefcc3f9a86d98 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
@@ -55,6 +55,10 @@ ENTITY ddr3_transpose IS
dp_out_clk : OUT STD_LOGIC;
dp_out_rst : OUT STD_LOGIC;
+
+ -- MM register map for DDR controller status info
+ reg_io_ddr_mosi : IN t_mem_mosi;
+ reg_io_ddr_miso : OUT t_mem_miso;
-- ST sinks
snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
@@ -63,8 +67,8 @@ ENTITY ddr3_transpose IS
src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- -- Memory Mapped
- ram_ss_ss_transp_mosi : IN t_mem_mosi; -- channel select control
+ -- Memory Mappedreg_io_ddr_mosi : IN t_mem_mosi;
+ ram_ss_ss_transp reg_io_ddr_miso _mosi : IN t_mem_mosi; -- channel select control
ram_ss_ss_transp_miso : OUT t_mem_miso;
ser_term_ctrl_out : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
@@ -194,7 +198,7 @@ BEGIN
g_siso : FOR J IN 0 TO g_nof_streams-1 GENERATE
snk_out_arr(J) <= ss_in_siso;
END GENERATE;
-
+
u_ddr3: ENTITY work.ddr3
GENERIC MAP(
g_ddr => c_ddr3_phy_4g,
@@ -223,7 +227,10 @@ BEGIN
ctlr_gen_clk => dp_out_clk,
ctlr_gen_rst => dp_out_rst,
-
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
ctlr_init_done => ctlr_init_done,
ctlr_rdy => ctlr_rdy,
@@ -239,7 +246,7 @@ BEGIN
wr_sosi => transpose_in_sosi,
wr_siso => transpose_in_siso,
-
+
flush_ena => flush_ena,
rd_sosi => transpose_out_sosi,