diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 0ec78eaec6201c1867a46565d0e61ebb04a02dab..38214e72d7c3202a66b85fe2fed3e064fda6f004 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -128,6 +128,7 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL inp_bsn_adr : NATURAL;
SIGNAL outp_ds : NATURAL;
SIGNAL outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL data_stopped : STD_LOGIC;
BEGIN
@@ -153,7 +154,8 @@ BEGIN
out_sosi => out_sosi,
out_adr => out_adr,
out_bsn_ds => inp_ds,
- out_bsn_adr => inp_bsn_adr
+ out_bsn_adr => inp_bsn_adr,
+ out_data_stopped => data_stopped
);
-- functions as a fifo buffer for input data into the sdram stick. also manages input to sdram stick.
@@ -279,6 +281,7 @@ BEGIN
inp_adr => out_adr,
inp_ds => inp_ds,
inp_bsn_adr => inp_bsn_adr,
+ inp_data_stopped => data_stopped,
rst_ddrctrl_input => rst_ddrctrl_input,
-- io_ddr
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 66348762b0e082bbdf10f42746ce2256317222f1..3f4cab12b7d991c5abd15ddc3fe2030bb5ff222e 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -62,6 +62,7 @@ ENTITY ddrctrl_controller IS
inp_adr : IN NATURAL;
inp_ds : IN NATURAL;
inp_bsn_adr : IN NATURAL;
+ inp_data_stopped : IN STD_LOGIC;
rst_ddrctrl_input : OUT STD_LOGIC;
-- io_ddr
@@ -107,13 +108,12 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
started : STD_LOGIC;
-- stopping signals
- ready_for_stop : STD_LOGIC;
+ ready_for_set_stop : STD_LOGIC;
stop_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
last_adr_to_write_to : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
stop_burstsize : NATURAL;
stopped : STD_LOGIC;
rst_ddrctrl_input : STD_LOGIC;
- cooling_down : NATURAL;
-- writing signals
need_burst : STD_LOGIC;
@@ -129,7 +129,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
wr_sosi : t_dp_sosi;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', c_proportion, '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
+ CONSTANT c_t_reg_init : t_reg := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
-- signals for readability
@@ -141,7 +141,7 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_ds, inp_bsn_adr, dvr_miso, rd_fifo_usedw, stop_in)
+ p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_ds, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, stop_in)
VARIABLE v : t_reg := c_t_reg_init;
@@ -191,13 +191,11 @@ BEGIN
ELSE
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0);
END IF;
- v.ready_for_stop := '0';
- v.cooling_down := c_proportion;
+ v.ready_for_set_stop := '0';
v.last_adr_to_write_to(c_adr_w-1 DOWNTO c_bitshift_w) := v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_w);
v.last_adr_to_write_to(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0))-TO_UINT(v.last_adr_to_write_to);
-
-- still a write cyle
-- if adr mod g_burstsize = 0
-- this makes sure that only ones every 64 writes a writeburst is started.
@@ -224,21 +222,18 @@ BEGIN
WHEN STOP_WRITING =>
- v.stopped := '1';
+ v.dvr_mosi.burstbegin := '0';
+ v.stopped := '1';
-- wait until the write burst is finished
- IF NOT (q_reg.cooling_down = 0) THEN
- v.cooling_down := q_reg.cooling_down-1;
+ IF inp_data_stopped = '0' THEN
v.state := STOP_WRITING;
- ELSIF dvr_miso.done = '1' AND q_reg.need_burst = '0' THEN
+ ELSIF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' AND q_reg.need_burst = '0' THEN
v.wr_sosi.valid := '0';
v.state := LAST_WRITE_BURST;
ELSE
- v.state := STOP_WRITING;
+ v.state := STOP_WRITING;
END IF;
- IF inp_sosi.valid = '1' THEN
- v.cooling_down := c_proportion;
- END IF;
-- still receiving write data.
-- if adr mod g_burstsize = 0
@@ -356,8 +351,8 @@ BEGIN
IF q_reg.state = RESET OR q_reg.state = WRITING OR q_reg.state = SET_STOP OR q_reg.state = IDLE THEN
IF stop_in = '1' THEN
- v.ready_for_stop := '1';
- ELSIF q_reg.ready_for_stop = '1' AND inp_sosi.eop = '1' THEN
+ v.ready_for_set_stop := '1';
+ ELSIF q_reg.ready_for_set_stop = '1' AND inp_sosi.eop = '1' THEN
v.state := SET_STOP;
ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index d4cb0309ce79cdf4a08bcaaeb4ec5c7e1818d9ea..208780472a0e4df9cfc607de8f8f3e87e0ffb783 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -60,7 +60,8 @@ ENTITY ddrctrl_input IS
out_sosi : OUT t_dp_sosi; -- output data
out_adr : OUT NATURAL;
out_bsn_ds : OUT NATURAL;
- out_bsn_adr : OUT NATURAL
+ out_bsn_adr : OUT NATURAL;
+ out_data_stopped : OUT STD_LOGIC
);
END ddrctrl_input;
@@ -72,11 +73,12 @@ ARCHITECTURE str OF ddrctrl_input IS
-- signals for connecting the components
- SIGNAL sosi_p_rp : t_dp_sosi := c_dp_sosi_init;
- SIGNAL sosi_rp_ac : t_dp_sosi := c_dp_sosi_init;
- SIGNAL adr : NATURAL := 0;
- SIGNAL bsn_ds : NATURAL := 0;
- SIGNAL valid : STD_LOGIC := '0';
+ SIGNAL sosi_p_rp : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL sosi_rp_ac : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL adr : NATURAL := 0;
+ SIGNAL bsn_ds : NATURAL := 0;
+ SIGNAL valid : STD_LOGIC := '0';
+ SIGNAL data_stopped_rp_ac : STD_LOGIC := '0';
BEGIN
@@ -108,7 +110,8 @@ BEGIN
in_sosi => sosi_p_rp, -- input data
in_stop => in_stop,
out_sosi => sosi_rp_ac, -- output data
- out_bsn_ds => bsn_ds -- amount of bits between adr [0] and sosi_arr[0][0] where bsn is assigned to
+ out_bsn_ds => bsn_ds, -- amount of bits between adr [0] and sosi_arr[0][0] where bsn is assigned to
+ out_data_stopped => data_stopped_rp_ac
);
-- creates address by counting input valids
@@ -122,10 +125,12 @@ BEGIN
rst => rst,
in_sosi => sosi_rp_ac, -- input data
in_bsn_ds => bsn_ds,
+ in_data_stopped => data_stopped_rp_ac,
out_sosi => out_sosi, -- output data
out_adr => adr,
out_bsn_adr => out_bsn_adr,
- out_bsn_ds => out_bsn_ds
+ out_bsn_ds => out_bsn_ds,
+ out_data_stopped => out_data_stopped
);
END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index 43cb85d273a95ca7e971c36aafc7347959e93a51..916bbb2a18196a555303ca81f99dc0f79b188292 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -1,160 +1,167 @@
--------------------------------------------------------------------------------
---
--- Copyright 2022
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
--- Author: Job van Wee
--- Purpose: Creates address by counting input valids
---
--- Description:
--- The counter starts on the first valid = '1' clockcylce, the counter stops
--- when valid = '0'.
---
--- Remark:
--- Use VHDL coding template from:
--- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
--- The maximum value of the address is determend by g_tech_ddr.
-
-LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE tech_ddr_lib.tech_ddr_pkg.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-
-ENTITY ddrctrl_input_address_counter IS
- GENERIC (
- g_tech_ddr : t_c_tech_ddr; -- type of memory
- g_max_adr : NATURAL
- );
- PORT (
- clk : IN STD_LOGIC;
- rst : IN STD_LOGIC;
- in_sosi : IN t_dp_sosi; -- input data
- in_bsn_ds : IN NATURAL;
- out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
- out_adr : OUT NATURAL;
- out_bsn_adr : OUT NATURAL;
- out_bsn_ds : OUT NATURAL
- );
-END ddrctrl_input_address_counter;
-
-
-ARCHITECTURE rtl OF ddrctrl_input_address_counter IS
-
- -- constants for readability
- CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the with of the input data and output data, 576
-
- -- type for statemachine
- TYPE t_state IS (RESET, COUNTING, MAX, IDLE);
-
- -- record for readability
- TYPE t_reg IS RECORD
- state : t_state;
- bsn_passed : STD_LOGIC;
- out_sosi : t_dp_sosi;
- out_bsn_adr : NATURAL;
- out_bsn_ds : NATURAL;
- s_in_sosi : t_dp_sosi;
- s_in_bsn_ds : NATURAL;
- s_adr : NATURAL;
- END RECORD;
-
- CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, 0, c_dp_sosi_init, 0, 0);
-
-
- -- signals for readability
- SIGNAL d_reg : t_reg := c_t_reg_init;
- SIGNAL q_reg : t_reg := c_t_reg_init;
-
-BEGIN
-
- q_reg <= d_reg WHEN rising_edge(clk);
-
- -- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0.
- p_adr : PROCESS(rst, in_sosi, q_reg)
-
- VARIABLE v : t_reg;
-
- BEGIN
- v := q_reg;
-
- -- compensate for delay in ddrctrl_input_address_counter
- v.out_sosi := q_reg.s_in_sosi;
- v.out_bsn_ds := q_reg.s_in_bsn_ds;
- v.s_in_sosi := in_sosi;
- v.s_in_bsn_ds := in_bsn_ds;
-
-
- CASE q_reg.state IS
- WHEN RESET =>
- v.s_adr := 0;
-
- IF q_reg.s_in_sosi.sop = '1' THEN
- v.out_bsn_adr := v.s_adr;
- END IF;
-
-
- WHEN COUNTING =>
- v.s_adr := q_reg.s_adr+1;
-
- IF q_reg.s_in_sosi.sop = '1' THEN
- v.out_bsn_adr := v.s_adr;
- END IF;
-
-
- WHEN MAX =>
- v.s_adr := 0;
-
- IF q_reg.s_in_sosi.sop = '1' THEN
- v.out_bsn_adr := v.s_adr;
- END IF;
-
-
- WHEN IDLE =>
- -- after a reset skip the first data block so the ddr memory can calm down.
- IF NOT(q_reg.s_in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
- v.bsn_passed := '1';
- END IF;
-
-
- END CASE;
-
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF q_reg.s_adr = g_max_adr-1 AND in_sosi.valid = '1' AND q_reg.bsn_passed = '1' THEN
- v.state := MAX;
- ELSIF in_sosi.valid = '1' AND q_reg.bsn_passed = '1' THEN
- v.state := COUNTING;
- ELSE
- v.state := IDLE;
- END IF;
-
- d_reg <= v;
- END PROCESS;
-
- -- fill outputs
- out_sosi <= q_reg.out_sosi;
- out_adr <= q_reg.s_adr;
- out_bsn_adr <= q_reg.out_bsn_adr;
- out_bsn_ds <= q_reg.out_bsn_ds;
- out_sosi.bsn <= q_reg.out_sosi.bsn;
-
-END rtl;
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Creates address by counting input valids
+--
+-- Description:
+-- The counter starts on the first valid = '1' clockcylce, the counter stops
+-- when valid = '0'.
+--
+-- Remark:
+-- Use VHDL coding template from:
+-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+-- The maximum value of the address is determend by g_tech_ddr.
+
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+
+ENTITY ddrctrl_input_address_counter IS
+ GENERIC (
+ g_tech_ddr : t_c_tech_ddr; -- type of memory
+ g_max_adr : NATURAL
+ );
+ PORT (
+ clk : IN STD_LOGIC;
+ rst : IN STD_LOGIC;
+ in_sosi : IN t_dp_sosi; -- input data
+ in_bsn_ds : IN NATURAL;
+ in_data_stopped : IN STD_LOGIC;
+ out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
+ out_adr : OUT NATURAL;
+ out_bsn_adr : OUT NATURAL;
+ out_bsn_ds : OUT NATURAL;
+ out_data_stopped : OUT STD_LOGIC
+ );
+END ddrctrl_input_address_counter;
+
+
+ARCHITECTURE rtl OF ddrctrl_input_address_counter IS
+
+ -- constants for readability
+ CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the with of the input data and output data, 576
+
+ -- type for statemachine
+ TYPE t_state IS (RESET, COUNTING, MAX, IDLE);
+
+ -- record for readability
+ TYPE t_reg IS RECORD
+ state : t_state;
+ bsn_passed : STD_LOGIC;
+ out_sosi : t_dp_sosi;
+ out_bsn_adr : NATURAL;
+ out_bsn_ds : NATURAL;
+ out_data_stopped : STD_LOGIC;
+ s_in_sosi : t_dp_sosi;
+ s_in_bsn_ds : NATURAL;
+ s_in_data_stopped : STD_LOGIC;
+ s_adr : NATURAL;
+ END RECORD;
+
+ CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, 0, '0', c_dp_sosi_init, 0, '0', 0);
+
+
+ -- signals for readability
+ SIGNAL d_reg : t_reg := c_t_reg_init;
+ SIGNAL q_reg : t_reg := c_t_reg_init;
+
+BEGIN
+
+ q_reg <= d_reg WHEN rising_edge(clk);
+
+ -- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0.
+ p_adr : PROCESS(rst, in_sosi, in_bsn_ds, in_data_stopped, q_reg)
+
+ VARIABLE v : t_reg;
+
+ BEGIN
+ v := q_reg;
+
+ -- compensate for delay in ddrctrl_input_address_counter
+ v.out_sosi := q_reg.s_in_sosi;
+ v.out_bsn_ds := q_reg.s_in_bsn_ds;
+ v.out_data_stopped := q_reg.s_in_data_stopped;
+ v.s_in_sosi := in_sosi;
+ v.s_in_bsn_ds := in_bsn_ds;
+ v.s_in_data_stopped := in_data_stopped;
+
+
+ CASE q_reg.state IS
+ WHEN RESET =>
+ v.s_adr := 0;
+
+ IF q_reg.s_in_sosi.sop = '1' THEN
+ v.out_bsn_adr := v.s_adr;
+ END IF;
+
+
+ WHEN COUNTING =>
+ v.s_adr := q_reg.s_adr+1;
+
+ IF q_reg.s_in_sosi.sop = '1' THEN
+ v.out_bsn_adr := v.s_adr;
+ END IF;
+
+
+ WHEN MAX =>
+ v.s_adr := 0;
+
+ IF q_reg.s_in_sosi.sop = '1' THEN
+ v.out_bsn_adr := v.s_adr;
+ END IF;
+
+
+ WHEN IDLE =>
+ -- after a reset skip the first data block so the ddr memory can initialize.
+ IF NOT(q_reg.s_in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
+ v.bsn_passed := '1';
+ END IF;
+
+
+ END CASE;
+
+ IF rst = '1' THEN
+ v.state := RESET;
+ ELSIF q_reg.s_adr = g_max_adr-1 AND in_sosi.valid = '1' AND q_reg.bsn_passed = '1' THEN
+ v.state := MAX;
+ ELSIF in_sosi.valid = '1' AND q_reg.bsn_passed = '1' THEN
+ v.state := COUNTING;
+ ELSE
+ v.state := IDLE;
+ END IF;
+
+ d_reg <= v;
+ END PROCESS;
+
+ -- fill outputs
+ out_sosi <= q_reg.out_sosi;
+ out_adr <= q_reg.s_adr;
+ out_bsn_adr <= q_reg.out_bsn_adr;
+ out_bsn_ds <= q_reg.out_bsn_ds;
+ out_sosi.bsn <= q_reg.out_sosi.bsn;
+ out_data_stopped <= q_reg.out_data_stopped;
+
+END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 6bcf139147a7f82a2914cc2b6741897a55f8355b..7b7a3ed0d98c5229929b4d25982b3aa41910a258 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -49,7 +49,8 @@ ENTITY ddrctrl_input_repack IS
in_stop : IN STD_LOGIC := '0';
out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
out_bsn_ds : OUT NATURAL := 0;
- out_bsn_wr : OUT STD_LOGIC := '0'
+ out_bsn_wr : OUT STD_LOGIC := '0';
+ out_data_stopped : OUT STD_LOGIC := '0'
);
END ddrctrl_input_repack;
@@ -77,9 +78,10 @@ ARCHITECTURE rtl OF ddrctrl_input_repack IS
out_data_count : STD_LOGIC; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
out_bsn_ds : NATURAL; -- this is the amount of bits that the data corresponding to out_bsn is shifted from the first bit in that data word
+ out_data_stopped : STD_LOGIC; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, 0, (OTHERS => '0'), '0', 0, 0, 0, '0', c_dp_sosi_init, 0);
+ CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, 0, (OTHERS => '0'), '0', 0, 0, 0, '0', c_dp_sosi_init, 0, '0');
-- signals for readability
@@ -107,6 +109,7 @@ BEGIN
v.s_input_cnt := q_reg.s_input_cnt+1;
v.out_sosi.sop := '0';
v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
@@ -139,6 +142,7 @@ BEGIN
v.out_bsn_ds := q_reg.q_out_bsn_ds;
v.out_sosi.sop := q_reg.q_sop;
v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
IF rst = '1' THEN
@@ -169,6 +173,7 @@ BEGIN
v.q_sop := '0';
v.out_sosi.sop := '0';
v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
IF rst = '1' THEN
@@ -242,7 +247,8 @@ BEGIN
WHEN STOP =>
v.out_sosi.valid := '0';
- v.q_sop := '0';
+ v.q_sop := '0';
+ v.out_data_stopped := '1';
IF rst = '1' THEN
v.state := RESET;
ELSIF in_stop = '1' OR in_sosi.valid = '0' THEN
@@ -263,7 +269,8 @@ BEGIN
END PROCESS;
-- fill outputs
- out_sosi <= q_reg.out_sosi;
- out_bsn_ds <= q_reg.out_bsn_ds;
+ out_sosi <= q_reg.out_sosi;
+ out_bsn_ds <= q_reg.out_bsn_ds;
+ out_data_stopped <= q_reg.out_data_stopped;
END rtl;