diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
index 609301a27fd9fd69cf01ac712067f1ff3491752a..82c0df011c95f6503ba618f2fbe419b37c5765ab 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
@@ -97,7 +97,7 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
-# false paths added for the jesd test design
+# false paths added for the jesd interface as these clocks are independent.
set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index cceb27d004e0df25b245ede31c7a6218b7189406..84a1502e5dff2560c39693d948b943367d2febba 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -39,7 +39,8 @@ peripherals:
- mm_port_name: REG_CROSSLETS_INFO
mm_port_type: REG
mm_port_description: |
- "The SDP crosslets info contains the step size and 15 offsets."
+ "The SDP crosslets info contains the step size and 15 offsets, that are used to select a new
+ crosslet subband for every integration interval"
fields:
- - { field_name: step, access_mode: RW, address_offset: 0x3C }
- - field_name: offset
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index faf5283462e31428be408343928b01e54a7cbc5f..ae271ee613332fceee60cd871908b4d6690bd0a9 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -212,7 +212,7 @@ BEGIN
GENERIC MAP (
g_nof_streams => c_sdp_S_pn,
g_nof_words => c_sdp_V_sample_delay,
- g_data_w => c_sdp_W_adc_jesd,
+ g_data_w => c_sdp_W_adc,
g_use_sync_in => TRUE
)
PORT MAP (
@@ -392,7 +392,7 @@ BEGIN
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_nof_streams => c_sdp_S_pn,
- g_symbol_w => c_sdp_W_adc_jesd,
+ g_symbol_w => c_sdp_W_adc,
g_nof_symbols_per_data => 1, -- Wideband factor is 1
g_nof_accumulations => g_bsn_nof_clk_per_sync
)
@@ -422,7 +422,7 @@ BEGIN
GENERIC MAP (
g_technology => g_technology,
g_nof_streams => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc_jesd,
+ g_data_w => c_sdp_W_adc,
g_buf_nof_data => g_buf_nof_data,
g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
)
@@ -449,7 +449,7 @@ BEGIN
u_dp_fifo_dc_arr : ENTITY dp_lib.dp_fifo_dc_arr
GENERIC MAP (
g_nof_streams => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc_jesd,
+ g_data_w => c_sdp_W_adc,
g_bsn_w => c_bs_bsn_w,
g_use_empty => FALSE,
g_use_ctrl => TRUE,
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 95d7115b26a5767cd4cb9629814438d1a249d900..5bf3166f9730c7bc147e51888724bd6e83228739 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -338,7 +338,6 @@ peripherals:
fields:
- - field_name: nof_blk_per_sync
field_description: |
- "The block counter resets if a sync arrives at the input or when nof_blk_per_sync is reached.
- nof_blk_per_sync is controllable using M&C."
+ "The block counter resets if a sync arrives at the input or when nof_blk_per_sync is reached."
address_offset: 0x0
access_mode: RW
diff --git a/libraries/dsp/st/src/vhdl/st_xst.vhd b/libraries/dsp/st/src/vhdl/st_xst.vhd
index d87e0be2d583400082c3dc5a9a8500725484e1d0..1a0e75770b67e3cbe3710b95062940c087bf3a82 100644
--- a/libraries/dsp/st/src/vhdl/st_xst.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xst.vhd
@@ -69,8 +69,8 @@ ARCHITECTURE str OF st_xst IS
busy : STD_LOGIC;
in_a_index : NATURAL;
in_b_index : NATURAL;
- reg_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
- reg_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
in_a_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
END RECORD;
@@ -121,14 +121,14 @@ BEGIN
VARIABLE v : t_reg;
VARIABLE v_in_a_index : NATURAL;
VARIABLE v_in_b_index : NATURAL;
- VARIABLE v_reg_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
- VARIABLE v_reg_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ VARIABLE v_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ VARIABLE v_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
BEGIN
v := r;
v_in_a_index := r.in_a_index;
v_in_b_index := r.in_b_index;
- v_reg_x_sosi_0_re := r.reg_x_sosi_0_re;
- v_reg_x_sosi_0_im := r.reg_x_sosi_0_im;
+ v_x_sosi_0_re := r.x_sosi_0_re;
+ v_x_sosi_0_im := r.x_sosi_0_im;
-- initiate next block
IF r.busy = '0' AND x_sosi_arr(0).sop = '1' THEN
v.busy := '1';
@@ -154,20 +154,20 @@ BEGIN
END IF;
-- Capture x_sosi_arr(0) data
- v_reg_x_sosi_0_re(v_in_b_index) := x_sosi_arr(0).re;
- v_reg_x_sosi_0_im(v_in_b_index) := x_sosi_arr(0).im;
+ v_x_sosi_0_re(v_in_b_index) := x_sosi_arr(0).re;
+ v_x_sosi_0_im(v_in_b_index) := x_sosi_arr(0).im;
-- reorder x_sosi_arr(0) data to follow in_a_index instead of in_b_index. All sosi in in_a_sosi_arr are identical.
FOR I IN 0 TO g_nof_streams-1 LOOP
v.in_a_sosi_arr(I) := x_sosi_arr(0);
- v.in_a_sosi_arr(I).re := v_reg_x_sosi_0_re(v_in_a_index);
- v.in_a_sosi_arr(I).im := v_reg_x_sosi_0_im(v_in_a_index);
+ v.in_a_sosi_arr(I).re := v_x_sosi_0_re(v_in_a_index);
+ v.in_a_sosi_arr(I).im := v_x_sosi_0_im(v_in_a_index);
END LOOP;
v.in_a_index := v_in_a_index;
v.in_b_index := v_in_b_index;
- v.reg_x_sosi_0_re := v_reg_x_sosi_0_re;
- v.reg_x_sosi_0_im := v_reg_x_sosi_0_im;
+ v.x_sosi_0_re := v_x_sosi_0_re;
+ v.x_sosi_0_im := v_x_sosi_0_im;
nxt_r <= v;
END PROCESS;