diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/qsys_lofar2_unb2c_ddrctrl.qsys b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/qsys_lofar2_unb2c_ddrctrl.qsys
index bc518d1c9485136c38127f329be09e547e7bc423..edf07f8a975373d55e4f8dc2316d425ac15f2f80 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/qsys_lofar2_unb2c_ddrctrl.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/qsys_lofar2_unb2c_ddrctrl.qsys
@@ -4565,47 +4565,6 @@
</componentDefinition>]]></parameter>
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>clk_out</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- <value>clk_in</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>125000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>clk_in</name>
<type>clock</type>
@@ -4678,6 +4637,47 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>clk_out</name>
+ <role>clk</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ <value>clk_in</value>
+ </entry>
+ <entry>
+ <key>clockRate</key>
+ <value>125000000</value>
+ </entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>clk_reset</name>
<type>reset</type>
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 47c2d2c826d8e00239a2d7c17a9e3d17c3236620..4b791b7b87e332847c64fab8c9d1bebb97049c73 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -141,6 +141,7 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL state_vec : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL ddrctrl_ctrl_state_local : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
+ SIGNAL ctlr_wr_flush_en : STD_LOGIC;
BEGIN
@@ -210,7 +211,8 @@ BEGIN
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
state_vec => state_vec,
-
+ ctlr_wr_flush_en_o => ctlr_wr_flush_en,
+
-- Driver clock domain
dvr_clk => clk,
dvr_rst => rst,
@@ -309,6 +311,7 @@ BEGIN
wr_sosi => wr_sosi,
wr_fifo_usedw => wr_fifo_usedw,
rd_fifo_usedw => rd_fifo_usedw,
+ ctlr_wr_flush_en => ctlr_wr_flush_en,
-- ddrctrl_output
outp_bsn => bsn_co,
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 2ef30499d20dda8f4a1016aaad784968df3f1d4f..8e534df27a61bc407cc1fa313ed389f7df5d477f 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -72,6 +72,7 @@ ENTITY ddrctrl_controller IS
wr_sosi : OUT t_dp_sosi;
wr_fifo_usedw : IN STD_LOGIC_VECTOR(g_wr_fifo_uw_w-1 DOWNTO 0);
rd_fifo_usedw : IN STD_LOGIC_VECTOR(g_rd_fifo_uw_w-1 DOWNTO 0);
+ ctlr_wr_flush_en : IN STD_LOGIC;
-- ddrctrl_output
outp_bsn : OUT STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
@@ -90,12 +91,12 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_pof_ma : NATURAL := ((NATURAL((REAL(g_max_adr)*(100.0-REAL(g_stop_percentage)))/100.0)/g_adr_per_b)*g_adr_per_b); --percentage of max address.
CONSTANT c_zeros : STD_LOGIC_VECTOR(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
+ CONSTANT c_stop_adr_zeros : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0) := (OTHERS => '0');
-- constant for reading
CONSTANT c_rd_data_w : NATURAL := g_nof_streams*g_out_data_w; -- 168
- CONSTANT c_rest : NATURAL := c_rd_data_w-(g_wr_data_w mod c_rd_data_w); -- 96
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
-- constant for debugging
@@ -104,6 +105,10 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_low_state_ndx : NATURAL := 2;
CONSTANT c_high_state_ndx : NATURAL := 5;
CONSTANT c_state_ndx_w : NATURAL := c_high_state_ndx-c_low_state_ndx+1;
+ CONSTANT c_low_bsn_ndx : NATURAL := 8;
+ CONSTANT c_high_bsn_ndx : NATURAL := 32-1;
+ CONSTANT c_bsn_ndx_w : NATURAL := c_high_bsn_ndx-c_low_bsn_ndx+1;
+ CONSTANT c_start_bsn : NATURAL := 14;
-- type for statemachine
TYPE t_state IS (RESET, STOP_READING, WAIT_FOR_SOP, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING);
@@ -158,6 +163,7 @@ BEGIN
v := q_reg;
v.wr_sosi := inp_sosi;
+ v.ddrctrl_ctrl_state(c_high_bsn_ndx DOWNTO c_low_bsn_ndx) := inp_sosi.bsn(c_start_bsn+c_bsn_ndx_w-1 DOWNTO c_start_bsn);
CASE q_reg.state IS
@@ -258,13 +264,13 @@ BEGIN
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+g_max_adr-c_pof_ma, c_adr_w);
END IF;
v.ready_for_set_stop := '0';
- IF TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0)) = 0 THEN
- v.last_adr_to_write_to(c_adr_w-1 DOWNTO 0) := TO_UVEC(g_max_adr-g_last_burstsize, c_adr_w);
+ IF v.stop_adr(c_adr_w-1 DOWNTO 0) = c_stop_adr_zeros(c_adr_w-1 DOWNTO 0) THEN
+ v.last_adr_to_write_to(c_adr_w-1 DOWNTO 0) := TO_UVEC(g_max_adr-g_last_burstsize, c_adr_w);
ELSE
v.last_adr_to_write_to(c_adr_w-1 DOWNTO c_bitshift_w) := v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_w);
END IF;
v.last_adr_to_write_to(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
- v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0))-TO_UINT(v.last_adr_to_write_to)+1;
+ v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w-1 DOWNTO 0),-1*TO_UINT(v.last_adr_to_write_to)),1));
-- still a write cyle
-- if adr mod g_burstsize = 0
@@ -308,7 +314,7 @@ BEGIN
v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-- still receiving write data.
- v.wr_bursts_ready := TO_UINT(TO_UVEC(TO_UINT(wr_fifo_usedw)+2, g_wr_fifo_uw_w)(g_wr_fifo_uw_w-1 DOWNTO c_bitshift_w));
+ v.wr_bursts_ready := TO_UINT(INCR_UVEC(wr_fifo_usedw, 2)(g_wr_fifo_uw_w-1 DOWNTO c_bitshift_w));
IF NOT (q_reg.wr_bursts_ready = 0) AND q_reg.dvr_mosi.burstbegin = '0'THEN
v.wr_burst_en := '1';
ELSIF q_reg.wr_bursts_ready = 0 THEN
@@ -372,7 +378,7 @@ BEGIN
v.read_adr := g_burstsize;
ELSE
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize-q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w);
+ v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := INCR_UVEC(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0), q_reg.stop_burstsize);
v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+g_burstsize;
END IF;
v.dvr_mosi.burstbegin := '1';
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
index 0c38238cf32190098ee91ee7f27916fb9c9e0245..53dc621af7f466d5718836938c8a1755144f5061 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -219,7 +219,7 @@ BEGIN
IF rst = '1' THEN
v.state := RESET;
- ELSIF q_reg.state = RESET OR (q_reg.valid_data = '0' AND q_reg.state = OFF) OR (((g_bim+TO_UINT(in_bsn)-1) = TO_UINT(q_reg.out_sosi.bsn)) AND v.out_sosi.eop = '1') THEN
+ ELSIF q_reg.state = RESET OR (q_reg.valid_data = '0' AND q_reg.state = OFF) OR ((INCR_UVEC(INCR_UVEC(in_bsn, g_bim), -1)(q_reg.out_sosi.bsn'length-1 DOWNTO 0) = q_reg.out_sosi.bsn(q_reg.out_sosi.bsn'length-1 DOWNTO 0)) AND v.out_sosi.eop = '1') THEN
v.state := OFF;
ELSIF q_reg.state = OFF THEN
v.state_off := '0';
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 1c9f5effb8ebcd447806fc3e44b69113220974af..aee6a046f1ff815f50906b1f9a191255d4542aab 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -202,7 +202,8 @@ ENTITY io_ddr IS
wr_fifo_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_wr_data_w) )-1 DOWNTO 0); -- for monitoring purposes
wr_sosi : IN t_dp_sosi;
wr_siso : OUT t_dp_siso;
-
+ ctlr_wr_flush_en_o : OUT STD_LOGIC;
+
-- Read FIFO clock domain
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
@@ -284,6 +285,8 @@ ARCHITECTURE str OF io_ddr IS
BEGIN
+ ctlr_wr_flush_en_o <= ctlr_wr_flush_en;
+
u_io_ddr_cross_domain : ENTITY work.io_ddr_cross_domain
GENERIC MAP (
g_cross_domain => g_cross_domain_dvr_ctlr,