From 5d85a29517244294cfa25af63ed2a4d452dd4d8e Mon Sep 17 00:00:00 2001
From: Zanting <zanting>
Date: Fri, 14 Aug 2015 14:32:12 +0000
Subject: [PATCH] Added new ddr versions

---
 .../unb1_test/quartus/qsys_unb1_test.qsys     | 1201 +++++++------
 .../quartus/unb1_test_pins_constraints.tcl    | 1537 +++++++++++------
 2 files changed, 1672 insertions(+), 1066 deletions(-)

diff --git a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
index 3b96557c53..26b6ad78e4 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
+++ b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
@@ -65,99 +65,99 @@
          type = "String";
       }
    }
-   element reg_diag_data_buffer_10GbE.mem
+   element reg_diag_tx_seq_ddr_MB_II.mem
    {
       datum baseAddress
       {
-         value = "12416";
+         value = "983104";
          type = "long";
       }
    }
-   element reg_mmdp_data.mem
+   element reg_dp_offload_tx_10GbE.mem
    {
       datum baseAddress
       {
-         value = "53288";
+         value = "13184";
          type = "long";
       }
    }
-   element reg_dp_offload_rx_10GbE_hdr_dat.mem
+   element ram_diag_data_buffer_1GbE.mem
    {
       datum baseAddress
       {
-         value = "13312";
+         value = "65536";
          type = "long";
       }
    }
-   element reg_diag_data_buffer_ddr.mem
+   element reg_dp_offload_tx_10GbE_hdr_dat.mem
    {
       datum baseAddress
       {
-         value = "12544";
+         value = "1024";
          type = "long";
       }
    }
-   element reg_unb_sens.mem
+   element reg_diag_rx_seq_ddr_MB_I.mem
    {
       datum baseAddress
       {
-         value = "12992";
+         value = "13280";
          type = "long";
       }
    }
-   element reg_diag_bg_10GbE.mem
+   element reg_dpmm_ctrl.mem
    {
       datum baseAddress
       {
-         value = "13152";
+         value = "983120";
          type = "long";
       }
    }
-   element reg_remu.mem
+   element reg_io_ddr_MB_I.mem
    {
       datum baseAddress
       {
-         value = "13024";
+         value = "262144";
          type = "long";
       }
    }
-   element reg_dpmm_ctrl.mem
+   element reg_diag_rx_seq_10gbe.mem
    {
       datum baseAddress
       {
-         value = "53264";
+         value = "12544";
          type = "long";
       }
    }
-   element reg_diag_rx_seq_ddr.mem
+   element reg_diag_rx_seq_ddr_MB_II.mem
    {
       datum baseAddress
       {
-         value = "13248";
+         value = "983040";
          type = "long";
       }
    }
-   element reg_diag_bg_ddr.mem
+   element ram_diag_data_buffer_ddr_MB_II.mem
    {
       datum baseAddress
       {
-         value = "13184";
+         value = "49152";
          type = "long";
       }
    }
-   element reg_bsn_monitor_10GbE.mem
+   element reg_io_ddr_MB_II.mem
    {
       datum baseAddress
       {
-         value = "768";
+         value = "524288";
          type = "long";
       }
    }
-   element reg_bsn_monitor_1GbE.mem
+   element ram_diag_bg_10GbE.mem
    {
       datum baseAddress
       {
-         value = "12800";
+         value = "16384";
          type = "long";
       }
    }
@@ -165,156 +165,172 @@
    {
       datum baseAddress
       {
-         value = "12928";
+         value = "12992";
          type = "long";
       }
    }
-   element ram_ss_ss_wide.mem
+   element reg_remu.mem
    {
       datum baseAddress
       {
-         value = "393216";
+         value = "13088";
          type = "long";
       }
    }
-   element reg_io_ddr.mem
+   element reg_dp_offload_tx_1GbE.mem
    {
       datum baseAddress
       {
-         value = "13280";
+         value = "983160";
          type = "long";
       }
    }
-   element pio_pps.mem
+   element reg_bsn_monitor_1GbE.mem
    {
       datum baseAddress
       {
-         value = "53296";
+         value = "12928";
          type = "long";
       }
    }
-   element reg_diag_tx_seq_ddr.mem
+   element ram_diag_data_buffer_ddr_MB_I.mem
    {
       datum baseAddress
       {
-         value = "53248";
+         value = "40960";
          type = "long";
       }
    }
-   element reg_diag_bg_1GbE.mem
+   element reg_tr_10GbE.mem
    {
       datum baseAddress
       {
-         value = "13088";
+         value = "786432";
          type = "long";
       }
    }
-   element ram_diag_bg_ddr.mem
+   element reg_dpmm_data.mem
    {
       datum baseAddress
       {
-         value = "49152";
+         value = "983128";
          type = "long";
       }
    }
-   element ram_diag_data_buffer_10GbE.mem
+   element reg_dp_offload_rx_1GbE_hdr_dat.mem
    {
       datum baseAddress
       {
-         value = "458752";
+         value = "256";
          type = "long";
       }
    }
-   element ram_diag_bg_10GbE.mem
+   element rom_system_info.mem
    {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
       datum baseAddress
       {
-         value = "16384";
+         value = "4096";
          type = "long";
       }
    }
-   element reg_dp_offload_tx_1GbE.mem
+   element reg_unb_sens.mem
    {
       datum baseAddress
       {
-         value = "53304";
+         value = "13056";
          type = "long";
       }
    }
-   element reg_dpmm_data.mem
+   element reg_diag_data_buffer_ddr_MB_I.mem
    {
       datum baseAddress
       {
-         value = "53272";
+         value = "12672";
          type = "long";
       }
    }
-   element reg_diag_rx_seq_1gbe.mem
+   element reg_mmdp_data.mem
    {
       datum baseAddress
       {
-         value = "13216";
+         value = "983144";
          type = "long";
       }
    }
-   element ram_diag_bg_1GbE.mem
+   element reg_diag_data_buffer_10GbE.mem
    {
       datum baseAddress
       {
-         value = "45056";
+         value = "12416";
          type = "long";
       }
    }
-   element reg_dp_offload_rx_1GbE_hdr_dat.mem
+   element reg_bsn_monitor_10GbE.mem
    {
       datum baseAddress
       {
-         value = "256";
+         value = "768";
          type = "long";
       }
    }
-   element reg_tr_xaui.mem
+   element pio_pps.mem
    {
       datum baseAddress
       {
-         value = "32768";
+         value = "983152";
          type = "long";
       }
    }
-   element ram_diag_data_buffer_1GbE.mem
+   element reg_diag_data_buffer_ddr_MB_II.mem
    {
       datum baseAddress
       {
-         value = "65536";
+         value = "12800";
          type = "long";
       }
    }
-   element reg_wdi.mem
+   element reg_mmdp_ctrl.mem
    {
-      datum _lockedAddress
+      datum baseAddress
       {
-         value = "1";
-         type = "boolean";
+         value = "983136";
+         type = "long";
       }
+   }
+   element reg_diag_rx_seq_1gbe.mem
+   {
       datum baseAddress
       {
-         value = "12288";
+         value = "13248";
          type = "long";
       }
    }
-   element reg_diag_rx_seq_10gbe.mem
+   element reg_dp_offload_rx_10GbE_hdr_dat.mem
    {
       datum baseAddress
       {
-         value = "12672";
+         value = "13312";
          type = "long";
       }
    }
-   element reg_epcs.mem
+   element reg_diag_data_buffer_1GbE.mem
    {
       datum baseAddress
       {
-         value = "13056";
+         value = "128";
+         type = "long";
+      }
+   }
+   element ram_diag_data_buffer_10GbE.mem
+   {
+      datum baseAddress
+      {
+         value = "917504";
          type = "long";
       }
    }
@@ -331,71 +347,71 @@
          type = "long";
       }
    }
-   element reg_tr_10GbE.mem
+   element reg_diag_bg_10GbE.mem
    {
       datum baseAddress
       {
-         value = "262144";
+         value = "13216";
          type = "long";
       }
    }
-   element reg_dp_offload_tx_1GbE_hdr_dat.mem
+   element reg_epcs.mem
    {
       datum baseAddress
       {
-         value = "512";
+         value = "13120";
          type = "long";
       }
    }
-   element reg_mmdp_ctrl.mem
+   element reg_tr_xaui.mem
    {
       datum baseAddress
       {
-         value = "53280";
+         value = "32768";
          type = "long";
       }
    }
-   element reg_bsn_monitor_ddr.mem
+   element reg_diag_tx_seq_1gbe.mem
    {
       datum baseAddress
       {
-         value = "12864";
+         value = "983072";
          type = "long";
       }
    }
-   element ram_diag_data_buffer_ddr.mem
+   element ram_diag_bg_1GbE.mem
    {
       datum baseAddress
       {
-         value = "524288";
+         value = "61440";
          type = "long";
       }
    }
-   element reg_diag_data_buffer_1GbE.mem
+   element reg_diag_tx_seq_ddr_MB_I.mem
    {
       datum baseAddress
       {
-         value = "128";
+         value = "983088";
          type = "long";
       }
    }
-   element reg_dp_offload_tx_10GbE_hdr_dat.mem
+   element reg_diag_bg_1GbE.mem
    {
       datum baseAddress
       {
-         value = "1024";
+         value = "13152";
          type = "long";
       }
    }
-   element reg_diag_tx_seq_1gbe.mem
+   element reg_dp_offload_tx_1GbE_hdr_dat.mem
    {
       datum baseAddress
       {
-         value = "13296";
+         value = "512";
          type = "long";
       }
    }
-   element rom_system_info.mem
+   element reg_wdi.mem
    {
       datum _lockedAddress
       {
@@ -404,15 +420,7 @@
       }
       datum baseAddress
       {
-         value = "4096";
-         type = "long";
-      }
-   }
-   element reg_dp_offload_tx_10GbE.mem
-   {
-      datum baseAddress
-      {
-         value = "13120";
+         value = "12288";
          type = "long";
       }
    }
@@ -420,7 +428,7 @@
    {
       datum baseAddress
       {
-         value = "40960";
+         value = "57344";
          type = "long";
       }
    }
@@ -486,7 +494,7 @@
    {
       datum _sortIndex
       {
-         value = "33";
+         value = "31";
          type = "int";
       }
    }
@@ -494,15 +502,7 @@
    {
       datum _sortIndex
       {
-         value = "32";
-         type = "int";
-      }
-   }
-   element ram_diag_bg_ddr
-   {
-      datum _sortIndex
-      {
-         value = "34";
+         value = "30";
          type = "int";
       }
    }
@@ -510,7 +510,7 @@
    {
       datum _sortIndex
       {
-         value = "39";
+         value = "35";
          type = "int";
       }
    }
@@ -518,23 +518,23 @@
    {
       datum _sortIndex
       {
-         value = "38";
+         value = "34";
          type = "int";
       }
    }
-   element ram_diag_data_buffer_ddr
+   element ram_diag_data_buffer_ddr_MB_I
    {
       datum _sortIndex
       {
-         value = "40";
+         value = "48";
          type = "int";
       }
    }
-   element ram_ss_ss_wide
+   element ram_diag_data_buffer_ddr_MB_II
    {
       datum _sortIndex
       {
-         value = "47";
+         value = "49";
          type = "int";
       }
    }
@@ -554,55 +554,55 @@
          type = "int";
       }
    }
-   element reg_bsn_monitor_ddr
+   element reg_diag_bg_10GbE
    {
       datum _sortIndex
       {
-         value = "22";
+         value = "29";
          type = "int";
       }
    }
-   element reg_diag_bg_10GbE
+   element reg_diag_bg_1GbE
    {
       datum _sortIndex
       {
-         value = "30";
+         value = "28";
          type = "int";
       }
    }
-   element reg_diag_bg_1GbE
+   element reg_diag_data_buffer_10GbE
    {
       datum _sortIndex
       {
-         value = "29";
+         value = "33";
          type = "int";
       }
    }
-   element reg_diag_bg_ddr
+   element reg_diag_data_buffer_1GbE
    {
       datum _sortIndex
       {
-         value = "31";
+         value = "32";
          type = "int";
       }
    }
-   element reg_diag_data_buffer_10GbE
+   element reg_diag_data_buffer_ddr_MB_I
    {
       datum _sortIndex
       {
-         value = "36";
+         value = "46";
          type = "int";
       }
    }
-   element reg_diag_data_buffer_1GbE
+   element reg_diag_data_buffer_ddr_MB_II
    {
       datum _sortIndex
       {
-         value = "35";
+         value = "47";
          type = "int";
       }
    }
-   element reg_diag_data_buffer_ddr
+   element reg_diag_rx_seq_10gbe
    {
       datum _sortIndex
       {
@@ -610,15 +610,15 @@
          type = "int";
       }
    }
-   element reg_diag_rx_seq_10gbe
+   element reg_diag_rx_seq_1gbe
    {
       datum _sortIndex
       {
-         value = "42";
+         value = "39";
          type = "int";
       }
    }
-   element reg_diag_rx_seq_1gbe
+   element reg_diag_rx_seq_ddr_MB_I
    {
       datum _sortIndex
       {
@@ -626,11 +626,11 @@
          type = "int";
       }
    }
-   element reg_diag_rx_seq_ddr
+   element reg_diag_rx_seq_ddr_MB_II
    {
       datum _sortIndex
       {
-         value = "46";
+         value = "45";
          type = "int";
       }
    }
@@ -638,7 +638,7 @@
    {
       datum _sortIndex
       {
-         value = "41";
+         value = "36";
          type = "int";
       }
    }
@@ -646,15 +646,23 @@
    {
       datum _sortIndex
       {
-         value = "43";
+         value = "38";
          type = "int";
       }
    }
-   element reg_diag_tx_seq_ddr
+   element reg_diag_tx_seq_ddr_MB_I
    {
       datum _sortIndex
       {
-         value = "45";
+         value = "42";
+         type = "int";
+      }
+   }
+   element reg_diag_tx_seq_ddr_MB_II
+   {
+      datum _sortIndex
+      {
+         value = "43";
          type = "int";
       }
    }
@@ -662,7 +670,7 @@
    {
       datum _sortIndex
       {
-         value = "28";
+         value = "27";
          type = "int";
       }
    }
@@ -670,7 +678,7 @@
    {
       datum _sortIndex
       {
-         value = "27";
+         value = "26";
          type = "int";
       }
    }
@@ -678,7 +686,7 @@
    {
       datum _sortIndex
       {
-         value = "24";
+         value = "23";
          type = "int";
       }
    }
@@ -686,7 +694,7 @@
    {
       datum _sortIndex
       {
-         value = "26";
+         value = "25";
          type = "int";
       }
    }
@@ -694,7 +702,7 @@
    {
       datum _sortIndex
       {
-         value = "23";
+         value = "22";
          type = "int";
       }
    }
@@ -702,7 +710,7 @@
    {
       datum _sortIndex
       {
-         value = "25";
+         value = "24";
          type = "int";
       }
    }
@@ -730,11 +738,19 @@
          type = "int";
       }
    }
-   element reg_io_ddr
+   element reg_io_ddr_MB_I
    {
       datum _sortIndex
       {
-         value = "48";
+         value = "40";
+         type = "int";
+      }
+   }
+   element reg_io_ddr_MB_II
+   {
+      datum _sortIndex
+      {
+         value = "41";
          type = "int";
       }
    }
@@ -802,6 +818,14 @@
          type = "int";
       }
    }
+   element timer_0.s1
+   {
+      datum baseAddress
+      {
+         value = "12320";
+         type = "long";
+      }
+   }
    element onchip_memory2_0.s1
    {
       datum _lockedAddress
@@ -815,14 +839,6 @@
          type = "long";
       }
    }
-   element timer_0.s1
-   {
-      datum baseAddress
-      {
-         value = "12320";
-         type = "long";
-      }
-   }
    element pio_wdi.s1
    {
       datum baseAddress
@@ -854,7 +870,7 @@
  <parameter name="projectName" value="" />
  <parameter name="sopcBorderPoints" value="false" />
  <parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1430735732056" />
+ <parameter name="timeStamp" value="1438699704726" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface
@@ -1848,113 +1864,43 @@
    type="conduit"
    dir="end" />
  <interface
-   name="ram_ss_ss_wide_readdata"
-   internal="ram_ss_ss_wide.readdata"
+   name="reg_diag_data_buffer_10gbe_readdata"
+   internal="reg_diag_data_buffer_10GbE.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_ss_ss_wide_read"
-   internal="ram_ss_ss_wide.read"
+   name="reg_diag_data_buffer_10gbe_read"
+   internal="reg_diag_data_buffer_10GbE.read"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_ss_ss_wide_writedata"
-   internal="ram_ss_ss_wide.writedata"
+   name="reg_diag_data_buffer_10gbe_writedata"
+   internal="reg_diag_data_buffer_10GbE.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_ss_ss_wide_write"
-   internal="ram_ss_ss_wide.write"
+   name="reg_diag_data_buffer_10gbe_write"
+   internal="reg_diag_data_buffer_10GbE.write"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_ss_ss_wide_address"
-   internal="ram_ss_ss_wide.address"
+   name="reg_diag_data_buffer_10gbe_address"
+   internal="reg_diag_data_buffer_10GbE.address"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_ss_ss_wide_clk"
-   internal="ram_ss_ss_wide.clk"
+   name="reg_diag_data_buffer_10gbe_clk"
+   internal="reg_diag_data_buffer_10GbE.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_ss_ss_wide_reset"
-   internal="ram_ss_ss_wide.reset"
+   name="reg_diag_data_buffer_10gbe_reset"
+   internal="reg_diag_data_buffer_10GbE.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_io_ddr_readdata"
-   internal="reg_io_ddr.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_io_ddr_read"
-   internal="reg_io_ddr.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_io_ddr_writedata"
-   internal="reg_io_ddr.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_io_ddr_write"
-   internal="reg_io_ddr.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_io_ddr_address"
-   internal="reg_io_ddr.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_io_ddr_clk"
-   internal="reg_io_ddr.clk"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_io_ddr_reset"
-   internal="reg_io_ddr.reset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diag_data_buffer_10gbe_readdata"
-   internal="reg_diag_data_buffer_10GbE.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diag_data_buffer_10gbe_read"
-   internal="reg_diag_data_buffer_10GbE.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diag_data_buffer_10gbe_writedata"
-   internal="reg_diag_data_buffer_10GbE.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diag_data_buffer_10gbe_write"
-   internal="reg_diag_data_buffer_10GbE.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diag_data_buffer_10gbe_address"
-   internal="reg_diag_data_buffer_10GbE.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diag_data_buffer_10gbe_clk"
-   internal="reg_diag_data_buffer_10GbE.clk"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diag_data_buffer_10gbe_reset"
-   internal="reg_diag_data_buffer_10GbE.reset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_diag_bg_10gbe_readdata"
-   internal="ram_diag_bg_10GbE.readdata"
+   name="ram_diag_bg_10gbe_readdata"
+   internal="ram_diag_bg_10GbE.readdata"
    type="conduit"
    dir="end" />
  <interface
@@ -2443,388 +2389,493 @@
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_ddr_readdata"
-   internal="reg_bsn_monitor_ddr.readdata"
+   name="reg_diag_rx_seq_1gbe_readdata"
+   internal="reg_diag_rx_seq_1gbe.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_ddr_read"
-   internal="reg_bsn_monitor_ddr.read"
+   name="reg_diag_rx_seq_1gbe_read"
+   internal="reg_diag_rx_seq_1gbe.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_ddr_writedata"
-   internal="reg_bsn_monitor_ddr.writedata"
+   name="reg_diag_rx_seq_1gbe_writedata"
+   internal="reg_diag_rx_seq_1gbe.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_ddr_write"
-   internal="reg_bsn_monitor_ddr.write"
+   name="reg_diag_rx_seq_1gbe_write"
+   internal="reg_diag_rx_seq_1gbe.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_ddr_address"
-   internal="reg_bsn_monitor_ddr.address"
+   name="reg_diag_rx_seq_1gbe_address"
+   internal="reg_diag_rx_seq_1gbe.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_ddr_clk"
-   internal="reg_bsn_monitor_ddr.clk"
+   name="reg_diag_rx_seq_1gbe_clk"
+   internal="reg_diag_rx_seq_1gbe.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_ddr_reset"
-   internal="reg_bsn_monitor_ddr.reset"
+   name="reg_diag_rx_seq_1gbe_reset"
+   internal="reg_diag_rx_seq_1gbe.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_bg_ddr_readdata"
-   internal="reg_diag_bg_ddr.readdata"
+   name="reg_diag_tx_seq_1gbe_readdata"
+   internal="reg_diag_tx_seq_1gbe.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_bg_ddr_read"
-   internal="reg_diag_bg_ddr.read"
+   name="reg_diag_tx_seq_1gbe_read"
+   internal="reg_diag_tx_seq_1gbe.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_bg_ddr_writedata"
-   internal="reg_diag_bg_ddr.writedata"
+   name="reg_diag_tx_seq_1gbe_writedata"
+   internal="reg_diag_tx_seq_1gbe.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_bg_ddr_write"
-   internal="reg_diag_bg_ddr.write"
+   name="reg_diag_tx_seq_1gbe_write"
+   internal="reg_diag_tx_seq_1gbe.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_bg_ddr_address"
-   internal="reg_diag_bg_ddr.address"
+   name="reg_diag_tx_seq_1gbe_address"
+   internal="reg_diag_tx_seq_1gbe.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_bg_ddr_clk"
-   internal="reg_diag_bg_ddr.clk"
+   name="reg_diag_tx_seq_1gbe_clk"
+   internal="reg_diag_tx_seq_1gbe.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_bg_ddr_reset"
-   internal="reg_diag_bg_ddr.reset"
+   name="reg_diag_tx_seq_1gbe_reset"
+   internal="reg_diag_tx_seq_1gbe.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_bg_ddr_readdata"
-   internal="ram_diag_bg_ddr.readdata"
+   name="reg_diag_rx_seq_10gbe_readdata"
+   internal="reg_diag_rx_seq_10gbe.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_bg_ddr_read"
-   internal="ram_diag_bg_ddr.read"
+   name="reg_diag_rx_seq_10gbe_read"
+   internal="reg_diag_rx_seq_10gbe.read"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_bg_ddr_writedata"
-   internal="ram_diag_bg_ddr.writedata"
+   name="reg_diag_rx_seq_10gbe_writedata"
+   internal="reg_diag_rx_seq_10gbe.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_bg_ddr_write"
-   internal="ram_diag_bg_ddr.write"
+   name="reg_diag_rx_seq_10gbe_write"
+   internal="reg_diag_rx_seq_10gbe.write"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_bg_ddr_address"
-   internal="ram_diag_bg_ddr.address"
+   name="reg_diag_rx_seq_10gbe_address"
+   internal="reg_diag_rx_seq_10gbe.address"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_bg_ddr_clk"
-   internal="ram_diag_bg_ddr.clk"
+   name="reg_diag_rx_seq_10gbe_clk"
+   internal="reg_diag_rx_seq_10gbe.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_bg_ddr_reset"
-   internal="ram_diag_bg_ddr.reset"
+   name="reg_diag_rx_seq_10gbe_reset"
+   internal="reg_diag_rx_seq_10gbe.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_data_buffer_ddr_readdata"
-   internal="reg_diag_data_buffer_ddr.readdata"
+   name="reg_diag_tx_seq_10gbe_readdata"
+   internal="reg_diag_tx_seq_10gbe.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_data_buffer_ddr_read"
-   internal="reg_diag_data_buffer_ddr.read"
+   name="reg_diag_tx_seq_10gbe_read"
+   internal="reg_diag_tx_seq_10gbe.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_data_buffer_ddr_writedata"
-   internal="reg_diag_data_buffer_ddr.writedata"
+   name="reg_diag_tx_seq_10gbe_writedata"
+   internal="reg_diag_tx_seq_10gbe.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_data_buffer_ddr_write"
-   internal="reg_diag_data_buffer_ddr.write"
+   name="reg_diag_tx_seq_10gbe_write"
+   internal="reg_diag_tx_seq_10gbe.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_data_buffer_ddr_address"
-   internal="reg_diag_data_buffer_ddr.address"
+   name="reg_diag_tx_seq_10gbe_address"
+   internal="reg_diag_tx_seq_10gbe.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_data_buffer_ddr_clk"
-   internal="reg_diag_data_buffer_ddr.clk"
+   name="reg_diag_tx_seq_10gbe_clk"
+   internal="reg_diag_tx_seq_10gbe.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_data_buffer_ddr_reset"
-   internal="reg_diag_data_buffer_ddr.reset"
+   name="reg_diag_tx_seq_10gbe_reset"
+   internal="reg_diag_tx_seq_10gbe.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buffer_ddr_readdata"
-   internal="ram_diag_data_buffer_ddr.readdata"
+   name="reg_io_ddr_mb_i_reset"
+   internal="reg_io_ddr_MB_I.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buffer_ddr_read"
-   internal="ram_diag_data_buffer_ddr.read"
+   name="reg_io_ddr_mb_i_clk"
+   internal="reg_io_ddr_MB_I.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buffer_ddr_writedata"
-   internal="ram_diag_data_buffer_ddr.writedata"
+   name="reg_io_ddr_mb_i_address"
+   internal="reg_io_ddr_MB_I.address"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buffer_ddr_write"
-   internal="ram_diag_data_buffer_ddr.write"
+   name="reg_io_ddr_mb_i_write"
+   internal="reg_io_ddr_MB_I.write"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buffer_ddr_address"
-   internal="ram_diag_data_buffer_ddr.address"
+   name="reg_io_ddr_mb_i_writedata"
+   internal="reg_io_ddr_MB_I.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buffer_ddr_clk"
-   internal="ram_diag_data_buffer_ddr.clk"
+   name="reg_io_ddr_mb_i_read"
+   internal="reg_io_ddr_MB_I.read"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buffer_ddr_reset"
-   internal="ram_diag_data_buffer_ddr.reset"
+   name="reg_io_ddr_mb_i_readdata"
+   internal="reg_io_ddr_MB_I.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_ddr_readdata"
-   internal="reg_diag_rx_seq_ddr.readdata"
+   name="reg_io_ddr_mb_ii_reset"
+   internal="reg_io_ddr_MB_II.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_ddr_read"
-   internal="reg_diag_rx_seq_ddr.read"
+   name="reg_io_ddr_mb_ii_clk"
+   internal="reg_io_ddr_MB_II.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_ddr_writedata"
-   internal="reg_diag_rx_seq_ddr.writedata"
+   name="reg_io_ddr_mb_ii_address"
+   internal="reg_io_ddr_MB_II.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_ddr_write"
-   internal="reg_diag_rx_seq_ddr.write"
+   name="reg_io_ddr_mb_ii_write"
+   internal="reg_io_ddr_MB_II.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_ddr_address"
-   internal="reg_diag_rx_seq_ddr.address"
+   name="reg_io_ddr_mb_ii_writedata"
+   internal="reg_io_ddr_MB_II.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_ddr_clk"
-   internal="reg_diag_rx_seq_ddr.clk"
+   name="reg_io_ddr_mb_ii_read"
+   internal="reg_io_ddr_MB_II.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_ddr_reset"
-   internal="reg_diag_rx_seq_ddr.reset"
+   name="reg_io_ddr_mb_ii_readdata"
+   internal="reg_io_ddr_MB_II.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_ddr_readdata"
-   internal="reg_diag_tx_seq_ddr.readdata"
+   name="reg_diag_tx_seq_ddr_mb_i_reset"
+   internal="reg_diag_tx_seq_ddr_MB_I.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_ddr_read"
-   internal="reg_diag_tx_seq_ddr.read"
+   name="reg_diag_tx_seq_ddr_mb_i_clk"
+   internal="reg_diag_tx_seq_ddr_MB_I.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_ddr_writedata"
-   internal="reg_diag_tx_seq_ddr.writedata"
+   name="reg_diag_tx_seq_ddr_mb_i_address"
+   internal="reg_diag_tx_seq_ddr_MB_I.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_ddr_write"
-   internal="reg_diag_tx_seq_ddr.write"
+   name="reg_diag_tx_seq_ddr_mb_i_write"
+   internal="reg_diag_tx_seq_ddr_MB_I.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_ddr_address"
-   internal="reg_diag_tx_seq_ddr.address"
+   name="reg_diag_tx_seq_ddr_mb_i_writedata"
+   internal="reg_diag_tx_seq_ddr_MB_I.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_ddr_clk"
-   internal="reg_diag_tx_seq_ddr.clk"
+   name="reg_diag_tx_seq_ddr_mb_i_read"
+   internal="reg_diag_tx_seq_ddr_MB_I.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_ddr_reset"
-   internal="reg_diag_tx_seq_ddr.reset"
+   name="reg_diag_tx_seq_ddr_mb_i_readdata"
+   internal="reg_diag_tx_seq_ddr_MB_I.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_1gbe_readdata"
-   internal="reg_diag_rx_seq_1gbe.readdata"
+   name="reg_diag_tx_seq_ddr_mb_ii_reset"
+   internal="reg_diag_tx_seq_ddr_MB_II.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_1gbe_read"
-   internal="reg_diag_rx_seq_1gbe.read"
+   name="reg_diag_tx_seq_ddr_mb_ii_clk"
+   internal="reg_diag_tx_seq_ddr_MB_II.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_1gbe_writedata"
-   internal="reg_diag_rx_seq_1gbe.writedata"
+   name="reg_diag_tx_seq_ddr_mb_ii_address"
+   internal="reg_diag_tx_seq_ddr_MB_II.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_1gbe_write"
-   internal="reg_diag_rx_seq_1gbe.write"
+   name="reg_diag_tx_seq_ddr_mb_ii_write"
+   internal="reg_diag_tx_seq_ddr_MB_II.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_1gbe_address"
-   internal="reg_diag_rx_seq_1gbe.address"
+   name="reg_diag_tx_seq_ddr_mb_ii_writedata"
+   internal="reg_diag_tx_seq_ddr_MB_II.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_1gbe_clk"
-   internal="reg_diag_rx_seq_1gbe.clk"
+   name="reg_diag_tx_seq_ddr_mb_ii_read"
+   internal="reg_diag_tx_seq_ddr_MB_II.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_1gbe_reset"
-   internal="reg_diag_rx_seq_1gbe.reset"
+   name="reg_diag_tx_seq_ddr_mb_ii_readdata"
+   internal="reg_diag_tx_seq_ddr_MB_II.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_1gbe_readdata"
-   internal="reg_diag_tx_seq_1gbe.readdata"
+   name="reg_diag_rx_seq_ddr_mb_i_reset"
+   internal="reg_diag_rx_seq_ddr_MB_I.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_1gbe_read"
-   internal="reg_diag_tx_seq_1gbe.read"
+   name="reg_diag_rx_seq_ddr_mb_i_clk"
+   internal="reg_diag_rx_seq_ddr_MB_I.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_1gbe_writedata"
-   internal="reg_diag_tx_seq_1gbe.writedata"
+   name="reg_diag_rx_seq_ddr_mb_i_address"
+   internal="reg_diag_rx_seq_ddr_MB_I.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_1gbe_write"
-   internal="reg_diag_tx_seq_1gbe.write"
+   name="reg_diag_rx_seq_ddr_mb_i_write"
+   internal="reg_diag_rx_seq_ddr_MB_I.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_1gbe_address"
-   internal="reg_diag_tx_seq_1gbe.address"
+   name="reg_diag_rx_seq_ddr_mb_i_writedata"
+   internal="reg_diag_rx_seq_ddr_MB_I.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_1gbe_clk"
-   internal="reg_diag_tx_seq_1gbe.clk"
+   name="reg_diag_rx_seq_ddr_mb_i_read"
+   internal="reg_diag_rx_seq_ddr_MB_I.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_1gbe_reset"
-   internal="reg_diag_tx_seq_1gbe.reset"
+   name="reg_diag_rx_seq_ddr_mb_i_readdata"
+   internal="reg_diag_rx_seq_ddr_MB_I.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_10gbe_readdata"
-   internal="reg_diag_rx_seq_10gbe.readdata"
+   name="reg_diag_rx_seq_ddr_mb_ii_reset"
+   internal="reg_diag_rx_seq_ddr_MB_II.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_10gbe_read"
-   internal="reg_diag_rx_seq_10gbe.read"
+   name="reg_diag_rx_seq_ddr_mb_ii_clk"
+   internal="reg_diag_rx_seq_ddr_MB_II.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_10gbe_writedata"
-   internal="reg_diag_rx_seq_10gbe.writedata"
+   name="reg_diag_rx_seq_ddr_mb_ii_address"
+   internal="reg_diag_rx_seq_ddr_MB_II.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_10gbe_write"
-   internal="reg_diag_rx_seq_10gbe.write"
+   name="reg_diag_rx_seq_ddr_mb_ii_write"
+   internal="reg_diag_rx_seq_ddr_MB_II.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_10gbe_address"
-   internal="reg_diag_rx_seq_10gbe.address"
+   name="reg_diag_rx_seq_ddr_mb_ii_writedata"
+   internal="reg_diag_rx_seq_ddr_MB_II.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_10gbe_clk"
-   internal="reg_diag_rx_seq_10gbe.clk"
+   name="reg_diag_rx_seq_ddr_mb_ii_read"
+   internal="reg_diag_rx_seq_ddr_MB_II.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_rx_seq_10gbe_reset"
-   internal="reg_diag_rx_seq_10gbe.reset"
+   name="reg_diag_rx_seq_ddr_mb_ii_readdata"
+   internal="reg_diag_rx_seq_ddr_MB_II.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_10gbe_readdata"
-   internal="reg_diag_tx_seq_10gbe.readdata"
+   name="reg_diag_data_buffer_ddr_mb_i_reset"
+   internal="reg_diag_data_buffer_ddr_MB_I.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_10gbe_read"
-   internal="reg_diag_tx_seq_10gbe.read"
+   name="reg_diag_data_buffer_ddr_mb_i_clk"
+   internal="reg_diag_data_buffer_ddr_MB_I.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_10gbe_writedata"
-   internal="reg_diag_tx_seq_10gbe.writedata"
+   name="reg_diag_data_buffer_ddr_mb_i_address"
+   internal="reg_diag_data_buffer_ddr_MB_I.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_10gbe_write"
-   internal="reg_diag_tx_seq_10gbe.write"
+   name="reg_diag_data_buffer_ddr_mb_i_write"
+   internal="reg_diag_data_buffer_ddr_MB_I.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_10gbe_address"
-   internal="reg_diag_tx_seq_10gbe.address"
+   name="reg_diag_data_buffer_ddr_mb_i_writedata"
+   internal="reg_diag_data_buffer_ddr_MB_I.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_10gbe_clk"
-   internal="reg_diag_tx_seq_10gbe.clk"
+   name="reg_diag_data_buffer_ddr_mb_i_read"
+   internal="reg_diag_data_buffer_ddr_MB_I.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_diag_tx_seq_10gbe_reset"
-   internal="reg_diag_tx_seq_10gbe.reset"
+   name="reg_diag_data_buffer_ddr_mb_i_readdata"
+   internal="reg_diag_data_buffer_ddr_MB_I.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buffer_ddr_mb_ii_reset"
+   internal="reg_diag_data_buffer_ddr_MB_II.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buffer_ddr_mb_ii_clk"
+   internal="reg_diag_data_buffer_ddr_MB_II.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buffer_ddr_mb_ii_address"
+   internal="reg_diag_data_buffer_ddr_MB_II.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buffer_ddr_mb_ii_write"
+   internal="reg_diag_data_buffer_ddr_MB_II.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buffer_ddr_mb_ii_writedata"
+   internal="reg_diag_data_buffer_ddr_MB_II.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buffer_ddr_mb_ii_read"
+   internal="reg_diag_data_buffer_ddr_MB_II.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buffer_ddr_mb_ii_readdata"
+   internal="reg_diag_data_buffer_ddr_MB_II.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_i_reset"
+   internal="ram_diag_data_buffer_ddr_MB_I.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_i_clk"
+   internal="ram_diag_data_buffer_ddr_MB_I.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_i_address"
+   internal="ram_diag_data_buffer_ddr_MB_I.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_i_write"
+   internal="ram_diag_data_buffer_ddr_MB_I.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_i_writedata"
+   internal="ram_diag_data_buffer_ddr_MB_I.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_i_read"
+   internal="ram_diag_data_buffer_ddr_MB_I.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_i_readdata"
+   internal="ram_diag_data_buffer_ddr_MB_I.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_ii_reset"
+   internal="ram_diag_data_buffer_ddr_MB_II.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_ii_clk"
+   internal="ram_diag_data_buffer_ddr_MB_II.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_ii_address"
+   internal="ram_diag_data_buffer_ddr_MB_II.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_ii_write"
+   internal="ram_diag_data_buffer_ddr_MB_II.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_ii_writedata"
+   internal="ram_diag_data_buffer_ddr_MB_II.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_ii_read"
+   internal="ram_diag_data_buffer_ddr_MB_II.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ram_diag_data_buffer_ddr_mb_ii_readdata"
+   internal="ram_diag_data_buffer_ddr_MB_II.readdata"
    type="conduit"
    dir="end" />
  <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
@@ -3067,7 +3118,7 @@ q]]></parameter>
   <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
   <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
   <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_1GbE.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_rx_1GbE_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_1GbE_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_10GbE_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_diag_data_buffer_10GbE.mem' start='0x3080' end='0x3100' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x3100' end='0x3180' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3180' end='0x3200' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3200' end='0x3240' /><slave name='reg_bsn_monitor_ddr.mem' start='0x3240' end='0x3280' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3280' end='0x32C0' /><slave name='reg_unb_sens.mem' start='0x32C0' end='0x32E0' /><slave name='reg_remu.mem' start='0x32E0' end='0x3300' /><slave name='reg_epcs.mem' start='0x3300' end='0x3320' /><slave name='reg_diag_bg_1GbE.mem' start='0x3320' end='0x3340' /><slave name='reg_dp_offload_tx_10GbE.mem' start='0x3340' end='0x3360' /><slave name='reg_diag_bg_10GbE.mem' start='0x3360' end='0x3380' /><slave name='reg_diag_bg_ddr.mem' start='0x3380' end='0x33A0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x33A0' end='0x33C0' /><slave name='reg_diag_rx_seq_ddr.mem' start='0x33C0' end='0x33E0' /><slave name='reg_io_ddr.mem' start='0x33E0' end='0x33F0' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x33F0' end='0x3400' /><slave name='reg_dp_offload_rx_10GbE_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg_10GbE.mem' start='0x4000' end='0x8000' /><slave name='reg_tr_xaui.mem' start='0x8000' end='0xA000' /><slave name='avs_eth_0.mms_ram' start='0xA000' end='0xB000' /><slave name='ram_diag_bg_1GbE.mem' start='0xB000' end='0xC000' /><slave name='ram_diag_bg_ddr.mem' start='0xC000' end='0xD000' /><slave name='reg_diag_tx_seq_ddr.mem' start='0xD000' end='0xD010' /><slave name='reg_dpmm_ctrl.mem' start='0xD010' end='0xD018' /><slave name='reg_dpmm_data.mem' start='0xD018' end='0xD020' /><slave name='reg_mmdp_ctrl.mem' start='0xD020' end='0xD028' /><slave name='reg_mmdp_data.mem' start='0xD028' end='0xD030' /><slave name='pio_pps.mem' start='0xD030' end='0xD038' /><slave name='reg_dp_offload_tx_1GbE.mem' start='0xD038' end='0xD040' /><slave name='ram_diag_data_buffer_1GbE.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /><slave name='ram_diag_data_buffer_10GbE.mem' start='0x70000' end='0x80000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x80000' end='0x90000' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_1GbE.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_rx_1GbE_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_1GbE_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_10GbE_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_diag_data_buffer_10GbE.mem' start='0x3080' end='0x3100' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3100' end='0x3180' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3180' end='0x3200' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x3200' end='0x3280' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3280' end='0x32C0' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x32C0' end='0x3300' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3320' /><slave name='reg_remu.mem' start='0x3320' end='0x3340' /><slave name='reg_epcs.mem' start='0x3340' end='0x3360' /><slave name='reg_diag_bg_1GbE.mem' start='0x3360' end='0x3380' /><slave name='reg_dp_offload_tx_10GbE.mem' start='0x3380' end='0x33A0' /><slave name='reg_diag_bg_10GbE.mem' start='0x33A0' end='0x33C0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x33C0' end='0x33E0' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x33E0' end='0x3400' /><slave name='reg_dp_offload_rx_10GbE_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg_10GbE.mem' start='0x4000' end='0x8000' /><slave name='reg_tr_xaui.mem' start='0x8000' end='0xA000' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xA000' end='0xC000' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' /><slave name='avs_eth_0.mms_ram' start='0xE000' end='0xF000' /><slave name='ram_diag_bg_1GbE.mem' start='0xF000' end='0x10000' /><slave name='ram_diag_data_buffer_1GbE.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_io_ddr_MB_I.mem' start='0x40000' end='0x80000' /><slave name='reg_io_ddr_MB_II.mem' start='0x80000' end='0xC0000' /><slave name='reg_tr_10GbE.mem' start='0xC0000' end='0xE0000' /><slave name='ram_diag_data_buffer_10GbE.mem' start='0xE0000' end='0xF0000' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0xF0000' end='0xF0020' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0xF0020' end='0xF0030' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0xF0030' end='0xF0040' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0xF0040' end='0xF0050' /><slave name='reg_dpmm_ctrl.mem' start='0xF0050' end='0xF0058' /><slave name='reg_dpmm_data.mem' start='0xF0058' end='0xF0060' /><slave name='reg_mmdp_ctrl.mem' start='0xF0060' end='0xF0068' /><slave name='reg_mmdp_data.mem' start='0xF0068' end='0xF0070' /><slave name='pio_pps.mem' start='0xF0070' end='0xF0078' /><slave name='reg_dp_offload_tx_1GbE.mem' start='0xF0078' end='0xF0080' /></address-map>]]></parameter>
   <parameter name="clockFrequency" value="125000000" />
   <parameter name="deviceFamilyName" value="Stratix IV" />
   <parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -3154,16 +3205,6 @@ q]]></parameter>
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_ss_ss_wide">
-  <parameter name="g_adr_w" value="14" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_io_ddr">
-  <parameter name="g_adr_w" value="2" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- </module>
  <module
    kind="avs_common_mm"
    version="1.0"
@@ -3240,18 +3281,26 @@ q]]></parameter>
    kind="avs_common_mm"
    version="1.0"
    enabled="1"
-   name="reg_bsn_monitor_ddr">
+   name="reg_diag_tx_seq_10gbe">
   <parameter name="g_adr_w" value="4" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diag_bg_ddr">
-  <parameter name="g_adr_w" value="3" />
+ <module
+   kind="avs_common_mm"
+   version="1.0"
+   enabled="1"
+   name="reg_diag_rx_seq_10gbe">
+  <parameter name="g_adr_w" value="5" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg_ddr">
-  <parameter name="g_adr_w" value="10" />
+ <module
+   kind="avs_common_mm"
+   version="1.0"
+   enabled="1"
+   name="reg_diag_tx_seq_1gbe">
+  <parameter name="g_adr_w" value="2" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -3259,8 +3308,13 @@ q]]></parameter>
    kind="avs_common_mm"
    version="1.0"
    enabled="1"
-   name="reg_diag_data_buffer_ddr">
-  <parameter name="g_adr_w" value="5" />
+   name="reg_diag_rx_seq_1gbe">
+  <parameter name="g_adr_w" value="3" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_io_ddr_MB_I">
+  <parameter name="g_adr_w" value="16" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -3268,8 +3322,8 @@ q]]></parameter>
    kind="avs_common_mm"
    version="1.0"
    enabled="1"
-   name="ram_diag_data_buffer_ddr">
-  <parameter name="g_adr_w" value="14" />
+   name="reg_io_ddr_MB_II">
+  <parameter name="g_adr_w" value="16" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -3277,8 +3331,8 @@ q]]></parameter>
    kind="avs_common_mm"
    version="1.0"
    enabled="1"
-   name="reg_diag_tx_seq_10gbe">
-  <parameter name="g_adr_w" value="4" />
+   name="reg_diag_tx_seq_ddr_MB_I">
+  <parameter name="g_adr_w" value="2" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -3286,8 +3340,8 @@ q]]></parameter>
    kind="avs_common_mm"
    version="1.0"
    enabled="1"
-   name="reg_diag_rx_seq_10gbe">
-  <parameter name="g_adr_w" value="5" />
+   name="reg_diag_tx_seq_ddr_MB_II">
+  <parameter name="g_adr_w" value="2" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -3295,8 +3349,8 @@ q]]></parameter>
    kind="avs_common_mm"
    version="1.0"
    enabled="1"
-   name="reg_diag_tx_seq_1gbe">
-  <parameter name="g_adr_w" value="2" />
+   name="reg_diag_rx_seq_ddr_MB_I">
+  <parameter name="g_adr_w" value="3" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -3304,7 +3358,7 @@ q]]></parameter>
    kind="avs_common_mm"
    version="1.0"
    enabled="1"
-   name="reg_diag_rx_seq_1gbe">
+   name="reg_diag_rx_seq_ddr_MB_II">
   <parameter name="g_adr_w" value="3" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
@@ -3313,8 +3367,8 @@ q]]></parameter>
    kind="avs_common_mm"
    version="1.0"
    enabled="1"
-   name="reg_diag_tx_seq_ddr">
-  <parameter name="g_adr_w" value="2" />
+   name="reg_diag_data_buffer_ddr_MB_I">
+  <parameter name="g_adr_w" value="5" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -3322,8 +3376,26 @@ q]]></parameter>
    kind="avs_common_mm"
    version="1.0"
    enabled="1"
-   name="reg_diag_rx_seq_ddr">
-  <parameter name="g_adr_w" value="3" />
+   name="reg_diag_data_buffer_ddr_MB_II">
+  <parameter name="g_adr_w" value="5" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+   kind="avs_common_mm"
+   version="1.0"
+   enabled="1"
+   name="ram_diag_data_buffer_ddr_MB_I">
+  <parameter name="g_adr_w" value="11" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+   kind="avs_common_mm"
+   version="1.0"
+   enabled="1"
+   name="ram_diag_data_buffer_ddr_MB_II">
+  <parameter name="g_adr_w" value="11" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -3399,7 +3471,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_unb_sens.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x32c0" />
+  <parameter name="baseAddress" value="0x3300" />
  </connection>
  <connection
    kind="avalon"
@@ -3431,7 +3503,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_remu.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x32e0" />
+  <parameter name="baseAddress" value="0x3320" />
  </connection>
  <connection
    kind="avalon"
@@ -3439,7 +3511,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_dpmm_ctrl.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xd010" />
+  <parameter name="baseAddress" value="0x000f0050" />
  </connection>
  <connection
    kind="avalon"
@@ -3447,7 +3519,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_dpmm_data.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xd018" />
+  <parameter name="baseAddress" value="0x000f0058" />
  </connection>
  <connection
    kind="avalon"
@@ -3455,7 +3527,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_mmdp_ctrl.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xd020" />
+  <parameter name="baseAddress" value="0x000f0060" />
  </connection>
  <connection
    kind="avalon"
@@ -3463,7 +3535,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_mmdp_data.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xd028" />
+  <parameter name="baseAddress" value="0x000f0068" />
  </connection>
  <connection
    kind="avalon"
@@ -3471,7 +3543,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_epcs.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3300" />
+  <parameter name="baseAddress" value="0x3340" />
  </connection>
  <connection
    kind="avalon"
@@ -3479,7 +3551,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="pio_pps.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xd030" />
+  <parameter name="baseAddress" value="0x000f0070" />
  </connection>
  <connection
    kind="avalon"
@@ -3487,7 +3559,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_tr_10GbE.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00040000" />
+  <parameter name="baseAddress" value="0x000c0000" />
  </connection>
  <connection
    kind="avalon"
@@ -3511,7 +3583,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="avs_eth_0.mms_ram">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xa000" />
+  <parameter name="baseAddress" value="0xe000" />
  </connection>
  <connection
    kind="interrupt"
@@ -3729,7 +3801,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_bsn_monitor_1GbE.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3200" />
+  <parameter name="baseAddress" value="0x3280" />
  </connection>
  <connection
    kind="reset"
@@ -3780,7 +3852,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_dp_offload_tx_1GbE.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xd038" />
+  <parameter name="baseAddress" value="0x000f0078" />
  </connection>
  <connection
    kind="avalon"
@@ -3832,7 +3904,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_diag_bg_1GbE.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3320" />
+  <parameter name="baseAddress" value="0x3360" />
  </connection>
  <connection
    kind="avalon"
@@ -3840,7 +3912,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="ram_diag_bg_1GbE.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xb000" />
+  <parameter name="baseAddress" value="0xf000" />
  </connection>
  <connection
    kind="reset"
@@ -3862,24 +3934,6 @@ q]]></parameter>
    version="11.1"
    start="clk_0.clk_reset"
    end="ram_diag_bg_1GbE.system_reset" />
- <connection
-   kind="reset"
-   version="11.1"
-   start="clk_0.clk_reset"
-   end="ram_ss_ss_wide.system_reset" />
- <connection
-   kind="reset"
-   version="11.1"
-   start="cpu_0.jtag_debug_module_reset"
-   end="ram_ss_ss_wide.system_reset" />
- <connection
-   kind="avalon"
-   version="11.1"
-   start="cpu_0.data_master"
-   end="ram_ss_ss_wide.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00060000" />
- </connection>
  <connection kind="clock" version="11.1" start="clk_0.clk" end="cpu_0.clk" />
  <connection
    kind="clock"
@@ -3979,30 +4033,6 @@ q]]></parameter>
    version="11.1"
    start="clk_0.clk"
    end="ram_diag_bg_1GbE.system" />
- <connection
-   kind="clock"
-   version="11.1"
-   start="clk_0.clk"
-   end="ram_ss_ss_wide.system" />
- <connection
-   kind="reset"
-   version="11.1"
-   start="clk_0.clk_reset"
-   end="reg_io_ddr.system_reset" />
- <connection
-   kind="reset"
-   version="11.1"
-   start="cpu_0.jtag_debug_module_reset"
-   end="reg_io_ddr.system_reset" />
- <connection kind="clock" version="11.1" start="clk_0.clk" end="reg_io_ddr.system" />
- <connection
-   kind="avalon"
-   version="11.1"
-   start="cpu_0.data_master"
-   end="reg_io_ddr.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x33e0" />
- </connection>
  <connection
    kind="reset"
    version="11.1"
@@ -4107,7 +4137,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_dp_offload_tx_10GbE.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3340" />
+  <parameter name="baseAddress" value="0x3380" />
  </connection>
  <connection
    kind="clock"
@@ -4146,7 +4176,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_diag_bg_10GbE.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3360" />
+  <parameter name="baseAddress" value="0x33a0" />
  </connection>
  <connection
    kind="clock"
@@ -4185,259 +4215,328 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="ram_diag_data_buffer_10GbE.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00070000" />
+  <parameter name="baseAddress" value="0x000e0000" />
  </connection>
  <connection
    kind="reset"
    version="11.1"
    start="clk_0.clk_reset"
-   end="reg_bsn_monitor_ddr.system_reset" />
- <connection
-   kind="reset"
-   version="11.1"
-   start="cpu_0.jtag_debug_module_reset"
-   end="reg_bsn_monitor_ddr.system_reset" />
- <connection
-   kind="reset"
-   version="11.1"
-   start="clk_0.clk_reset"
-   end="reg_diag_bg_ddr.system_reset" />
+   end="reg_diag_tx_seq_10gbe.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="cpu_0.jtag_debug_module_reset"
-   end="reg_diag_bg_ddr.system_reset" />
+   end="reg_diag_tx_seq_10gbe.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="clk_0.clk_reset"
-   end="ram_diag_bg_ddr.system_reset" />
+   end="reg_diag_rx_seq_10gbe.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="cpu_0.jtag_debug_module_reset"
-   end="ram_diag_bg_ddr.system_reset" />
+   end="reg_diag_rx_seq_10gbe.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="clk_0.clk_reset"
-   end="reg_diag_data_buffer_ddr.system_reset" />
+   end="reg_diag_tx_seq_1gbe.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="cpu_0.jtag_debug_module_reset"
-   end="reg_diag_data_buffer_ddr.system_reset" />
+   end="reg_diag_tx_seq_1gbe.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="clk_0.clk_reset"
-   end="ram_diag_data_buffer_ddr.system_reset" />
+   end="reg_diag_rx_seq_1gbe.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="cpu_0.jtag_debug_module_reset"
-   end="ram_diag_data_buffer_ddr.system_reset" />
+   end="reg_diag_rx_seq_1gbe.system_reset" />
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="reg_bsn_monitor_ddr.system" />
+   end="reg_diag_tx_seq_10gbe.system" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="reg_bsn_monitor_ddr.mem">
+   end="reg_diag_tx_seq_10gbe.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3240" />
+  <parameter name="baseAddress" value="0x32c0" />
  </connection>
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="reg_diag_bg_ddr.system" />
+   end="reg_diag_rx_seq_10gbe.system" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="reg_diag_bg_ddr.mem">
+   end="reg_diag_rx_seq_10gbe.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3380" />
+  <parameter name="baseAddress" value="0x3100" />
  </connection>
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="ram_diag_bg_ddr.system" />
+   end="reg_diag_tx_seq_1gbe.system" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="ram_diag_bg_ddr.mem">
+   end="reg_diag_tx_seq_1gbe.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xc000" />
+  <parameter name="baseAddress" value="0x000f0020" />
  </connection>
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="reg_diag_data_buffer_ddr.system" />
+   end="reg_diag_rx_seq_1gbe.system" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="reg_diag_data_buffer_ddr.mem">
+   end="reg_diag_rx_seq_1gbe.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3100" />
+  <parameter name="baseAddress" value="0x33c0" />
  </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_io_ddr_MB_I.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_0.clk_reset"
+   end="reg_io_ddr_MB_I.system_reset" />
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="ram_diag_data_buffer_ddr.system" />
+   end="reg_io_ddr_MB_I.system" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="ram_diag_data_buffer_ddr.mem">
+   end="reg_io_ddr_MB_I.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00080000" />
+  <parameter name="baseAddress" value="0x00040000" />
  </connection>
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_0.clk"
+   end="reg_io_ddr_MB_II.system" />
  <connection
    kind="reset"
    version="11.1"
    start="clk_0.clk_reset"
-   end="reg_diag_tx_seq_10gbe.system_reset" />
+   end="reg_io_ddr_MB_II.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="cpu_0.jtag_debug_module_reset"
-   end="reg_diag_tx_seq_10gbe.system_reset" />
+   end="reg_io_ddr_MB_II.system_reset" />
  <connection
-   kind="reset"
+   kind="avalon"
    version="11.1"
-   start="clk_0.clk_reset"
-   end="reg_diag_rx_seq_10gbe.system_reset" />
+   start="cpu_0.data_master"
+   end="reg_io_ddr_MB_II.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00080000" />
+ </connection>
  <connection
    kind="reset"
    version="11.1"
    start="cpu_0.jtag_debug_module_reset"
-   end="reg_diag_rx_seq_10gbe.system_reset" />
+   end="reg_diag_tx_seq_ddr_MB_I.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="clk_0.clk_reset"
-   end="reg_diag_tx_seq_1gbe.system_reset" />
+   end="reg_diag_tx_seq_ddr_MB_I.system_reset" />
  <connection
-   kind="reset"
+   kind="clock"
    version="11.1"
-   start="cpu_0.jtag_debug_module_reset"
-   end="reg_diag_tx_seq_1gbe.system_reset" />
+   start="clk_0.clk"
+   end="reg_diag_tx_seq_ddr_MB_I.system" />
  <connection
-   kind="reset"
+   kind="avalon"
    version="11.1"
-   start="clk_0.clk_reset"
-   end="reg_diag_rx_seq_1gbe.system_reset" />
+   start="cpu_0.data_master"
+   end="reg_diag_tx_seq_ddr_MB_I.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x000f0030" />
+ </connection>
  <connection
-   kind="reset"
+   kind="clock"
    version="11.1"
-   start="cpu_0.jtag_debug_module_reset"
-   end="reg_diag_rx_seq_1gbe.system_reset" />
+   start="clk_0.clk"
+   end="reg_diag_tx_seq_ddr_MB_II.system" />
  <connection
    kind="reset"
    version="11.1"
    start="clk_0.clk_reset"
-   end="reg_diag_tx_seq_ddr.system_reset" />
+   end="reg_diag_tx_seq_ddr_MB_II.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="cpu_0.jtag_debug_module_reset"
-   end="reg_diag_tx_seq_ddr.system_reset" />
+   end="reg_diag_tx_seq_ddr_MB_II.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_diag_tx_seq_ddr_MB_II.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x000f0040" />
+ </connection>
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_0.clk"
+   end="reg_diag_rx_seq_ddr_MB_I.system" />
  <connection
    kind="reset"
    version="11.1"
    start="clk_0.clk_reset"
-   end="reg_diag_rx_seq_ddr.system_reset" />
+   end="reg_diag_rx_seq_ddr_MB_I.system_reset" />
  <connection
    kind="reset"
    version="11.1"
    start="cpu_0.jtag_debug_module_reset"
-   end="reg_diag_rx_seq_ddr.system_reset" />
- <connection
-   kind="clock"
-   version="11.1"
-   start="clk_0.clk"
-   end="reg_diag_tx_seq_10gbe.system" />
+   end="reg_diag_rx_seq_ddr_MB_I.system_reset" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="reg_diag_tx_seq_10gbe.mem">
+   end="reg_diag_rx_seq_ddr_MB_I.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3280" />
+  <parameter name="baseAddress" value="0x33e0" />
  </connection>
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="reg_diag_rx_seq_10gbe.system" />
+   end="reg_diag_rx_seq_ddr_MB_II.system" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_0.clk_reset"
+   end="reg_diag_rx_seq_ddr_MB_II.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_diag_rx_seq_ddr_MB_II.system_reset" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="reg_diag_rx_seq_10gbe.mem">
+   end="reg_diag_rx_seq_ddr_MB_II.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3180" />
+  <parameter name="baseAddress" value="0x000f0000" />
  </connection>
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="reg_diag_tx_seq_1gbe.system" />
+   end="reg_diag_data_buffer_ddr_MB_I.system" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_0.clk_reset"
+   end="reg_diag_data_buffer_ddr_MB_I.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_diag_data_buffer_ddr_MB_I.system_reset" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="reg_diag_tx_seq_1gbe.mem">
+   end="reg_diag_data_buffer_ddr_MB_I.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x33f0" />
+  <parameter name="baseAddress" value="0x3180" />
  </connection>
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="reg_diag_rx_seq_1gbe.system" />
+   end="reg_diag_data_buffer_ddr_MB_II.system" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_0.clk_reset"
+   end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="reg_diag_rx_seq_1gbe.mem">
+   end="reg_diag_data_buffer_ddr_MB_II.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x33a0" />
+  <parameter name="baseAddress" value="0x3200" />
  </connection>
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="reg_diag_tx_seq_ddr.system" />
+   end="ram_diag_data_buffer_ddr_MB_I.system" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_0.clk_reset"
+   end="ram_diag_data_buffer_ddr_MB_I.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="ram_diag_data_buffer_ddr_MB_I.system_reset" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="reg_diag_tx_seq_ddr.mem">
+   end="ram_diag_data_buffer_ddr_MB_I.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xd000" />
+  <parameter name="baseAddress" value="0xa000" />
  </connection>
  <connection
    kind="clock"
    version="11.1"
    start="clk_0.clk"
-   end="reg_diag_rx_seq_ddr.system" />
+   end="ram_diag_data_buffer_ddr_MB_II.system" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_0.clk_reset"
+   end="ram_diag_data_buffer_ddr_MB_II.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="ram_diag_data_buffer_ddr_MB_II.system_reset" />
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.data_master"
-   end="reg_diag_rx_seq_ddr.mem">
+   end="ram_diag_data_buffer_ddr_MB_II.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x33c0" />
+  <parameter name="baseAddress" value="0xc000" />
  </connection>
 </system>
diff --git a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins_constraints.tcl b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins_constraints.tcl
index 97d70ca65f..a0d682642d 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins_constraints.tcl
+++ b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins_constraints.tcl
@@ -1,517 +1,1024 @@
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD 1.5V -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[7]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|pll1" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD 1.5V -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[5]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[6]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|ureset|phy_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[5]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[6]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[7]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to "u_revision|\\gen_ddr_dual_stream_MB_I:u_ddr_stream_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|pll1" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_II_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_II_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_II_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_II_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_II_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD 1.5V -to MB_II_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_II_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_II_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_II_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[0] -to MB_II_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[0] -to MB_II_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[0] -to MB_II_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[0] -to MB_II_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[0] -to MB_II_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[0] -to MB_II_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[0] -to MB_II_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[0] -to MB_II_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[1] -to MB_II_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[1] -to MB_II_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[1] -to MB_II_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[1] -to MB_II_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[1] -to MB_II_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[1] -to MB_II_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[1] -to MB_II_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[1] -to MB_II_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[2] -to MB_II_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[2] -to MB_II_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[2] -to MB_II_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[2] -to MB_II_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[2] -to MB_II_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[2] -to MB_II_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[2] -to MB_II_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[2] -to MB_II_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[3] -to MB_II_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[3] -to MB_II_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[3] -to MB_II_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[3] -to MB_II_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[3] -to MB_II_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[3] -to MB_II_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[3] -to MB_II_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[3] -to MB_II_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[4] -to MB_II_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[4] -to MB_II_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[4] -to MB_II_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[4] -to MB_II_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[4] -to MB_II_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[4] -to MB_II_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[4] -to MB_II_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[4] -to MB_II_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[5] -to MB_II_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[5] -to MB_II_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[5] -to MB_II_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[5] -to MB_II_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[5] -to MB_II_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[5] -to MB_II_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[5] -to MB_II_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[5] -to MB_II_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[6] -to MB_II_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[6] -to MB_II_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[6] -to MB_II_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[6] -to MB_II_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[6] -to MB_II_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[6] -to MB_II_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[6] -to MB_II_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[6] -to MB_II_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[7] -to MB_II_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[7] -to MB_II_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[7] -to MB_II_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[7] -to MB_II_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[7] -to MB_II_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[7] -to MB_II_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[7] -to MB_II_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[7] -to MB_II_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[0] -to MB_II_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[1] -to MB_II_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[2] -to MB_II_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[3] -to MB_II_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[4] -to MB_II_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[5] -to MB_II_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[6] -to MB_II_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_II_IO.dqs[7] -to MB_II_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_II_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[5]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|clk[6]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|ureset|phy_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[5]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[6]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[7]" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
+set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to "u_revision|\\gen_ddr_dual_stream_MB_II:u_ddr_stream_MB_II|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master:u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master|ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_inst|pll0|upll_memphy|auto_generated|pll1" -tag __ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0
 set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name UNIPHY_TEMP_VER_CODE 1207645311
+set_global_assignment -name UNIPHY_TEMP_VER_CODE 1484282465
\ No newline at end of file
-- 
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