diff --git a/libraries/io/eth/src/vhdl/eth_statistics.vhd b/libraries/io/eth/src/vhdl/eth_statistics.vhd
index 89ac030b35afd6b94737cdd9d8f50cfc4d156e37..51f22e7599a06695851e159e4e8f2bc0ed93a5bb 100644
--- a/libraries/io/eth/src/vhdl/eth_statistics.vhd
+++ b/libraries/io/eth/src/vhdl/eth_statistics.vhd
@@ -23,6 +23,18 @@
 -- . Daniel van der Schuur
 -- Purpose:
 -- . 1GbE wrapper for dp_statistics
+-- Remark:
+-- . Make sure that the Tx Eth also uses the transceiver sim model (and not
+--   the transceiver IP model).
+-- . The eth_clk for the Rx Eth is generated internally. The eth_clk that is
+--   used for the Tx Eth should have the same timing, so initialized at '0'
+--   and generated using eth_clk <= NOT eth_clk. If the sim link fails, then
+--   it could be due to delta cycle difference between the Rx eth_clk and
+--   the Tx eth_clk. Therefore it is better not to reassign the eth_clk like
+--   in e.g. eth_clk <= tx_eth_clk, because signal assignment '<=' adds a
+--   simulation delta cycle.
+-- . The eth_serial_in becomes active /= '0' when the Tx Eth is actually
+--   sending data, so this depends on the application or tb stimuli.
 
 LIBRARY IEEE, common_lib, work, technology_lib, dp_lib, tech_tse_lib;
 USE IEEE.STD_LOGIC_1164.ALL;