diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index a9a72853c46f8e63860ddc24b7a9e5236a342a5c..2958ab8001bc0c84c824da12b52acf598b0be7f1 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -121,6 +121,7 @@ synth_files =
src/vhdl/common_reinterleave.vhd
src/vhdl/common_paged_reg.vhd
src/vhdl/common_paged_ram_crw_crw.vhd
+ src/vhdl/common_paged_ram_cr_cw.vhd
src/vhdl/common_paged_ram_rw_rw.vhd
src/vhdl/common_paged_ram_r_w.vhd
src/vhdl/common_paged_ram_ww_rr.vhd
@@ -171,6 +172,8 @@ test_bench_files =
tb/vhdl/tb_common_multiplexer.vhd
tb/vhdl/tb_common_operation_tree.vhd
tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+ tb/vhdl/tb_common_paged_ram_cr_cw.vhd
+ tb/vhdl/tb_common_paged_ram_rw_rw.vhd
tb/vhdl/tb_common_paged_ram_ww_rr.vhd
tb/vhdl/tb_common_pulse_extend.vhd
tb/vhdl/tb_common_pulse_delay.vhd
@@ -220,6 +223,9 @@ regression_test_vhdl =
tb/vhdl/tb_common_fifo_rd.vhd
tb/vhdl/tb_common_mem_mux.vhd
tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+ tb/vhdl/tb_common_paged_ram_cr_cw.vhd
+ tb/vhdl/tb_common_paged_ram_rw_rw.vhd
+ #tb/vhdl/tb_common_paged_ram_ww_rr.vhd
tb/vhdl/tb_common_pulser_us_ms_s.vhd
tb/vhdl/tb_common_select_m_symbols.vhd
tb/vhdl/tb_common_shiftram.vhd
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6deefedd86c140de86d38e5014d945099e4078c9
--- /dev/null
+++ b/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
@@ -0,0 +1,317 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- D.F. Brouwer
+-- Purpose:
+-- Multi page memory with seperate clock and address per port with single wr
+-- and single rd
+-- Description:
+-- When *_next_page pulses then the next access will occur in the next page.
+-- Remarks:
+-- . There are three architecture variants (default use "use_adr"):
+-- . use_mux : Use multiplexer logic and one RAM per page
+-- . use_adr : Use MSbit address lines and one buf RAM for all pages
+-- . use_ofs : Use address offset adders and one buf RAM for all pages
+-- . The "use_mux" variant requires the multiplexer logic but can be more
+-- efficient regarding RAM usage than the "use_adr" variant.
+-- The "use_ofs" variant requires address adder logic, but is optimal
+-- regarding RAM usage in case the page size is not a power of 2, because the
+-- pages are then mapped at subsequent addresses in the buf RAM.
+-- . The "use_adr" variant is optimal for speed, so that is set as default.
+--
+-- . The crw_crw RAM covers all other variants, which were utilized by other
+-- common RAM variant files. However, because the crw_crw IP is no longer
+-- supported as it was previously used for previous FPGA technology identifiers
+-- (device types) by the Agilex 7 (agi027_xxxx), the individual IPs should be
+-- used. As a result, this file has been created. [1]
+-- Reference:
+-- [1] Based on the architecture of common_paged_ram_crw_crw.vhd.
+
+library IEEE, technology_lib;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library common_lib;
+use work.common_pkg.all;
+use work.common_mem_pkg.all;
+use technology_lib.technology_select_pkg.all;
+
+entity common_paged_ram_cr_cw is
+ generic (
+ g_technology : natural := c_tech_select_default;
+ g_str : string := "use_adr";
+ g_data_w : natural;
+ g_nof_pages : natural := 2; -- >= 2
+ g_page_sz : natural;
+ g_wr_start_page : natural := 0;
+ g_rd_start_page : natural := 0;
+ g_rd_latency : natural := 1
+ );
+ port (
+ -- Write port clock domain
+ wr_rst : in std_logic;
+ wr_clk : in std_logic;
+ wr_clken : in std_logic := '1';
+ wr_next_page : in std_logic;
+ wr_adr : in std_logic_vector(ceil_log2(g_page_sz) - 1 downto 0) := (others => '0');
+ wr_en : in std_logic := '0';
+ wr_dat : in std_logic_vector(g_data_w - 1 downto 0) := (others => '0');
+ -- Read port clock domain
+ rd_rst : in std_logic;
+ rd_clk : in std_logic;
+ rd_clken : in std_logic := '1';
+ rd_next_page : in std_logic;
+ rd_adr : in std_logic_vector(ceil_log2(g_page_sz) - 1 downto 0) := (others => '0');
+ rd_en : in std_logic := '1';
+ rd_dat : out std_logic_vector(g_data_w - 1 downto 0);
+ rd_val : out std_logic
+ );
+end common_paged_ram_cr_cw;
+
+architecture rtl of common_paged_ram_cr_cw is
+ type t_page_sel_arr is array (integer range <>) of natural range 0 to g_nof_pages - 1;
+
+ constant c_page_addr_w : natural := ceil_log2(g_page_sz);
+
+ -- g_str = "use_mux" :
+ constant c_page_ram : t_c_mem := (latency => g_rd_latency,
+ adr_w => c_page_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0');
+
+ type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
+
+ -- g_str = "use_adr" :
+ constant c_mem_nof_pages_w : natural := true_log2(g_nof_pages);
+ constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
+ constant c_mem_nof_words : natural := g_nof_pages * 2**c_page_addr_w; -- <= 2**c_mem_addr_w
+
+ constant c_mem_ram : t_c_mem := (latency => g_rd_latency,
+ adr_w => c_mem_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_mem_nof_words,
+ init_sl => '0');
+
+ -- g_str = "use_ofs" :
+ constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
+ constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
+
+ constant c_buf_ram : t_c_mem := (latency => g_rd_latency,
+ adr_w => c_buf_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_buf_nof_words,
+ init_sl => '0');
+
+ -- >>> Page control
+
+ -- g_str = "use_mux" and g_str = "use_adr" :
+ -- . use page_sel direct for wr_en, rd_en, and address
+ signal page_sel_wr : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_wr : natural;
+ signal page_sel_rd : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_rd : natural;
+
+ -- . use page_sel_dly to adjust for g_rd_latency of rd_dat and rd_val
+ signal page_sel_wr_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_wr_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal page_sel_rd_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_rd_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+
+ -- g_str = "use_ofs" :
+ signal page_ofs_wr : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_wr : natural;
+ signal page_ofs_rd : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_rd : natural;
+
+ -- >>> Access control
+
+ -- g_str = "use_mux" :
+ signal page_wr_en : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_dat : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_en : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_rd_dat : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_val : std_logic_vector(0 to g_nof_pages - 1);
+
+ -- g_str = "use_adr" :
+ signal mem_wr_adr : std_logic_vector(c_mem_addr_w - 1 downto 0);
+ signal mem_rd_adr : std_logic_vector(c_mem_addr_w - 1 downto 0);
+
+ -- g_str = "use_ofs" :
+ signal buf_wr_adr : std_logic_vector(c_buf_addr_w - 1 downto 0);
+ signal buf_rd_adr : std_logic_vector(c_buf_addr_w - 1 downto 0);
+begin
+ -- page select (for all) and page address offset (for use_ofs)
+ p_reg_wr : process (wr_rst, wr_clk)
+ begin
+ if wr_rst = '1' then
+ page_sel_wr <= g_wr_start_page;
+ page_sel_wr_dly <= (others => g_wr_start_page);
+ page_ofs_wr <= g_wr_start_page * g_page_sz;
+ elsif rising_edge(wr_clk) then
+ page_sel_wr <= nxt_page_sel_wr;
+ page_sel_wr_dly <= nxt_page_sel_wr_dly;
+ page_ofs_wr <= nxt_page_ofs_wr;
+ end if;
+ end process;
+
+ p_reg_rd : process (rd_rst, rd_clk)
+ begin
+ if rd_rst = '1' then
+ page_sel_rd <= g_rd_start_page;
+ page_sel_rd_dly <= (others => g_rd_start_page);
+ page_ofs_rd <= g_rd_start_page * g_page_sz;
+ elsif rising_edge(rd_clk) then
+ page_sel_rd <= nxt_page_sel_rd;
+ page_sel_rd_dly <= nxt_page_sel_rd_dly;
+ page_ofs_rd <= nxt_page_ofs_rd;
+ end if;
+ end process;
+
+ nxt_page_sel_wr_dly(0) <= page_sel_wr;
+ nxt_page_sel_wr_dly(1 to g_rd_latency - 1) <= page_sel_wr_dly(0 to g_rd_latency - 2);
+ nxt_page_sel_rd_dly(0) <= page_sel_rd;
+ nxt_page_sel_rd_dly(1 to g_rd_latency - 1) <= page_sel_rd_dly(0 to g_rd_latency - 2);
+
+ p_wr_next_page : process(wr_next_page, page_sel_wr, page_ofs_wr)
+ begin
+ nxt_page_sel_wr <= page_sel_wr;
+ nxt_page_ofs_wr <= page_ofs_wr;
+ if wr_next_page = '1' then
+ if page_sel_wr < g_nof_pages - 1 then
+ nxt_page_sel_wr <= page_sel_wr + 1;
+ nxt_page_ofs_wr <= page_ofs_wr + g_page_sz;
+ else
+ nxt_page_sel_wr <= 0;
+ nxt_page_ofs_wr <= 0;
+ end if;
+ end if;
+ end process;
+
+ p_rd_next_page : process(rd_next_page, page_sel_rd, page_ofs_rd)
+ begin
+ nxt_page_sel_rd <= page_sel_rd;
+ nxt_page_ofs_rd <= page_ofs_rd;
+ if rd_next_page = '1' then
+ if page_sel_rd < g_nof_pages - 1 then
+ nxt_page_sel_rd <= page_sel_rd + 1;
+ nxt_page_ofs_rd <= page_ofs_rd + g_page_sz;
+ else
+ nxt_page_sel_rd <= 0;
+ nxt_page_ofs_rd <= 0;
+ end if;
+ end if;
+ end process;
+
+ gen_mux : if g_str = "use_mux" generate
+ gen_pages : for I in 0 to g_nof_pages - 1 generate
+ u_ram : entity work.common_ram_cr_cw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ wr_clken => wr_clken,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ rd_clken => rd_clken,
+ wr_adr => wr_adr,
+ wr_en => page_wr_en(I),
+ wr_dat => wr_dat,
+ rd_adr => rd_adr,
+ rd_en => page_rd_en(I),
+ rd_dat => page_rd_dat(I),
+ rd_val => page_rd_val(I)
+ );
+ end generate;
+
+ p_mux : process(page_sel_wr, wr_en, page_sel_wr_dly, page_sel_rd,
+ rd_en, page_sel_rd_dly, page_rd_dat, page_rd_val)
+ begin
+ -- use page_sel direct for control
+ page_wr_en <= (others => '0');
+ page_rd_en <= (others => '0');
+ page_wr_en(page_sel_wr) <= wr_en;
+ page_rd_en(page_sel_rd) <= rd_en;
+
+ -- use page_sel_dly to account for the RAM read latency
+ rd_dat <= page_rd_dat(page_sel_rd_dly(g_rd_latency - 1));
+ rd_val <= page_rd_val(page_sel_rd_dly(g_rd_latency - 1));
+ end process;
+ end generate; -- gen_mux
+
+ gen_adr : if g_str = "use_adr" generate
+ u_mem : entity work.common_ram_cr_cw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mem_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ wr_clken => wr_clken,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ rd_clken => rd_clken,
+ wr_adr => mem_wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ rd_adr => mem_rd_adr,
+ rd_en => rd_en,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
+
+ mem_wr_adr <= TO_UVEC(page_sel_wr, c_mem_nof_pages_w) & wr_adr;
+ mem_rd_adr <= TO_UVEC(page_sel_rd, c_mem_nof_pages_w) & rd_adr;
+ end generate; -- gen_adr
+
+ gen_ofs : if g_str = "use_ofs" generate
+ u_buf : entity work.common_ram_cr_cw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ wr_clken => wr_clken,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ rd_clken => rd_clken,
+ wr_adr => buf_wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ rd_adr => buf_rd_adr,
+ rd_en => rd_en,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
+
+ buf_wr_adr <= INCR_UVEC(RESIZE_UVEC(wr_adr, c_buf_addr_w), page_ofs_wr);
+ buf_rd_adr <= INCR_UVEC(RESIZE_UVEC(rd_adr, c_buf_addr_w), page_ofs_rd);
+ end generate; -- gen_ofs
+
+end rtl;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index 4bc889b7fe958710a094a72551dec6fe230a54ea..c4012fc05482c9c5b6318d8437e6419679fd8891 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -1,25 +1,29 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2011
+-- Copyright 2011-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
-
--- Purpose: Multi page memory
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- -
+-- Changed by:
+-- D.F. Brouwer
+-- Purpose:
+-- Multi page memory
-- Description:
-- When next_page_* pulses then the next access will occur in the next page.
-- Remarks:
@@ -33,6 +37,9 @@
-- regarding RAM usage in case the page size is not a power of 2, because the
-- pages are then mapped at subsequent addresses in the buf RAM.
-- . The "use_adr" variant is optimal for speed, so that is set as default.
+-- Issues:
+-- Unavailable for Intel Agilex 7 (agi027_xxxx). See common_paged_ram_rw_rw
+-- for more context.
library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
index 254a426c535fa4f92dbcb191a1fb9a21c1e7ecb5..b2f05fc2700a05592eb6960dfaf96a641b20ce4c 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
@@ -21,9 +21,9 @@
-- Purpose: Multi page memory
-- Description:
--- When next_page_* pulses then the next access will occur in the next page.
+-- When *_next_page pulses then the next access will occur in the next page.
-- Remarks:
--- . See common_paged_ram_crw_crw for details.
+-- . See common_paged_ram_rw_rw for details.
library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
index 22dc9992af4ac0225fe7caa13e1f6f108312a1b3..4e4405a92ab196a72c53327c42d766a1e572ca85 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
@@ -1,48 +1,70 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2011
+-- Copyright 2011-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
-
--- Purpose: Multi page memory
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- -
+-- Changed by:
+-- D.F. Brouwer
+-- Purpose:
+-- Multi page memory
-- Description:
-- When next_page_* pulses then the next access will occur in the next page.
-- Remarks:
--- . See common_paged_ram_crw_crw for details.
+-- . There are three architecture variants (default use "use_adr"):
+-- . use_mux : Use multiplexer logic and one RAM per page
+-- . use_adr : Use MSbit address lines and one buf RAM for all pages
+-- . use_ofs : Use address offset adders and one buf RAM for all pages
+-- . The "use_mux" variant requires the multiplexer logic but can be more
+-- efficient regarding RAM usage than the "use_adr" variant.
+-- The "use_ofs" variant requires address adder logic, but is optimal
+-- regarding RAM usage in case the page size is not a power of 2, because the
+-- pages are then mapped at subsequent addresses in the buf RAM.
+-- . The "use_adr" variant is optimal for speed, so that is set as default.
+--
+-- . The crw_crw RAM covers all other variants, which were utilized by other
+-- common RAM variant files. However, because the crw_crw IP is no longer
+-- supported as it was previously used for previous FPGA technology identifiers
+-- (device types) by the Agilex 7 (agi027_xxxx), the rw_rw IP should be used.
+-- As a result, this file has been modified. [1]
+-- Reference:
+-- [1] Based on the architecture of common_paged_ram_crw_crw.vhd.
library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library common_lib;
use work.common_pkg.all;
+use work.common_mem_pkg.all;
use technology_lib.technology_select_pkg.all;
entity common_paged_ram_rw_rw is
generic (
- g_technology : natural := c_tech_select_default;
- g_str : string := "use_adr";
- g_data_w : natural;
- g_nof_pages : natural := 2; -- >= 2
- g_page_sz : natural;
- g_start_page_a : natural := 0;
- g_start_page_b : natural := 0;
- g_rd_latency : natural := 1;
- g_true_dual_port : boolean := true
+ g_technology : natural := c_tech_select_default;
+ g_str : string := "use_adr";
+ g_data_w : natural;
+ g_nof_pages : natural := 2; -- >= 2
+ g_page_sz : natural;
+ g_start_page_a : natural := 0;
+ g_start_page_b : natural := 0;
+ g_rd_latency : natural := 1;
+ g_true_dual_port : boolean := true
);
port (
rst : in std_logic;
@@ -65,40 +87,254 @@ entity common_paged_ram_rw_rw is
);
end common_paged_ram_rw_rw;
-architecture str of common_paged_ram_rw_rw is
+architecture rtl of common_paged_ram_rw_rw is
+ type t_page_sel_arr is array (integer range <>) of natural range 0 to g_nof_pages - 1;
+
+ constant c_page_addr_w : natural := ceil_log2(g_page_sz);
+
+ -- g_str = "use_mux" :
+ constant c_page_ram : t_c_mem := (latency => g_rd_latency,
+ adr_w => c_page_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0');
+
+ type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
+
+ -- g_str = "use_adr" :
+ constant c_mem_nof_pages_w : natural := true_log2(g_nof_pages);
+ constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
+ constant c_mem_nof_words : natural := g_nof_pages * 2**c_page_addr_w; -- <= 2**c_mem_addr_w
+
+ constant c_mem_ram : t_c_mem := (latency => g_rd_latency,
+ adr_w => c_mem_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_mem_nof_words,
+ init_sl => '0');
+
+ -- g_str = "use_ofs" :
+ constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
+ constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
+
+ constant c_buf_ram : t_c_mem := (latency => g_rd_latency,
+ adr_w => c_buf_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_buf_nof_words,
+ init_sl => '0');
+
+ -- >>> Page control
+
+ -- g_str = "use_mux" and g_str = "use_adr" :
+ -- . use page_sel direct for wr_en, rd_en, and address
+ signal page_sel_a : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_a : natural;
+ signal page_sel_b : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_b : natural;
+
+ -- . use page_sel_dly to adjust for g_rd_latency of rd_dat and rd_val
+ signal page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+
+ -- g_str = "use_ofs" :
+ signal page_ofs_a : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_a : natural;
+ signal page_ofs_b : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_b : natural;
+
+ -- >>> Access control
+
+ -- g_str = "use_mux" :
+ signal page_wr_en_a : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_dat_a : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_en_a : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_rd_dat_a : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_val_a : std_logic_vector(0 to g_nof_pages - 1);
+
+ signal page_wr_en_b : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_dat_b : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_en_b : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_rd_dat_b : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_val_b : std_logic_vector(0 to g_nof_pages - 1);
+
+ -- g_str = "use_adr" :
+ signal mem_adr_a : std_logic_vector(c_mem_addr_w - 1 downto 0);
+ signal mem_adr_b : std_logic_vector(c_mem_addr_w - 1 downto 0);
+
+ -- g_str = "use_ofs" :
+ signal buf_adr_a : std_logic_vector(c_buf_addr_w - 1 downto 0);
+ signal buf_adr_b : std_logic_vector(c_buf_addr_w - 1 downto 0);
begin
- u_crw_crw : entity work.common_paged_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_str => g_str,
- g_data_w => g_data_w,
- g_nof_pages => g_nof_pages,
- g_page_sz => g_page_sz,
- g_start_page_a => g_start_page_a,
- g_start_page_b => g_start_page_b,
- g_rd_latency => g_rd_latency,
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => clken,
- clken_b => clken,
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
-end str;
+ -- page select (for all) and page address offset (for use_ofs)
+ p_reg_a : process (rst, clk)
+ begin
+ if rst = '1' then
+ page_sel_a <= g_start_page_a;
+ page_sel_a_dly <= (others => g_start_page_a);
+ page_ofs_a <= g_start_page_a * g_page_sz;
+ elsif rising_edge(clk) then
+ page_sel_a <= nxt_page_sel_a;
+ page_sel_a_dly <= nxt_page_sel_a_dly;
+ page_ofs_a <= nxt_page_ofs_a;
+ end if;
+ end process;
+
+ p_reg_b : process (rst, clk)
+ begin
+ if rst = '1' then
+ page_sel_b <= g_start_page_b;
+ page_sel_b_dly <= (others => g_start_page_b);
+ page_ofs_b <= g_start_page_b * g_page_sz;
+ elsif rising_edge(clk) then
+ page_sel_b <= nxt_page_sel_b;
+ page_sel_b_dly <= nxt_page_sel_b_dly;
+ page_ofs_b <= nxt_page_ofs_b;
+ end if;
+ end process;
+
+ nxt_page_sel_a_dly(0) <= page_sel_a;
+ nxt_page_sel_a_dly(1 to g_rd_latency - 1) <= page_sel_a_dly(0 to g_rd_latency - 2);
+ nxt_page_sel_b_dly(0) <= page_sel_b;
+ nxt_page_sel_b_dly(1 to g_rd_latency - 1) <= page_sel_b_dly(0 to g_rd_latency - 2);
+
+ p_next_page_a : process(next_page_a, page_sel_a, page_ofs_a)
+ begin
+ nxt_page_sel_a <= page_sel_a;
+ nxt_page_ofs_a <= page_ofs_a;
+ if next_page_a = '1' then
+ if page_sel_a < g_nof_pages - 1 then
+ nxt_page_sel_a <= page_sel_a + 1;
+ nxt_page_ofs_a <= page_ofs_a + g_page_sz;
+ else
+ nxt_page_sel_a <= 0;
+ nxt_page_ofs_a <= 0;
+ end if;
+ end if;
+ end process;
+
+ p_next_page_b : process(next_page_b, page_sel_b, page_ofs_b)
+ begin
+ nxt_page_sel_b <= page_sel_b;
+ nxt_page_ofs_b <= page_ofs_b;
+ if next_page_b = '1' then
+ if page_sel_b < g_nof_pages - 1 then
+ nxt_page_sel_b <= page_sel_b + 1;
+ nxt_page_ofs_b <= page_ofs_b + g_page_sz;
+ else
+ nxt_page_sel_b <= 0;
+ nxt_page_ofs_b <= 0;
+ end if;
+ end if;
+ end process;
+
+ gen_mux : if g_str = "use_mux" generate
+ gen_pages : for I in 0 to g_nof_pages - 1 generate
+ u_ram : entity work.common_ram_rw_rw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ adr_a => adr_a,
+ wr_en_a => page_wr_en_a(I),
+ wr_dat_a => wr_dat_a,
+ rd_en_a => page_rd_en_a(I),
+ rd_dat_a => page_rd_dat_a(I),
+ rd_val_a => page_rd_val_a(I),
+ adr_b => adr_b,
+ wr_en_b => page_wr_en_b(I),
+ wr_dat_b => wr_dat_b,
+ rd_en_b => page_rd_en_b(I),
+ rd_dat_b => page_rd_dat_b(I),
+ rd_val_b => page_rd_val_b(I)
+ );
+ end generate;
+
+ p_mux : process(page_sel_a, wr_en_a, rd_en_a, page_sel_a_dly, page_rd_dat_a, page_rd_val_a,
+ page_sel_b, wr_en_b, rd_en_b, page_sel_b_dly, page_rd_dat_b, page_rd_val_b)
+ begin
+ -- use page_sel direct for control
+ page_wr_en_a <= (others => '0');
+ page_wr_en_b <= (others => '0');
+ page_rd_en_a <= (others => '0');
+ page_rd_en_b <= (others => '0');
+ page_wr_en_a(page_sel_a) <= wr_en_a;
+ page_wr_en_b(page_sel_b) <= wr_en_b;
+ page_rd_en_a(page_sel_a) <= rd_en_a;
+ page_rd_en_b(page_sel_b) <= rd_en_b;
+
+ -- use page_sel_dly to account for the RAM read latency
+ rd_dat_a <= page_rd_dat_a(page_sel_a_dly(g_rd_latency - 1));
+ rd_dat_b <= page_rd_dat_b(page_sel_b_dly(g_rd_latency - 1));
+ rd_val_a <= page_rd_val_a(page_sel_a_dly(g_rd_latency - 1));
+ rd_val_b <= page_rd_val_b(page_sel_b_dly(g_rd_latency - 1));
+ end process;
+ end generate; -- gen_mux
+
+ gen_adr : if g_str = "use_adr" generate
+ u_mem : entity work.common_ram_rw_rw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mem_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ adr_a => mem_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => mem_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
+
+ mem_adr_a <= TO_UVEC(page_sel_a, c_mem_nof_pages_w) & adr_a;
+ mem_adr_b <= TO_UVEC(page_sel_b, c_mem_nof_pages_w) & adr_b;
+ end generate; -- gen_adr
+
+ gen_ofs : if g_str = "use_ofs" generate
+ u_buf : entity work.common_ram_rw_rw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ adr_a => buf_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => buf_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
+
+ buf_adr_a <= INCR_UVEC(RESIZE_UVEC(adr_a, c_buf_addr_w), page_ofs_a);
+ buf_adr_b <= INCR_UVEC(RESIZE_UVEC(adr_b, c_buf_addr_w), page_ofs_b);
+ end generate; -- gen_ofs
+
+end rtl;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
index 748ab33ce8c261631aac84288dcbb92af25d7976..6977e8583cdb92b1f6baa3023d63706955e227fe 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
@@ -1,26 +1,43 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- -
+-- Changed by:
+-- D.F. Brouwer
+-- Description:
+-- Dual clock domain
+-- Use port a only for write in write clock domain
+-- Use port b only for read in read clock domain
+-- Remarks:
+-- The crw_crw RAM covers all other variants, which were utilized by other
+-- common RAM variant files. However, because the crw_crw IP is no longer
+-- supported as it was previously used for previous FPGA technology identifiers
+-- (device types) by the Agilex 7 (agi027_xxxx), the individual IPs should be
+-- used. As a result, this file has been modified. [1]
+-- Reference:
+-- [1] Based on the architecture of common_ram_crw_crw.vhd.
-library IEEE, technology_lib;
+library IEEE, technology_lib, tech_memory_lib;
use IEEE.std_logic_1164.all;
+use work.common_pkg.all;
use work.common_mem_pkg.all;
use technology_lib.technology_select_pkg.all;
@@ -50,35 +67,72 @@ entity common_ram_cr_cw is
end common_ram_cr_cw;
architecture str of common_ram_cr_cw is
+ constant c_rd_latency : natural := sel_a_b(g_ram.latency < 2, g_ram.latency, 2); -- handle read latency 1 or 2 in RAM
+ constant c_pipeline : natural := sel_a_b(g_ram.latency > c_rd_latency, g_ram.latency - c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline
+
+ -- Intermediate signal for extra pipelining
+ signal ram_rd_dat : std_logic_vector(rd_dat'range);
+
+ -- Map sl to single bit slv for rd_val pipelining
+ signal ram_rd_en : std_logic_vector(0 downto 0);
+ signal ram_rd_val : std_logic_vector(0 downto 0);
begin
- -- Dual clock domain
- -- Use port a only for write in write clock domain
- -- Use port b only for read in read clock domain
+ assert g_ram.latency >= 1
+ report "common_ram_cr_cw : only support read latency >= 1"
+ severity FAILURE;
- u_cr_cw : entity work.common_ram_crw_crw
+ -- memory access
+ u_cr_cw : entity tech_memory_lib.tech_memory_ram_cr_cw
generic map (
g_technology => g_technology,
- g_ram => g_ram,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
g_init_file => g_init_file
)
+ port map
+ (
+ wrclock => wr_clk,
+ wrclocken => wr_clken,
+ wren => wr_en,
+ wraddress => wr_adr,
+ data => wr_dat,
+ rdclock => rd_clk,
+ rdclocken => rd_clken,
+ rdaddress => rd_adr,
+ q => ram_rd_dat
+ );
+
+ -- read output
+ u_pipe : entity work.common_pipeline
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => rd_clk,
+ clken => rd_clken,
+ in_dat => ram_rd_dat,
+ out_dat => rd_dat
+ );
+
+ -- rd_val control
+ ram_rd_en(0) <= rd_en;
+
+ rd_val <= ram_rd_val(0);
+
+ u_rd_val : entity work.common_pipeline
+ generic map (
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
port map (
- rst_a => wr_rst,
- rst_b => rd_rst,
- clk_a => wr_clk,
- clk_b => rd_clk,
- clken_a => wr_clken,
- clken_b => rd_clken,
- wr_en_a => wr_en,
- wr_en_b => '0',
- wr_dat_a => wr_dat,
- wr_dat_b => (others => '0'),
- adr_a => wr_adr,
- adr_b => rd_adr,
- rd_en_a => '0',
- rd_en_b => rd_en,
- rd_dat_a => OPEN,
- rd_dat_b => rd_dat,
- rd_val_a => OPEN,
- rd_val_b => rd_val
+ clk => rd_clk,
+ clken => rd_clken,
+ in_dat => ram_rd_en,
+ out_dat => ram_rd_val
);
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
index b2a595644f4227a84650c31fb80f51690131f4b9..d314cdc9f5163c4e2a4bb0a28746479bedf119a1 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
@@ -1,26 +1,39 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Description:
+-- Dual clock domain with different aspect ratio data widhts
+-- Use port a only for write in write clock domain
+-- Use port b only for read in read clock domain
+-- Remark:
+-- Because the Agilex 7 (agi027_xxxx) does not support the crwk_crw IP,
+-- and unfortunately, the rwk_rw IP isn't supported either, the crk_cw IP
+-- has been created, resulting in modifications to this file.[1]
+-- Reference:
+-- [1] Based on the structure of common_crw_crw_ratio.vhd.
-library IEEE, technology_lib;
+library IEEE, technology_lib, tech_memory_lib;
use IEEE.std_logic_1164.all;
+use work.common_pkg.all;
use work.common_mem_pkg.all;
use technology_lib.technology_select_pkg.all;
@@ -51,36 +64,81 @@ entity common_ram_cr_cw_ratio is
end common_ram_cr_cw_ratio;
architecture str of common_ram_cr_cw_ratio is
+ constant c_ram : t_c_mem := g_ram_wr; -- use shared parameters from port wr (a) parameter
+
+ constant c_rd_latency : natural := sel_a_b(c_ram.latency < 2, c_ram.latency, 2); -- handle read latency 1 or 2 in RAM
+ constant c_pipeline : natural := sel_a_b(c_ram.latency > c_rd_latency, c_ram.latency - c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline
+
+ -- Intermediate signal for extra pipelining
+ signal ram_rd_dat : std_logic_vector(rd_dat'range);
+
+ -- Map sl to single bit slv for rd_val pipelining
+ signal ram_rd_en : std_logic_vector(0 downto 0);
+ signal ram_rd_val : std_logic_vector(0 downto 0);
+
begin
- -- Dual clock domain
- -- Use port a only for write in write clock domain
- -- Use port b only for read in read clock domain
+ assert c_ram.latency >= 1
+ report "common_ram_cr_cw_ratio : only support read latency >= 1"
+ severity FAILURE;
+
+ assert g_ram_wr.latency = g_ram_rd.latency
+ report "common_ram_cr_cw_ratio : only support same read latency for both ports"
+ severity FAILURE;
+
+ -- memory access
+ u_ramk : entity tech_memory_lib.tech_memory_ram_crk_cw
+ generic map (
+ g_technology => g_technology,
+ g_wr_adr_w => g_ram_wr.adr_w,
+ g_rd_adr_w => g_ram_rd.adr_w,
+ g_wr_dat_w => g_ram_wr.dat_w,
+ g_rd_dat_w => g_ram_rd.dat_w,
+ g_wr_nof_words => g_ram_wr.nof_dat,
+ g_rd_nof_words => g_ram_rd.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map (
+ wrclock => wr_clk,
+ rdclock => rd_clk,
+ wrclocken => wr_clken,
+ rdclocken => rd_clken,
+ wren => wr_en,
+ data => wr_dat,
+ wraddress => wr_adr,
+ rdaddress => rd_adr,
+ q => ram_rd_dat
+ );
+
+ -- read output
+ u_pipe : entity work.common_pipeline
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram_rd.dat_w,
+ g_out_dat_w => g_ram_rd.dat_w
+ )
+ port map (
+ clk => rd_clk,
+ clken => rd_clken,
+ in_dat => ram_rd_dat,
+ out_dat => rd_dat
+ );
+
+ -- rd_val control
+ ram_rd_en(0) <= rd_en;
+
+ rd_val <= ram_rd_val(0);
- u_cr_cw : entity work.common_ram_crw_crw_ratio
+ u_rd_val : entity work.common_pipeline
generic map (
- g_technology => g_technology,
- g_ram_a => g_ram_wr,
- g_ram_b => g_ram_rd,
- g_init_file => g_init_file
+ g_pipeline => c_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
)
port map (
- rst_a => wr_rst,
- rst_b => rd_rst,
- clk_a => wr_clk,
- clk_b => rd_clk,
- clken_a => wr_clken,
- clken_b => rd_clken,
- wr_en_a => wr_en,
- wr_en_b => '0',
- wr_dat_a => wr_dat,
- wr_dat_b => (others => '0'),
- adr_a => wr_adr,
- adr_b => rd_adr,
- rd_en_a => '0',
- rd_en_b => rd_en,
- rd_dat_a => OPEN,
- rd_dat_b => rd_dat,
- rd_val_a => OPEN,
- rd_val_b => rd_val
+ clk => rd_clk,
+ clken => rd_clken,
+ in_dat => ram_rd_en,
+ out_dat => ram_rd_val
);
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
index c49f6b39570dc76f0c7b6fd735cd7c36971c46a1..9460631e1d382162793e67faeca1b60b9220582c 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
@@ -1,23 +1,30 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- -
+-- Changed by:
+-- D.F. Brouwer
+-- Issues:
+-- Unavailable for Intel Agilex 7 (agi027_xxxx). See common_ram_rw_rw
+-- for more context.
library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
index acdfa0d2196449f5df82793998de66d4e9972299..b602cf707d949f511a55c5950f308644a978cce9 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
@@ -1,23 +1,30 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- -
+-- Changed by:
+-- D.F. Brouwer
+-- Issues:
+-- Unavailable for Intel Agilex 7 (agi027_xxxx). See common_ram_rw_rw
+-- for more context.
library IEEE, technology_lib, tech_memory_lib;
use IEEE.std_logic_1164.all;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
index c9930f48926ce557ab8fe1ff32714b7b1c50df1a..c85bd11f2ed1e35a5a55991bfe36c4449b1874aa 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
@@ -1,23 +1,30 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- -
+-- Changed by:
+-- D.F. Brouwer
+-- Issues:
+-- Unavailable for Intel Agilex 7 (agi027_xxxx). See common_ram_cr_cw_ratio
+-- for more context.
library IEEE, technology_lib, tech_memory_lib;
use IEEE.std_logic_1164.all;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
index 021d7638b8b23a59533f0351265c05eef94eb68a..5fe4fde7782fbdff680103be8f74b3894325b558 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
@@ -1,23 +1,30 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- -
+-- Changed by:
+-- D.F. Brouwer
+-- Issues:
+-- Unavailable for Intel Agilex 7 (agi027_xxxx). See common_ram_rw_rw
+-- for more context.
library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
diff --git a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
index 5c333e54056b31e78ac718e495a8ddde09ab4440..4a2740b82e22215a7acbc6da526b0df18f0b119a 100644
--- a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
@@ -1,34 +1,49 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- -
+-- Changed by:
+-- D.F. Brouwer
+-- Description:
+-- This a true dual port ram that only uses one clock domain
+-- Remarks:
+-- The crw_crw RAM covers all other variants, which were utilized by other
+-- common RAM variant files. However, because the crw_crw IP is no longer
+-- supported as it was previously used for previous FPGA technology identifiers
+-- (device types) by the Agilex 7 (agi027_xxxx), the rw_rw IP should be used.
+-- As a result, this file has been modified. [1]
+-- Reference:
+-- [1] Based on the architecture of common_ram_crw_crw.vhd.
-library IEEE, technology_lib;
+library IEEE, technology_lib, tech_memory_lib;
use IEEE.std_logic_1164.all;
+use work.common_pkg.all;
use work.common_mem_pkg.all;
use technology_lib.technology_select_pkg.all;
entity common_ram_rw_rw is
generic (
- g_technology : natural := c_tech_select_default;
- g_ram : t_c_mem := c_mem_ram;
- g_init_file : string := "UNUSED";
+ g_technology : natural := c_tech_select_default;
+ g_ram : t_c_mem := c_mem_ram;
+ g_init_file : string := "UNUSED";
g_true_dual_port : boolean := true
);
port (
@@ -51,34 +66,127 @@ entity common_ram_rw_rw is
end common_ram_rw_rw;
architecture str of common_ram_rw_rw is
+ constant c_rd_latency : natural := sel_a_b(g_ram.latency < 2, g_ram.latency, 2); -- handle read latency 1 or 2 in RAM
+ constant c_pipeline : natural := sel_a_b(g_ram.latency > c_rd_latency, g_ram.latency - c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline
+
+ -- Intermediate signal for extra pipelining
+ signal ram_rd_dat_a : std_logic_vector(rd_dat_a'range);
+ signal ram_rd_dat_b : std_logic_vector(rd_dat_b'range);
+
+ -- Map sl to single bit slv for rd_val pipelining
+ signal ram_rd_en_a : std_logic_vector(0 downto 0);
+ signal ram_rd_en_b : std_logic_vector(0 downto 0);
+ signal ram_rd_val_a : std_logic_vector(0 downto 0);
+ signal ram_rd_val_b : std_logic_vector(0 downto 0);
begin
- -- Use only one clock domain
+ assert g_ram.latency >= 1
+ report "common_ram_rw_rw : only support read latency >= 1"
+ severity FAILURE;
+
+ -- memory access
+ gen_true_dual_port : if g_true_dual_port = true generate
+ u_ram : entity tech_memory_lib.tech_memory_ram_rw_rw
+ generic map (
+ g_technology => g_technology,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map (
+ clock => clk,
+ enable => clken,
+ wren_a => wr_en_a,
+ wren_b => wr_en_b,
+ data_a => wr_dat_a,
+ data_b => wr_dat_b,
+ address_a => adr_a,
+ address_b => adr_b,
+ q_a => ram_rd_dat_a,
+ q_b => ram_rd_dat_b
+ );
+ end generate;
+
+ gen_simple_dual_port : if g_true_dual_port = false generate
+ u_ram : entity tech_memory_lib.tech_memory_ram_r_w
+ generic map (
+ g_technology => g_technology,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map
+ (
+ clock => clk,
+ enable => clken,
+ wren => wr_en_a,
+ wraddress => adr_a,
+ data => wr_dat_a,
+ rdaddress => adr_b,
+ q => ram_rd_dat_b
+ );
+ end generate;
+
+ -- read output
+ u_pipe_a : entity work.common_pipeline
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => ram_rd_dat_a,
+ out_dat => rd_dat_a
+ );
+
+ u_pipe_b : entity work.common_pipeline
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => ram_rd_dat_b,
+ out_dat => rd_dat_b
+ );
+
+ -- rd_val control
+ ram_rd_en_a(0) <= rd_en_a;
+ ram_rd_en_b(0) <= rd_en_b;
+
+ rd_val_a <= ram_rd_val_a(0);
+ rd_val_b <= ram_rd_val_b(0);
+
+ u_rd_val_a : entity work.common_pipeline
+ generic map (
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => ram_rd_en_a,
+ out_dat => ram_rd_val_a
+ );
- u_crw_crw : entity work.common_ram_crw_crw
+ u_rd_val_b : entity work.common_pipeline
generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file,
- g_true_dual_port => g_true_dual_port
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
)
port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => clken,
- clken_b => clken,
- wr_en_a => wr_en_a,
- wr_en_b => wr_en_b,
- wr_dat_a => wr_dat_a,
- wr_dat_b => wr_dat_b,
- adr_a => adr_a,
- adr_b => adr_b,
- rd_en_a => rd_en_a,
- rd_en_b => rd_en_b,
- rd_dat_a => rd_dat_a,
- rd_dat_b => rd_dat_b,
- rd_val_a => rd_val_a,
- rd_val_b => rd_val_b
+ clk => clk,
+ clken => clken,
+ in_dat => ram_rd_en_b,
+ out_dat => ram_rd_val_b
);
end str;
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..05e526c6838c9c5742008eeaac54cc7af1a214df
--- /dev/null
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
@@ -0,0 +1,231 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- D.F. Brouwer
+-- Purpose:
+-- Test bench for common_paged_ram_cr_cw
+-- Reference:
+-- Based on tb_common_paged_ram_crw_crw.vhd
+-- Description:
+-- Features:
+-- . Use c_gap_sz = 0 to try writing and reading multiple page without idle
+-- cycles
+-- . Most applications use c_nof_pages = 2, but use > 2 is supported too.
+-- Usage:
+-- > as 10
+-- > run -all
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.common_pkg.all;
+use work.tb_common_pkg.all;
+
+entity tb_common_paged_ram_cr_cw is
+end tb_common_paged_ram_cr_cw;
+
+architecture tb of tb_common_paged_ram_cr_cw is
+ constant clk_period : time := 10 ns;
+
+ constant c_data_w : natural := 8;
+ constant c_nof_pages : natural := 2; -- >= 2
+ constant c_page_sz : natural := 8;
+ constant c_wr_start_page : natural := 0;
+ constant c_rd_start_page : natural := 1;
+ constant c_gap_sz : natural := 0; -- >= 0
+ constant c_rl : natural := 1;
+
+ signal rst : std_logic;
+ signal clk : std_logic := '1';
+ signal tb_end : std_logic := '0';
+
+ -- DUT
+ signal next_page : std_logic;
+
+ signal wr_next_page : std_logic;
+ signal wr_adr : std_logic_vector(ceil_log2(c_page_sz) - 1 downto 0) := (others => '0');
+ signal wr_en : std_logic;
+ signal wr_dat : std_logic_vector(c_data_w - 1 downto 0) := (others => '0');
+
+ signal rd_next_page : std_logic;
+ signal rd_adr : std_logic_vector(ceil_log2(c_page_sz) - 1 downto 0) := (others => '0');
+ signal rd_en : std_logic := '0';
+
+ signal mux_rd_dat : std_logic_vector(c_data_w - 1 downto 0);
+ signal mux_rd_val : std_logic;
+
+ signal adr_rd_dat : std_logic_vector(c_data_w - 1 downto 0);
+ signal adr_rd_val : std_logic;
+
+ signal ofs_rd_dat : std_logic_vector(c_data_w - 1 downto 0);
+ signal ofs_rd_val : std_logic;
+
+ -- Verify
+ signal verify_en : std_logic;
+ signal ready : std_logic := '1';
+
+ signal prev_mux_rd_dat : std_logic_vector(c_data_w - 1 downto 0);
+ signal prev_adr_rd_dat : std_logic_vector(c_data_w - 1 downto 0);
+ signal prev_ofs_rd_dat : std_logic_vector(c_data_w - 1 downto 0);
+begin
+ clk <= not clk and not tb_end after clk_period / 2;
+ rst <= '1', '0' after clk_period * 7;
+
+ verify_en <= '0', '1' after clk_period * (15 + (c_nof_pages - 1) * c_page_sz);
+
+ -- Apply stimuli via port 'a', do write 'a' and read 'b', and derive the 'b' stimuli from the 'a' stimuli with 1 clock cycle latency
+ wr_next_page <= next_page;
+ rd_next_page <= next_page when rising_edge(clk);
+
+ wr_dat <= INCR_UVEC( wr_dat, 1) when rising_edge(clk) and wr_en = '1';
+ wr_adr <= INCR_UVEC( wr_adr, 1) when rising_edge(clk) and wr_en = '1';
+ rd_adr <= wr_adr when rising_edge(clk);
+ rd_en <= wr_en when rising_edge(clk);
+
+ p_stimuli : process
+ begin
+ next_page <= '0';
+ wr_en <= '0';
+ proc_common_wait_until_low(clk, rst);
+ proc_common_wait_some_cycles(clk, 3);
+
+ -- Access the pages several times
+ for I in 0 to c_nof_pages * 3 loop
+ wr_en <= '1';
+ proc_common_wait_some_cycles(clk, c_page_sz - 1);
+ next_page <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ next_page <= '0';
+ wr_en <= '0';
+ proc_common_wait_some_cycles(clk, c_gap_sz); -- optinal gap between the pages
+ end loop;
+
+ wr_en <= '0';
+ proc_common_wait_some_cycles(clk, c_page_sz);
+ tb_end <= '1';
+ wait;
+ end process;
+
+ u_dut_mux : entity work.common_paged_ram_cr_cw
+ generic map (
+ g_str => "use_mux",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_wr_start_page => c_wr_start_page,
+ g_rd_start_page => c_rd_start_page
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => rst,
+ wr_clk => clk,
+ wr_clken => '1',
+ wr_next_page => wr_next_page,
+ wr_adr => wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ -- Read port clock domain
+ rd_rst => rst,
+ rd_clk => clk,
+ rd_clken => '1',
+ rd_next_page => rd_next_page,
+ rd_adr => rd_adr,
+ rd_en => rd_en,
+ rd_dat => mux_rd_dat,
+ rd_val => mux_rd_val
+ );
+
+ u_dut_adr : entity work.common_paged_ram_cr_cw
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_wr_start_page => c_wr_start_page,
+ g_rd_start_page => c_rd_start_page
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => rst,
+ wr_clk => clk,
+ wr_clken => '1',
+ wr_next_page => wr_next_page,
+ wr_adr => wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ -- Read port clock domain
+ rd_rst => rst,
+ rd_clk => clk,
+ rd_clken => '1',
+ rd_next_page => rd_next_page,
+ rd_adr => rd_adr,
+ rd_en => rd_en,
+ rd_dat => adr_rd_dat,
+ rd_val => adr_rd_val
+ );
+
+ u_dut_ofs : entity work.common_paged_ram_cr_cw
+ generic map (
+ g_str => "use_ofs",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_wr_start_page => c_wr_start_page,
+ g_rd_start_page => c_rd_start_page
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => rst,
+ wr_clk => clk,
+ wr_clken => '1',
+ wr_next_page => wr_next_page,
+ wr_adr => wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ -- Read port clock domain
+ rd_rst => rst,
+ rd_clk => clk,
+ rd_clken => '1',
+ rd_next_page => rd_next_page,
+ rd_adr => rd_adr,
+ rd_en => rd_en,
+ rd_dat => ofs_rd_dat,
+ rd_val => ofs_rd_val
+ );
+
+ -- Verify that the read data is incrementing data
+ proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val, mux_rd_dat, prev_mux_rd_dat);
+ proc_common_verify_data(c_rl, clk, verify_en, ready, adr_rd_val, adr_rd_dat, prev_adr_rd_dat);
+ proc_common_verify_data(c_rl, clk, verify_en, ready, ofs_rd_val, ofs_rd_dat, prev_ofs_rd_dat);
+
+ -- Verify that the read data is the same for all three DUT variants
+ p_verify_equal : process(clk)
+ begin
+ if rising_edge(clk) then
+ if unsigned(mux_rd_dat) /= unsigned(adr_rd_dat) or unsigned(mux_rd_dat) /= unsigned(ofs_rd_dat) then
+ report "DUT : read data differs between two implementations" severity ERROR;
+ end if;
+ if mux_rd_val /= adr_rd_val or mux_rd_val /= ofs_rd_val then
+ report "DUT : read valid differs between two implementations" severity ERROR;
+ end if;
+ end if;
+ end process;
+end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2de05fffb45fc79828ab8ff58ced5d5406787234
--- /dev/null
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
@@ -0,0 +1,231 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- D.F. Brouwer
+-- Purpose:
+-- Test bench for common_paged_ram_rw_rw
+-- Reference:
+-- Based on tb_common_paged_ram_crw_crw.vhd
+-- Description:
+-- Features:
+-- . Use c_gap_sz = 0 to try writing and reading multiple page without idle
+-- cycles
+-- . Most applications use c_nof_pages = 2, but use > 2 is supported too.
+-- Usage:
+-- > as 10
+-- > run -all
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.common_pkg.all;
+use work.tb_common_pkg.all;
+
+entity tb_common_paged_ram_rw_rw is
+end tb_common_paged_ram_rw_rw;
+
+architecture tb of tb_common_paged_ram_rw_rw is
+ constant clk_period : time := 10 ns;
+
+ constant c_data_w : natural := 8;
+ constant c_nof_pages : natural := 2; -- >= 2
+ constant c_page_sz : natural := 8;
+ constant c_start_page_a : natural := 0;
+ constant c_start_page_b : natural := 1;
+ constant c_gap_sz : natural := 0; -- >= 0
+ constant c_rl : natural := 1;
+
+ signal rst : std_logic;
+ signal clk : std_logic := '1';
+ signal tb_end : std_logic := '0';
+
+ -- DUT
+ signal next_page : std_logic;
+
+ signal next_page_a : std_logic;
+ signal adr_a : std_logic_vector(ceil_log2(c_page_sz) - 1 downto 0) := (others => '0');
+ signal wr_en_a : std_logic;
+ signal wr_dat_a : std_logic_vector(c_data_w - 1 downto 0) := (others => '0');
+
+ signal next_page_b : std_logic;
+ signal adr_b : std_logic_vector(ceil_log2(c_page_sz) - 1 downto 0) := (others => '0');
+ signal rd_en_b : std_logic := '0';
+
+ signal mux_rd_dat_b : std_logic_vector(c_data_w - 1 downto 0);
+ signal mux_rd_val_b : std_logic;
+
+ signal adr_rd_dat_b : std_logic_vector(c_data_w - 1 downto 0);
+ signal adr_rd_val_b : std_logic;
+
+ signal ofs_rd_dat_b : std_logic_vector(c_data_w - 1 downto 0);
+ signal ofs_rd_val_b : std_logic;
+
+ -- Verify
+ signal verify_en : std_logic;
+ signal ready : std_logic := '1';
+
+ signal prev_mux_rd_dat_b : std_logic_vector(c_data_w - 1 downto 0);
+ signal prev_adr_rd_dat_b : std_logic_vector(c_data_w - 1 downto 0);
+ signal prev_ofs_rd_dat_b : std_logic_vector(c_data_w - 1 downto 0);
+begin
+ clk <= not clk and not tb_end after clk_period / 2;
+ rst <= '1', '0' after clk_period * 7;
+
+ verify_en <= '0', '1' after clk_period * (15 + (c_nof_pages - 1) * c_page_sz);
+
+ -- Apply stimuli via port 'a', do write 'a' and read 'b', and derive the 'b' stimuli from the 'a' stimuli with 1 clock cycle latency
+ next_page_a <= next_page;
+ next_page_b <= next_page when rising_edge(clk);
+
+ wr_dat_a <= INCR_UVEC(wr_dat_a, 1) when rising_edge(clk) and wr_en_a = '1';
+ adr_a <= INCR_UVEC( adr_a, 1) when rising_edge(clk) and wr_en_a = '1';
+ adr_b <= adr_a when rising_edge(clk);
+ rd_en_b <= wr_en_a when rising_edge(clk);
+
+ p_stimuli : process
+ begin
+ next_page <= '0';
+ wr_en_a <= '0';
+ proc_common_wait_until_low(clk, rst);
+ proc_common_wait_some_cycles(clk, 3);
+
+ -- Access the pages several times
+ for I in 0 to c_nof_pages * 3 loop
+ wr_en_a <= '1';
+ proc_common_wait_some_cycles(clk, c_page_sz - 1);
+ next_page <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ next_page <= '0';
+ wr_en_a <= '0';
+ proc_common_wait_some_cycles(clk, c_gap_sz); -- optinal gap between the pages
+ end loop;
+
+ wr_en_a <= '0';
+ proc_common_wait_some_cycles(clk, c_page_sz);
+ tb_end <= '1';
+ wait;
+ end process;
+
+ u_dut_mux : entity work.common_paged_ram_rw_rw
+ generic map (
+ g_str => "use_mux",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => mux_rd_dat_b,
+ rd_val_b => mux_rd_val_b
+ );
+
+ u_dut_adr : entity work.common_paged_ram_rw_rw
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => adr_rd_dat_b,
+ rd_val_b => adr_rd_val_b
+ );
+
+ u_dut_ofs : entity work.common_paged_ram_rw_rw
+ generic map (
+ g_str => "use_ofs",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => ofs_rd_dat_b,
+ rd_val_b => ofs_rd_val_b
+ );
+
+ -- Verify that the read data is incrementing data
+ proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val_b, mux_rd_dat_b, prev_mux_rd_dat_b);
+ proc_common_verify_data(c_rl, clk, verify_en, ready, adr_rd_val_b, adr_rd_dat_b, prev_adr_rd_dat_b);
+ proc_common_verify_data(c_rl, clk, verify_en, ready, ofs_rd_val_b, ofs_rd_dat_b, prev_ofs_rd_dat_b);
+
+ -- Verify that the read data is the same for all three DUT variants
+ p_verify_equal : process(clk)
+ begin
+ if rising_edge(clk) then
+ if unsigned(mux_rd_dat_b) /= unsigned(adr_rd_dat_b) or unsigned(mux_rd_dat_b) /= unsigned(ofs_rd_dat_b) then
+ report "DUT : read data differs between two implementations" severity ERROR;
+ end if;
+ if mux_rd_val_b /= adr_rd_val_b or mux_rd_val_b /= ofs_rd_val_b then
+ report "DUT : read valid differs between two implementations" severity ERROR;
+ end if;
+ end if;
+ end process;
+end tb;
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/README.txt b/libraries/technology/ip_agi027_xxxx/fifo/README.txt
index e88d724fd4de6ef97cf899387f009ec9c56be7aa..d1be2f1322bd9fa0e9d1fea982656bc14f35e69d 100644
--- a/libraries/technology/ip_agi027_xxxx/fifo/README.txt
+++ b/libraries/technology/ip_agi027_xxxx/fifo/README.txt
@@ -29,7 +29,7 @@ Contents:
terminal command generate_ip_libs <buildset> and finish to save the changes.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
- . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original if case it needs to be modified.
+ . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original in case it needs to be modified.
- methode B:
. copy original ip_arria_e2sg_<fifo_name>.vhd file.
@@ -42,7 +42,7 @@ Contents:
directory using the terminal command generate_ip_libs <buildset> to finish it.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
- . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original if case it needs to be modified.
+ . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original in case it needs to be modified.
this yields:
@@ -82,7 +82,7 @@ Contents:
set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_xxxx/fifo/quartus/fifo.qsf could be added to the hdllib.cfg under
[quartus_project_file]. Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
- The Quartus project ip_agi027_xxxx_fif.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_fifo/ was used to verify that the FIFO IP
+ The Quartus project ip_agi027_xxxx_fifo.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_fifo/ was used to verify that the FIFO IP
actually synthesise to the appropriate FPGA resources. Use the Quartus GUI to manually select a top level component for synthesis e.g.
by right clicking the entity vhd file in the file tab of the Quartus project navigator window. For the (default) testcondition the
generics are set to 1024 words deep and 20 bits wide. Then check the resource usage in the synthesis and fitter reports.
diff --git a/libraries/technology/ip_agi027_xxxx/ram/README.txt b/libraries/technology/ip_agi027_xxxx/ram/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..86b2e05154011e1dacac7bdf9d579038d763e5da
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/README.txt
@@ -0,0 +1,247 @@
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/ram
+VERSION 01 - 20231110
+
+Contents:
+
+1) RAM components
+2) ROM components
+3) Agilex7 IP
+4) Inferred IP
+5) Memory initialization file
+6) Implementation options (LUTs or block RAM)
+7) Synthesis trials
+8) Agilex7 issues
+9) References
+
+
+
+1) RAM components:
+
+ Available:
+ ip_agi027_xxxx_ram_cr_cw = One read port with clock and one write port with clock and with separate address and same data width on both ports.
+ ip_agi027_xxxx_ram_crk_cw = One read port with clock and one write port with clock and with separate address and different data withs on both ports.
+ The data port widths maintain a power of two ratio between them.
+ ip_agi027_xxxx_ram_r_w = Single clock, one read port and one write port and with separate address and same data width on both ports.
+ ip_agi027_xxxx_ram_rw_rw = Two read/write ports each port with same clock and with separate address per port and same data width on both ports.
+
+ Unavailable:
+ ip_agi027_xxxx_ram_crw_crw = Two read/write ports each port with own port clock and with separate address and same data width on both ports.
+ For the Agilex 7 this IP can only be generated with 'Emulate TDP dual clock mode' and what this entails is described
+ under '8) Agilex7 issues'. With this mandatory enable option, this IP is not supported as used for previous technologies.
+ ip_agi027_xxxx_ram_crwk_crw = Two read/write ports each port with own port clock and with power of two ratio between port widths.
+ Not available, because the Agilex 7 does not support ratio widths in combination with true dual port mode.
+
+
+2) ROM components:
+ ip_agi027_xxxx_rom_r_w = Not available and not needed, because the ip_agi027_xxxx_ram_r_w can be used for ROM IP by not connecting the
+ write port. The IP could be created and than the vhd file can be derived from the generated HDL files and the
+ existing ip_stratixiv_rom_r.vhd file.
+
+
+
+3) Agilex7 IP
+
+ The RAM IPs were ported manually from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_xxxx by creating it in Quartus
+ using the same parameter settings by:
+
+ - methode A:
+ . copy original ip_arria_e2sg_<ram_name>.vhd and ip_arria_e2sg_<ram_name>.ip files.
+ . rename ip_arria_e2sg_<ram_name>.ip and .vhd into ip_agi027_xxxx_<ram_name>.ip and .vhd (also replace name inside the .vhd file)
+ . open in to Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
+ Finish automatically convert to "new" IP, note differences such as version.
+ . then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build directory using the
+ terminal command generate_ip_libs <buildset> and finish to save the changes.
+ . compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
+ necessary to make it work.
+ . git commit also the ip_agi027_xxxx_<ram_name>.ip to preserve the original in case it needs to be modified.
+
+ - methode B:
+ . copy original ip_arria_e2sg_<ram_name>.vhd file.
+ . rename ip_arria_e2sg_<ram_name>.vhd into ip_agi027_xxxx_<ram_name>.vhd (also replace name inside the .vhd file).
+ . open ip_arria_e2sg_<ram_name>.ip file in Quartus 19.4.0 build 64. No device family and device part need to be set.
+ . open also Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
+ . select the corresponding IP in the IP catalog in Quartus 23.2.0 and provide the filename as ip_agi027_xxxx_<ram_name>.ip
+ Finish automatically convert to IP, note differences such as version.
+ . save the changes and then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build
+ directory using the terminal command generate_ip_libs <buildset> to finish it.
+ . compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
+ necessary to make it work.
+ . git commit also the ip_agi027_xxxx_<ram_name>.ip to preserve the original if case it needs to be modified.
+
+ this yields:
+
+ ip_agi027_xxxx_ram_cr_cw.ip
+ ip_agi027_xxxx_ram_crk_cw.ip
+ is derived from the ip_arria10_e2sg_ram_crwk_crw by modifying it to feature a single read and a single write port,
+ and incorporating a dual-clock design with distinct clocks for reading and writing.
+ ip_agi027_xxxx_ram_r_w.ip
+ ip_agi027_xxxx_ram_rw_rw.ip
+ is derived from the ip_arria10_e2sg_ram_crw_crw, incorporating the modification to operate with a single clock.
+
+
+ The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_xxxx_ram_*.vhd
+ directly instantiates the altera_syncram component. The buildset for the agi027_xxxx is iwave.
+
+ The instantiation is copied manually from the ip_agi027_xxxx_ram_*/ram_2port_2040/sim/ip_agi027_xxxx_ram_*.vhd and saved in the
+ ip_agi027_xxxx_<ram_name>.vhd file. So the generated HDL files are no longer needed, because it could easily be derived
+ from the IP file and the files will be generated in the build directory (under iwave/qsys-generate/) when using the terminal command
+ generate_ip_libs <buildset>.
+
+ It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
+ that is a simulation package. However it resembles how it worked for Stratix IV with altera_mf.
+
+
+
+4) Inferred IP
+
+ The inferred Altera code was obtained using template insert with Quartus 14.0a10. The IPs with different port widths,
+ like the ram_crk_cw, can not be inferred from RTL code.
+ For the RAM the g_inferred generic is set to FALSE because the inferred instances do not yet support g_init_file.
+ It is possible to init the RAM using a function e.g. see the README.txt for arria10. But this is probably not being
+ applied (for now) because it's easier to generate an IP and use the altera_syncram component. The inferred ones
+ require more effort to make them work, because the structure of the inferred Altera code should let Quartus know
+ to use a RAM block for implementation.
+
+
+
+5) Memory initialization file
+
+ Often referred to as a .mif file. It is used to initialize the content of memory blocks within the design, specifying
+ the data to be stored in each memory location. This file must be included in the Quartus Projects. During synthesis,
+ the tool uses this file to iniliaze the memory blocks in the design.
+ To support the g_init_file requires first reading the file in a certain format, by providing a file path as a string,
+ which indicates the location of the file. This path is telative to the project folder in the build directory.
+ These files uses the Intel hex-standar and are word adressed (32 bits per address). For us an integer format or SLV
+ format with one value per line (line number = address) would be fine. Using SLV format is necessary if the RAM data
+ is wider than 32 bit, because VHDL integer range is only 2**32. The tb_common_pkg has functions to read such a file.
+ Previously Quartus created a mif file from this when it infers the RAM. However the UniBoard1 designs provided a mif
+ file that fits the RAM IP. Therefore it was easier initially to also use the RAM IP for Arria10, and this still holds
+ on, also for the Agilex7. For RadioHDL a generic RAM init file format is preferrable though. Currently the args tooling
+ with the command gen_rom_mmap.py (refer to [8]) is used to generate the register map as a text file, compresses it, and
+ then creates the corresponding .hex or .mif file from it. For other RAM initialization we generate a hex file with
+ Python or with the Memory Initialization Tool that Quartus Prime GUI provides ourselves. This tool allows you to
+ specify the initial contents of memories in your design visually.
+
+
+
+6) Implementation options (LUTs or block RAM)
+
+ The IP (and also the inferred) RAM can be set to use LUTs (MLAB), block RAM (M20K) or LCs, however this is not supported yet.
+
+ . For IP RAM this would imply adding a generic to set the appropriate parameter in the altera_syncram
+ . For inferred RAM this would imply adding a generic to be used for the syntype attribute.
+ For an example see the README.txt for arria10.
+
+
+
+7) Synthesis trials
+
+ All the synth .vhd files have been simulated and performed well.
+ The quartus/ram.qsf could be derived from the ip_arria10/ram/ folder and changed to only the following assignments:
+ set_global_assignment -name FAMILY "Agilex 7"
+ set_global_assignment -name DEVICE AGIB027R31A1I1VB
+ set_global_assignment -name LAST_QUARTUS_VERSION "23.2.0 Pro Edition"
+ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+ set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+ set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
+ set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
+ set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
+ quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_xxxx/ram/quartus/ram.qsf could be added to the hdllib.cfg under
+ [quartus_project_file]. Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
+ The Quartus project ip_agi027_xxxx_ram.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_ram/ was used to verify that the block RAM IP
+ actually synthesise to the appropriate FPGA resources. The current version of the inferred RAM is verified at arria10. Use the Quartus
+ GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file in the file tab of the Quartus
+ project navigator window. For the (default) testcondition the generics are set to 32 words memory size and 8 bits wide. They only differ
+ for crk_cw waarbij the generics are set to 32 words memory size for writing, 32 bits wide of each write port, 16 words memory size for
+ reading and 64 bits wide of each write port. Then check the resource usage in the synthesis and fitter reports.
+ The most important information from these reports is (found under Place Stage > Resource Usage Summary / Resource Utilazation by Entity):
+ . for g_nof_words equal to 32 and for g_dat_w equal to 8:
+ . one M20k block ram is used, but it is not completely filled. 8 * 32 = 256 block memory bits.
+ . no M20k block ram is used. Instead, 256 MLAB memory bits are used along with combinational ALUT usage and 8 memory ALUT usage.
+ . for g_nof_words equal to 1024 and for g_dat_w equal to 20, exactly one M20k block ram is used and filled completely.
+ 20 * 1024 = 20480 block memory bits.
+ . for g_wr_nof_words equal to 32, g_wr_dat_w equal to 32, g_rd_nof_words equal to 16, and g_rd_dat_w equal to 64, two M20k block RAMs are
+ used, but they are not completely filled. Only 1024 block memory bits are used. 32 * 32 = 1024 block memory bits. A reasonable explanation
+ for this is that the data width is greater than 40 bits, which is the maximum data width with this memory size for one block ram. [2]
+ . the total M20k blocks is 13272. Thus the total block memory bits that is available is 13272 * 20480 = 271810560 when optimal use.
+ . no dsp blocks are used.
+ . the total dsp blocks on the device is 8528.
+ . the dedicated logic registers are 5 of the primary type.
+ . the total logic registers are 1825600 for each type.
+ . the used LABs is 5 (4 logic/1 memory).
+ . the total LABs on device is 91280.
+ . no ALMs needed for cr_cw, crk_cw and rw_rw.
+ . the ALMs needed [=A-B+C] for r_w is 13.
+ . the total ALMs on device is 912800.
+ . due to a critical warning that occured during synthesis of cr_cw (refer to [4]), it was identified that the issue arises when it uses dual
+ clock in conjunction with the read_during_write_mode_mixed_ports => "OLD_DATA". According to altera_syncram user guide, this configuration
+ is only supported when the same clock is utilized. Currently, the parameter value is set to "OLD_DATA", because when this parameter it is
+ set to "DONT_CARE" for the ip_arria10_e2sg_ram_crw_crw this eliminates the warning, but the regression test then fails. Implementing this
+ correctly across all technologies requires additonal effort. It is possible that this configuration may be applied in the future.
+ . due to the same parameter an error occurs for rw_rw. As a result the parameter value is now set to DONT_CARE in stead of OLD_DATA to resolve
+ the error. [3]
+
+
+
+8) Agilex7 issues
+
+ No (direct) available use of ip_agi027_xxxx_ram_crw_crw and *_crwk_crw. The other .vhd synth files based on generated HDL files of the IPs did not
+ encounter any issues.
+
+ crw_crw (dual-clock-read-write port RAM):
+ -Cause:
+ Due to the error that occurs in the Quartus configuration (refer to [5]), the parameter "emulate TDP dual clock mode" needs to be enabled.
+ As a result, this synthesis file cannot easily be ported. While the file can be successfully configured, it cannot be used differently without
+ a significant latency. This limitation arises because the VHDL synthesis code of this IP must utilize the TDP dual clock emulator, which consists
+ of two DCFIFOs and a single RAM block. However, it is preferable to resolve this issue at a higher layer where the implementation occurs.
+
+ -Explanation:
+ Nevertheless according to the user manual of the Agilex 7, when you engage the TDP dual clock emulator feature (refer to [1]):
+ . the clock connection to port A must be a slow clock (clock A).
+ . the clock connection to port B must be a fast clock (clock B).
+ . the clock frequency ratio of clock B divided by clock A is greater than or equal to seven.
+ . port A and port B will have different latency, it can only be used with a minimum latency of five clock cycles (of clock A), which is significant.
+ . the latency for port A decreases as the difference between the two clock frequencies increase.
+ . the latency for port b is fixed to two clock cycles and the output registers are enabled for this configuration.
+ . the FIFO addresses clock domain crossing (CDC) issues for the control signals and serves as a temporary buffer for storing data before and after
+ being processing by the RAM block.
+ . the FIFO depth can be adjusted with the use of a generic.
+ . the FIFO depth must be a power of 2 and must exceed the clock frequency ratio (B/A) to ensure the proper functioning of the emulated TDP.
+
+ -Solution:
+ This results in the utilization of a newly created IP, ip_agi027_xxxx_ram_rw_rw, which is a single-clock dual-read-write RAM, instead of *_crw_crw. And
+ address the solution at the higher-level layers where the implementation is occurring. This is appropriate due to the structure of the HDL git repository.
+ For this new IP, tech_memory_ram_rw_rw is created, wherein rw_rw functionality is constructed for the previous technology identifiers using the crw_crw
+ IP synthesis files in only one clock domain by providing the same clock signal twice, and no new rw_rw IPs need to be generated.
+ The 'common_ram_rw_rw' and 'common_paged_ram_rw_rw' files had to be modified to facilitate the integration of this new RAM IP. Additionally, an extra
+ testbench is created to simulate the "paged" file by duplicating the '*_crw_crw' version. This adjustment was necessary because previously, the
+ 'common_(paged_)_ram_crw_crw' files were underlying utilized by the 'rw_rw' files, and the usage has now been shifted to these files.
+
+ crwk_crw (dual-clock-read-write port with a power of two data width ratio):
+ -Cause:
+ Due to the errors that occurs in the Quartus configuration (refer to [5], [6] and [7]), the ip_agi027_xxxx_ram_crwk_crw cannot be ported.
+ This IP has also the same issue due to the clocking method as crw_crw, but also has additonal issues due to incompatibility for different data withs
+ for true dual port RAM.
+
+ -Solution:
+ To facilitate a specific aspect of the functionality provided by crwk_crw, specifically its integration into common_ram_cr_cw_ratio, a newly IP,
+ ip_agi027_xxxx_crk_cw is created instead of *_crwk_crw. Which is a dual-clock simple-dual-read-write RAM. Unfortunately, there is no built-in
+ implementation or solution for achieving the same functionality as crwk_crw for backward compatibility with Arria10 in the Quartus tool.
+ This implies that a custom implementation must be created at higher-level layers to achieve this functionality.
+ For this new IP, tech_memory_ram_crk_cw is created, wherein crk_cw functionality is made compatible for the existing technology identifiers using the crwk_crw
+ IP synthesis files, by utilizing only the read port for one clock domain and only the write port for the other, eliminating the need to generate new rw_rw IPs.
+ The 'common_ram_cr_cw_ratio' file had to be modified to facilitate the integration of this new RAM IP. No additional testbench is created for simulation,
+ as there is also no testbench for the underlying 'common_ram_crw_crw_ratio' file that was utilized.
+
+
+9) References:
+
+ [1] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/true-dual-port-dual-clock-emulator.html
+ [2] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/embedded-memory-configurations.html
+ [3] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/mixed-port-read-during-write-mode.html
+ [4] Critical Warning(15003): "mixed_port_feed_through_mode" parameter of RAM atom gen_ip.u_altera_syncram|auto_generated|altera_syncram_impl1|ram_block2a5 cannot have value "old" when different read and write clocks are used.
+ [5] Error: In 'Clks/Rd, Byte En' tab. 'Emulate TDP dual clock mode' must be enabled if clocking method is 'Customize clocks for A and B ports' for Agilex 7 while using two read/write ports.
+ [6] Error: In 'Widths/Blk Type' tab, the valid ratio between widths of port A and port B is 1 for device family Agilex 7 while using two read/write ports.
+ [7] Error: In 'Widths/Blk Type' tab. 'Use different data widths on different ports' feature cannot be enabled as the valid ratio between port A and B must be 1 for Agilex 7 while using two read/write ports.
+ [8] ARGS tool script to generate fpgamap.py M&C Python client include file
diff --git a/libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..fb25e87c10cf7b56120d1b51fbfe036faec1c36b
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_agi027_xxxx_ram
+hdl_library_clause_name = ip_agi027_xxxx_ram_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+ ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd
+ ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd
+ ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd
+
+ ip_agi027_xxxx_ram_cr_cw.vhd
+ ip_agi027_xxxx_ram_crk_cw.vhd
+ ip_agi027_xxxx_ram_rw_rw.vhd
+ ip_agi027_xxxx_ram_r_w.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.ip b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.ip
new file mode 100644
index 0000000000000000000000000000000000000000..b5a1ecff7fe5b5333e77a26f93f8c00e8f317326
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.ip
@@ -0,0 +1,884 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
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+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdclock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>ram_2port</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>data</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>q</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wraddress</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdaddress</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wren</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrclock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdclock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_ram_cr_cw</ipxact:library>
+ <ipxact:name>ram_2port</ipxact:name>
+ <ipxact:version>20.4.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device Family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MODE" type="int">
+ <ipxact:name>GUI_MODE</ipxact:name>
+ <ipxact:displayName>Operation Mode</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEM_IN_BITS" type="int">
+ <ipxact:name>GUI_MEM_IN_BITS</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEMSIZE_BITS" type="int">
+ <ipxact:name>GUI_MEMSIZE_BITS</ipxact:name>
+ <ipxact:displayName>How many bits of memory?</ipxact:displayName>
+ <ipxact:value>256</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEMSIZE_WORDS" type="int">
+ <ipxact:name>GUI_MEMSIZE_WORDS</ipxact:name>
+ <ipxact:displayName>How many words of memory?</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_QA_WIDTH" type="int">
+ <ipxact:name>GUI_QA_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'q_a' output bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_QB_WIDTH" type="int">
+ <ipxact:name>GUI_QB_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'q_b' output bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DATAA_WIDTH" type="int">
+ <ipxact:name>GUI_DATAA_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'data_a' input bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH" type="string">
+ <ipxact:name>GUI_MAX_DEPTH</ipxact:name>
+ <ipxact:displayName>Set the maximum block depth to</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_ECCENCPARITY" type="int">
+ <ipxact:name>GUI_WIDTH_ECCENCPARITY</ipxact:name>
+ <ipxact:displayName>Set the ecc enc parity width</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TBENCH" type="bit">
+ <ipxact:name>GUI_TBENCH</ipxact:name>
+ <ipxact:displayName>TESTING</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TDP_EMULATE" type="bit">
+ <ipxact:name>GUI_TDP_EMULATE</ipxact:name>
+ <ipxact:displayName>Emulate TDP dual clock mode</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_VAR_WIDTH" type="bit">
+ <ipxact:name>GUI_VAR_WIDTH</ipxact:name>
+ <ipxact:displayName>Use different data widths on different ports</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RAM_BLOCK_TYPE" type="string">
+ <ipxact:name>GUI_RAM_BLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>Ram Block Type</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LC_IMPLEMENTION_OPTIONS" type="int">
+ <ipxact:name>GUI_LC_IMPLEMENTION_OPTIONS</ipxact:name>
+ <ipxact:displayName>How should the memory be implemented?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_FILE_REFERENCE" type="int">
+ <ipxact:name>GUI_FILE_REFERENCE</ipxact:name>
+ <ipxact:displayName>Initialization File:</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_OPTIMIZATION_OPTION" type="int">
+ <ipxact:name>GUI_OPTIMIZATION_OPTION</ipxact:name>
+ <ipxact:displayName>Which timing/power optimization option do you want to use?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLOCK_TYPE" type="int">
+ <ipxact:name>GUI_CLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>Which clocking method do you want to use?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDEN_SINGLE" type="bit">
+ <ipxact:name>GUI_RDEN_SINGLE</ipxact:name>
+ <ipxact:displayName>Create a 'rden' read enable signal</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDEN_DOUBLE" type="bit">
+ <ipxact:name>GUI_RDEN_DOUBLE</ipxact:name>
+ <ipxact:displayName>Create 'rden_a' and 'rden_b' read enable signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_A" type="bit">
+ <ipxact:name>GUI_BYTE_ENABLE_A</ipxact:name>
+ <ipxact:displayName>Create byte enable for port A</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_B" type="bit">
+ <ipxact:name>GUI_BYTE_ENABLE_B</ipxact:name>
+ <ipxact:displayName>Create byte enable for port B</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_DOUBLE" type="bit">
+ <ipxact:name>GUI_ECC_DOUBLE</ipxact:name>
+ <ipxact:displayName>Enable Error Correction Check (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_TRIPLE" type="bit">
+ <ipxact:name>GUI_ECC_TRIPLE</ipxact:name>
+ <ipxact:displayName>Enable Error Correction Check (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_PIPELINE" type="bit">
+ <ipxact:name>GUI_ECC_PIPELINE</ipxact:name>
+ <ipxact:displayName>Enable ECC Pipeline Registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECCENCBYPASS" type="bit">
+ <ipxact:name>GUI_ECCENCBYPASS</ipxact:name>
+ <ipxact:displayName>Enable ECC Encoder Bypass</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_COHERENT_READ" type="bit">
+ <ipxact:name>GUI_COHERENT_READ</ipxact:name>
+ <ipxact:displayName>Enable Coherent Read</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_FORCE_TO_ZERO" type="bit">
+ <ipxact:name>GUI_FORCE_TO_ZERO</ipxact:name>
+ <ipxact:displayName>Enable Force To Zero</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_PR" type="bit">
+ <ipxact:name>GUI_PR</ipxact:name>
+ <ipxact:displayName>Implement clock-enable circuitry for use in a partial reconfiguration region</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_WIDTH" type="int">
+ <ipxact:name>GUI_BYTE_ENABLE_WIDTH</ipxact:name>
+ <ipxact:displayName>What is the width of a byte for byte enables?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WRITE_INPUT_PORTS" type="bit">
+ <ipxact:name>GUI_WRITE_INPUT_PORTS</ipxact:name>
+ <ipxact:displayName>All write input ports</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_INPUT_RDADDRESS" type="bit">
+ <ipxact:name>GUI_READ_INPUT_RDADDRESS</ipxact:name>
+ <ipxact:displayName>rdaddress port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DIFFERENT_CLKENS" type="bit">
+ <ipxact:name>GUI_DIFFERENT_CLKENS</ipxact:name>
+ <ipxact:displayName>Use different clock enables for registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_WRITE_INPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_WRITE_INPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for write input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_READ_INPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_READ_INPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for read input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_READ_OUTPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_READ_OUTPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_INPUT_REG_A" type="bit">
+ <ipxact:name>GUI_CLKEN_INPUT_REG_A</ipxact:name>
+ <ipxact:displayName>Use clock enable for port A input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_INPUT_REG_B" type="bit">
+ <ipxact:name>GUI_CLKEN_INPUT_REG_B</ipxact:name>
+ <ipxact:displayName>Use clock enable for port B input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_OUTPUT_REG_A" type="bit">
+ <ipxact:name>GUI_CLKEN_OUTPUT_REG_A</ipxact:name>
+ <ipxact:displayName>Use clock enable for port A output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_OUTPUT_REG_B" type="bit">
+ <ipxact:name>GUI_CLKEN_OUTPUT_REG_B</ipxact:name>
+ <ipxact:displayName>Use clock enable for port B output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_ADDRESS_STALL_A" type="bit">
+ <ipxact:name>GUI_CLKEN_ADDRESS_STALL_A</ipxact:name>
+ <ipxact:displayName>Create an addressstall_a input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_ADDRESS_STALL_B" type="bit">
+ <ipxact:name>GUI_CLKEN_ADDRESS_STALL_B</ipxact:name>
+ <ipxact:displayName>Create an addressstall_b input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_WRADDRESSSTALL" type="bit">
+ <ipxact:name>GUI_CLKEN_WRADDRESSSTALL</ipxact:name>
+ <ipxact:displayName>Create an wr_addressstall input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_RDADDRESSSTALL" type="bit">
+ <ipxact:name>GUI_CLKEN_RDADDRESSSTALL</ipxact:name>
+ <ipxact:displayName>Create an rd_addressstall input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_INPUT_RDADDRESS" type="bit">
+ <ipxact:name>GUI_ACLR_READ_INPUT_RDADDRESS</ipxact:name>
+ <ipxact:displayName>rdaddress port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_ACLR_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_ACLR_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SCLR_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_SCLR_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SCLR_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_SCLR_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Q_PORT_MODE" type="int">
+ <ipxact:name>GUI_Q_PORT_MODE</ipxact:name>
+ <ipxact:displayName><html>How should the q_a and q_b outputs behave when reading a memory location<br>that is being written from the other port?</html></ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CONSTRAINED_DONT_CARE" type="bit">
+ <ipxact:name>GUI_CONSTRAINED_DONT_CARE</ipxact:name>
+ <ipxact:displayName><html>Do not analyze the timing between write and read operation. Metastabillity issues are<br>prevented by never writing and reading at the same address at the same time.</html></ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDW_A_MODE" type="string">
+ <ipxact:name>GUI_RDW_A_MODE</ipxact:name>
+ <ipxact:displayName>What should the q_a output be when reading from a memory location being written to?</ipxact:displayName>
+ <ipxact:value>New Data</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDW_B_MODE" type="string">
+ <ipxact:name>GUI_RDW_B_MODE</ipxact:name>
+ <ipxact:displayName>What should the q_b output be when reading from a memory location being written to?</ipxact:displayName>
+ <ipxact:value>New Data</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_NBE_A" type="bit">
+ <ipxact:name>GUI_NBE_A</ipxact:name>
+ <ipxact:displayName>Get x's for write masked bytes instead of old data when byte enable is used</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_NBE_B" type="bit">
+ <ipxact:name>GUI_NBE_B</ipxact:name>
+ <ipxact:displayName>Get x's for write masked bytes instead of old data when byte enable is used</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BLANK_MEMORY" type="int">
+ <ipxact:name>GUI_BLANK_MEMORY</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_INIT_FILE_LAYOUT" type="string">
+ <ipxact:name>GUI_INIT_FILE_LAYOUT</ipxact:name>
+ <ipxact:displayName>The initial content file should conform to which port's dimensions?</ipxact:displayName>
+ <ipxact:value>PORT_B</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_INIT_SIM_TO_X" type="bit">
+ <ipxact:name>GUI_INIT_SIM_TO_X</ipxact:name>
+ <ipxact:displayName>Initialize memory content data to XX..X on power-up in simulation</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MIF_FILENAME" type="string">
+ <ipxact:name>GUI_MIF_FILENAME</ipxact:name>
+ <ipxact:displayName>File name</ipxact:displayName>
+ <ipxact:value>./ram_1024.hex</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="clock" altera:internal="ram_2port_0.clock"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="data" altera:internal="ram_2port_0.data" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="data" altera:internal="data"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="q" altera:internal="ram_2port_0.q" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="q" altera:internal="q"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rdaddress" altera:internal="ram_2port_0.rdaddress" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rdaddress" altera:internal="rdaddress"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rdclock" altera:internal="ram_2port_0.rdclock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="rdclock" altera:internal="rdclock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="wraddress" altera:internal="ram_2port_0.wraddress" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="wraddress" altera:internal="wraddress"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="wrclock" altera:internal="ram_2port_0.wrclock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="wrclock" altera:internal="wrclock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="wren" altera:internal="ram_2port_0.wren" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="wren" altera:internal="wren"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.vhd b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..808061d154f634e3720ba99fe99bcaf7c4ccb1da
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.vhd
@@ -0,0 +1,163 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper / Instantiate RAM IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_cr_cw_ram_2port_2040_cmcw2dy.vhd
+
+library ieee, technology_lib;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use technology_lib.technology_pkg.all;
+
+library altera_lnsim;
+use altera_lnsim.altera_lnsim_components.all;
+
+entity ip_agi027_xxxx_ram_cr_cw is
+ generic (
+ g_inferred : boolean := false;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port (
+ data : in std_logic_vector(g_dat_w - 1 downto 0);
+ rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
+ rdclk : in std_logic;
+ wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
+ wrclk : in std_logic := '1';
+ wren : in std_logic := '0';
+ q : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_ram_cr_cw;
+
+architecture SYN of ip_agi027_xxxx_ram_cr_cw is
+ constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
+
+ component altera_syncram
+ generic (
+ address_aclr_b : string;
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_b : string;
+ init_file : string;
+ -- enable_force_to_zero : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_b : string;
+ -- outdata_sclr_b : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ read_during_write_mode_mixed_ports : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer
+ );
+ port (
+ address_a : in std_logic_vector(g_adr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_adr_w - 1 downto 0);
+ clock0 : in std_logic;
+ clock1 : in std_logic;
+ data_a : in std_logic_vector(g_dat_w - 1 downto 0);
+ wren_a : in std_logic;
+ q_b : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+ end component;
+
+ signal rdaddr : natural range 0 to g_nof_words - 1;
+ signal wraddr : natural range 0 to g_nof_words - 1;
+
+ signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
+ signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
+begin
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
+
+ gen_ip : if g_inferred = false generate
+ u_altera_syncram : altera_syncram
+ generic map (
+ address_aclr_b => "NONE",
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ init_file => g_init_file,
+ -- enable_force_to_zero => "FALSE",
+ intended_device_family => "Agilex 7",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words,
+ numwords_b => g_nof_words,
+ operation_mode => "DUAL_PORT",
+ outdata_aclr_b => "NONE",
+ -- outdata_sclr_b => "NONE",
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_mixed_ports => "OLD_DATA",
+ widthad_a => g_adr_w,
+ widthad_b => g_adr_w,
+ width_a => g_dat_w,
+ width_b => g_dat_w,
+ width_byteena_a => 1
+ )
+ port map (
+ address_a => wraddress,
+ address_b => rdaddress,
+ clock0 => wrclk,
+ clock1 => rdclk,
+ data_a => data,
+ wren_a => wren,
+ q_b => q
+ );
+ end generate;
+
+ gen_inferred : if g_inferred = true generate
+ rdaddr <= to_integer(unsigned(rdaddress));
+ wraddr <= to_integer(unsigned(wraddress));
+
+ u_mem : entity work.ip_agi027_xxxx_simple_dual_port_ram_dual_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ rclk => rdclk,
+ wclk => wrclk,
+ raddr => rdaddr,
+ waddr => wraddr,
+ data => data,
+ we => wren,
+ q => out_q
+ );
+
+ reg_q <= out_q when rising_edge(rdclk);
+
+ q <= out_q when g_rd_latency = 1 else reg_q;
+ end generate;
+
+end SYN;
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.ip b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.ip
new file mode 100644
index 0000000000000000000000000000000000000000..f4b52b5e2069ff32bddfd611ca45e219cabc3f40
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.ip
@@ -0,0 +1,898 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_ram_crk_cw</ipxact:library>
+ <ipxact:name>ram_2port_0</ipxact:name>
+ <ipxact:version>20.4.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>data</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datain</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>data</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>q</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataout</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>q</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>wraddress</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wraddress</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wraddress</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>rdaddress</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdaddress</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdaddress</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>wren</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wren</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wren</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>wrclock</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrclock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>rdclock</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdclock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>ram_2port</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>data</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>q</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wraddress</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdaddress</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>9</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wren</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrclock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdclock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_ram_crk_cw</ipxact:library>
+ <ipxact:name>ram_2port</ipxact:name>
+ <ipxact:version>20.4.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device Family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MODE" type="int">
+ <ipxact:name>GUI_MODE</ipxact:name>
+ <ipxact:displayName>Operation Mode</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEM_IN_BITS" type="int">
+ <ipxact:name>GUI_MEM_IN_BITS</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEMSIZE_BITS" type="int">
+ <ipxact:name>GUI_MEMSIZE_BITS</ipxact:name>
+ <ipxact:displayName>How many bits of memory?</ipxact:displayName>
+ <ipxact:value>256</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEMSIZE_WORDS" type="int">
+ <ipxact:name>GUI_MEMSIZE_WORDS</ipxact:name>
+ <ipxact:displayName>How many words of memory?</ipxact:displayName>
+ <ipxact:value>256</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_QA_WIDTH" type="int">
+ <ipxact:name>GUI_QA_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'q_a' output bus be?</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_QB_WIDTH" type="int">
+ <ipxact:name>GUI_QB_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'q_b' output bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DATAA_WIDTH" type="int">
+ <ipxact:name>GUI_DATAA_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'data_a' input bus be?</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH" type="string">
+ <ipxact:name>GUI_MAX_DEPTH</ipxact:name>
+ <ipxact:displayName>Set the maximum block depth to</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_ECCENCPARITY" type="int">
+ <ipxact:name>GUI_WIDTH_ECCENCPARITY</ipxact:name>
+ <ipxact:displayName>Set the ecc enc parity width</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TBENCH" type="bit">
+ <ipxact:name>GUI_TBENCH</ipxact:name>
+ <ipxact:displayName>TESTING</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TDP_EMULATE" type="bit">
+ <ipxact:name>GUI_TDP_EMULATE</ipxact:name>
+ <ipxact:displayName>Emulate TDP dual clock mode</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_VAR_WIDTH" type="bit">
+ <ipxact:name>GUI_VAR_WIDTH</ipxact:name>
+ <ipxact:displayName>Use different data widths on different ports</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RAM_BLOCK_TYPE" type="string">
+ <ipxact:name>GUI_RAM_BLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>Ram Block Type</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LC_IMPLEMENTION_OPTIONS" type="int">
+ <ipxact:name>GUI_LC_IMPLEMENTION_OPTIONS</ipxact:name>
+ <ipxact:displayName>How should the memory be implemented?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_FILE_REFERENCE" type="int">
+ <ipxact:name>GUI_FILE_REFERENCE</ipxact:name>
+ <ipxact:displayName>Initialization File:</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_OPTIMIZATION_OPTION" type="int">
+ <ipxact:name>GUI_OPTIMIZATION_OPTION</ipxact:name>
+ <ipxact:displayName>Which timing/power optimization option do you want to use?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLOCK_TYPE" type="int">
+ <ipxact:name>GUI_CLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>Which clocking method do you want to use?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDEN_SINGLE" type="bit">
+ <ipxact:name>GUI_RDEN_SINGLE</ipxact:name>
+ <ipxact:displayName>Create a 'rden' read enable signal</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDEN_DOUBLE" type="bit">
+ <ipxact:name>GUI_RDEN_DOUBLE</ipxact:name>
+ <ipxact:displayName>Create 'rden_a' and 'rden_b' read enable signals</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_A" type="bit">
+ <ipxact:name>GUI_BYTE_ENABLE_A</ipxact:name>
+ <ipxact:displayName>Create byte enable for port A</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_B" type="bit">
+ <ipxact:name>GUI_BYTE_ENABLE_B</ipxact:name>
+ <ipxact:displayName>Create byte enable for port B</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_DOUBLE" type="bit">
+ <ipxact:name>GUI_ECC_DOUBLE</ipxact:name>
+ <ipxact:displayName>Enable Error Correction Check (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_TRIPLE" type="bit">
+ <ipxact:name>GUI_ECC_TRIPLE</ipxact:name>
+ <ipxact:displayName>Enable Error Correction Check (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_PIPELINE" type="bit">
+ <ipxact:name>GUI_ECC_PIPELINE</ipxact:name>
+ <ipxact:displayName>Enable ECC Pipeline Registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECCENCBYPASS" type="bit">
+ <ipxact:name>GUI_ECCENCBYPASS</ipxact:name>
+ <ipxact:displayName>Enable ECC Encoder Bypass</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_COHERENT_READ" type="bit">
+ <ipxact:name>GUI_COHERENT_READ</ipxact:name>
+ <ipxact:displayName>Enable Coherent Read</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_FORCE_TO_ZERO" type="bit">
+ <ipxact:name>GUI_FORCE_TO_ZERO</ipxact:name>
+ <ipxact:displayName>Enable Force To Zero</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_PR" type="bit">
+ <ipxact:name>GUI_PR</ipxact:name>
+ <ipxact:displayName>Implement clock-enable circuitry for use in a partial reconfiguration region</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_WIDTH" type="int">
+ <ipxact:name>GUI_BYTE_ENABLE_WIDTH</ipxact:name>
+ <ipxact:displayName>What is the width of a byte for byte enables?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WRITE_INPUT_PORTS" type="bit">
+ <ipxact:name>GUI_WRITE_INPUT_PORTS</ipxact:name>
+ <ipxact:displayName>All write input ports</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_INPUT_RDADDRESS" type="bit">
+ <ipxact:name>GUI_READ_INPUT_RDADDRESS</ipxact:name>
+ <ipxact:displayName>rdaddress port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DIFFERENT_CLKENS" type="bit">
+ <ipxact:name>GUI_DIFFERENT_CLKENS</ipxact:name>
+ <ipxact:displayName>Use different clock enables for registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_WRITE_INPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_WRITE_INPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for write input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_READ_INPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_READ_INPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for read input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_READ_OUTPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_READ_OUTPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_INPUT_REG_A" type="bit">
+ <ipxact:name>GUI_CLKEN_INPUT_REG_A</ipxact:name>
+ <ipxact:displayName>Use clock enable for port A input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_INPUT_REG_B" type="bit">
+ <ipxact:name>GUI_CLKEN_INPUT_REG_B</ipxact:name>
+ <ipxact:displayName>Use clock enable for port B input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_OUTPUT_REG_A" type="bit">
+ <ipxact:name>GUI_CLKEN_OUTPUT_REG_A</ipxact:name>
+ <ipxact:displayName>Use clock enable for port A output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_OUTPUT_REG_B" type="bit">
+ <ipxact:name>GUI_CLKEN_OUTPUT_REG_B</ipxact:name>
+ <ipxact:displayName>Use clock enable for port B output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_ADDRESS_STALL_A" type="bit">
+ <ipxact:name>GUI_CLKEN_ADDRESS_STALL_A</ipxact:name>
+ <ipxact:displayName>Create an addressstall_a input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_ADDRESS_STALL_B" type="bit">
+ <ipxact:name>GUI_CLKEN_ADDRESS_STALL_B</ipxact:name>
+ <ipxact:displayName>Create an addressstall_b input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_WRADDRESSSTALL" type="bit">
+ <ipxact:name>GUI_CLKEN_WRADDRESSSTALL</ipxact:name>
+ <ipxact:displayName>Create an wr_addressstall input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_RDADDRESSSTALL" type="bit">
+ <ipxact:name>GUI_CLKEN_RDADDRESSSTALL</ipxact:name>
+ <ipxact:displayName>Create an rd_addressstall input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_INPUT_RDADDRESS" type="bit">
+ <ipxact:name>GUI_ACLR_READ_INPUT_RDADDRESS</ipxact:name>
+ <ipxact:displayName>rdaddress port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_ACLR_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_ACLR_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SCLR_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_SCLR_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SCLR_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_SCLR_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Q_PORT_MODE" type="int">
+ <ipxact:name>GUI_Q_PORT_MODE</ipxact:name>
+ <ipxact:displayName><html>How should the q_a and q_b outputs behave when reading a memory location<br>that is being written from the other port?</html></ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CONSTRAINED_DONT_CARE" type="bit">
+ <ipxact:name>GUI_CONSTRAINED_DONT_CARE</ipxact:name>
+ <ipxact:displayName><html>Do not analyze the timing between write and read operation. Metastabillity issues are<br>prevented by never writing and reading at the same address at the same time.</html></ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDW_A_MODE" type="string">
+ <ipxact:name>GUI_RDW_A_MODE</ipxact:name>
+ <ipxact:displayName>What should the q_a output be when reading from a memory location being written to?</ipxact:displayName>
+ <ipxact:value>New Data</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDW_B_MODE" type="string">
+ <ipxact:name>GUI_RDW_B_MODE</ipxact:name>
+ <ipxact:displayName>What should the q_b output be when reading from a memory location being written to?</ipxact:displayName>
+ <ipxact:value>New Data</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_NBE_A" type="bit">
+ <ipxact:name>GUI_NBE_A</ipxact:name>
+ <ipxact:displayName>Get x's for write masked bytes instead of old data when byte enable is used</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_NBE_B" type="bit">
+ <ipxact:name>GUI_NBE_B</ipxact:name>
+ <ipxact:displayName>Get x's for write masked bytes instead of old data when byte enable is used</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BLANK_MEMORY" type="int">
+ <ipxact:name>GUI_BLANK_MEMORY</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_INIT_FILE_LAYOUT" type="string">
+ <ipxact:name>GUI_INIT_FILE_LAYOUT</ipxact:name>
+ <ipxact:displayName>The initial content file should conform to which port's dimensions?</ipxact:displayName>
+ <ipxact:value>PORT_B</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_INIT_SIM_TO_X" type="bit">
+ <ipxact:name>GUI_INIT_SIM_TO_X</ipxact:name>
+ <ipxact:displayName>Initialize memory content data to XX..X on power-up in simulation</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MIF_FILENAME" type="string">
+ <ipxact:name>GUI_MIF_FILENAME</ipxact:name>
+ <ipxact:displayName>File name</ipxact:displayName>
+ <ipxact:value>./ram_1024.hex</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address_a" altera:internal="ram_2port_0.address_a"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="address_b" altera:internal="ram_2port_0.address_b"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock" altera:internal="ram_2port_0.clock"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock_a" altera:internal="ram_2port_0.clock_a"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock_b" altera:internal="ram_2port_0.clock_b"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="data" altera:internal="ram_2port_0.data" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="data" altera:internal="data"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="data_a" altera:internal="ram_2port_0.data_a"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="data_b" altera:internal="ram_2port_0.data_b"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="inclock" altera:internal="ram_2port_0.inclock"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="outclock" altera:internal="ram_2port_0.outclock"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="q" altera:internal="ram_2port_0.q" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="q" altera:internal="q"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="q_a" altera:internal="ram_2port_0.q_a"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="q_b" altera:internal="ram_2port_0.q_b"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rdaddress" altera:internal="ram_2port_0.rdaddress" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rdaddress" altera:internal="rdaddress"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rdclock" altera:internal="ram_2port_0.rdclock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="rdclock" altera:internal="rdclock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rden_a" altera:internal="ram_2port_0.rden_a"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rden_b" altera:internal="ram_2port_0.rden_b"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="wraddress" altera:internal="ram_2port_0.wraddress" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="wraddress" altera:internal="wraddress"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="wrclock" altera:internal="ram_2port_0.wrclock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="wrclock" altera:internal="wrclock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="wren" altera:internal="ram_2port_0.wren" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="wren" altera:internal="wren"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="wren_a" altera:internal="ram_2port_0.wren_a"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="wren_b" altera:internal="ram_2port_0.wren_b"></altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.vhd b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8d94883e3d19fc0f2a22ae0b86dcd0abecf52ee3
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.vhd
@@ -0,0 +1,143 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper / Instantiate RAM IP with generics
+-- Description:
+-- Simple dual port ram with dual clock domain and with ratio data widths
+-- Port a is only used for write in write clock domain
+-- Port b is only used for read in read clock domain
+-- Reference:
+-- Copied component declaration and instance example from
+-- generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_crk_cw_ram_2port_2040_aadk55y.vhd
+-- Remark:
+-- Created this IP for the Agilex 7 (agi027_xxxx) due to incompatibility with
+-- the standard crwk_crw IP variant, to facilitate its integration into
+-- common_ram_cr_cw_ratio.
+
+library ieee, technology_lib;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use technology_lib.technology_pkg.all;
+
+library altera_lnsim;
+use altera_lnsim.altera_lnsim_components.all;
+
+entity ip_agi027_xxxx_ram_crk_cw is
+ generic (
+ g_wr_adr_w : natural := 5;
+ g_wr_dat_w : natural := 32;
+ g_wr_nof_words : natural := 2**5;
+ g_rd_adr_w : natural := 4;
+ g_rd_dat_w : natural := 64;
+ g_rd_nof_words : natural := 2**4;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port (
+ data : in std_logic_vector(g_wr_dat_w - 1 downto 0);
+ wraddress : in std_logic_vector(g_wr_adr_w - 1 downto 0);
+ wrclk : in std_logic := '1';
+ wren : in std_logic := '0';
+ rdaddress : in std_logic_vector(g_rd_adr_w - 1 downto 0);
+ rdclk : in std_logic;
+ q : out std_logic_vector(g_rd_dat_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_ram_crk_cw;
+
+architecture SYN of ip_agi027_xxxx_ram_crk_cw is
+ constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
+
+ component altera_syncram
+ generic (
+ address_aclr_b : string;
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_b : string;
+ init_file : string;
+ init_file_layout : string;
+ -- enable_force_to_zero : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_b : string;
+ -- outdata_sclr_b : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer
+ );
+ port (
+ address_a : in std_logic_vector(g_wr_adr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_rd_adr_w - 1 downto 0);
+ clock0 : in std_logic;
+ clock1 : in std_logic;
+ data_a : in std_logic_vector(g_wr_dat_w - 1 downto 0);
+ wren_a : in std_logic;
+ q_b : out std_logic_vector(g_rd_dat_w - 1 downto 0)
+ );
+ end component;
+
+begin
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_crk_cw : read latency must be 1 (default) or 2" severity FAILURE;
+
+ u_altera_syncram : altera_syncram
+ generic map (
+ address_aclr_b => "NONE",
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ init_file => g_init_file,
+ init_file_layout => "PORT_B",
+ -- enable_force_to_zero => "FALSE",
+ intended_device_family => "Agilex 7",
+ lpm_type => "altera_syncram",
+ numwords_a => g_wr_nof_words,
+ numwords_b => g_rd_nof_words,
+ operation_mode => "DUAL_PORT",
+ outdata_aclr_b => "NONE",
+ -- outdata_sclr_b => "NONE",
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ widthad_a => g_wr_adr_w,
+ widthad_b => g_rd_adr_w,
+ width_a => g_wr_dat_w,
+ width_b => g_rd_dat_w,
+ width_byteena_a => 1
+ )
+ port map (
+ address_a => wraddress,
+ address_b => rdaddress,
+ clock0 => wrclk,
+ clock1 => rdclk,
+ data_a => data,
+ wren_a => wren,
+ q_b => q
+ );
+
+end SYN;
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.ip b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.ip
new file mode 100644
index 0000000000000000000000000000000000000000..9154a7b5047f40380afcb513ab66e76192b798db
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.ip
@@ -0,0 +1,821 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_ram_r_w</ipxact:library>
+ <ipxact:name>ram_2port_0</ipxact:name>
+ <ipxact:version>20.4.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>data</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datain</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>data</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>q</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataout</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>q</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>wraddress</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wraddress</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wraddress</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>rdaddress</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdaddress</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdaddress</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>wren</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wren</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wren</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>ram_2port</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>data</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>q</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wraddress</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdaddress</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wren</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_ram_r_w</ipxact:library>
+ <ipxact:name>ram_2port</ipxact:name>
+ <ipxact:version>20.4.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device Family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MODE" type="int">
+ <ipxact:name>GUI_MODE</ipxact:name>
+ <ipxact:displayName>Operation Mode</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEM_IN_BITS" type="int">
+ <ipxact:name>GUI_MEM_IN_BITS</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEMSIZE_BITS" type="int">
+ <ipxact:name>GUI_MEMSIZE_BITS</ipxact:name>
+ <ipxact:displayName>How many bits of memory?</ipxact:displayName>
+ <ipxact:value>256</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEMSIZE_WORDS" type="int">
+ <ipxact:name>GUI_MEMSIZE_WORDS</ipxact:name>
+ <ipxact:displayName>How many words of memory?</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_QA_WIDTH" type="int">
+ <ipxact:name>GUI_QA_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'q_a' output bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_QB_WIDTH" type="int">
+ <ipxact:name>GUI_QB_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'q_b' output bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DATAA_WIDTH" type="int">
+ <ipxact:name>GUI_DATAA_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'data_a' input bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH" type="string">
+ <ipxact:name>GUI_MAX_DEPTH</ipxact:name>
+ <ipxact:displayName>Set the maximum block depth to</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_ECCENCPARITY" type="int">
+ <ipxact:name>GUI_WIDTH_ECCENCPARITY</ipxact:name>
+ <ipxact:displayName>Set the ecc enc parity width</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TBENCH" type="bit">
+ <ipxact:name>GUI_TBENCH</ipxact:name>
+ <ipxact:displayName>TESTING</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TDP_EMULATE" type="bit">
+ <ipxact:name>GUI_TDP_EMULATE</ipxact:name>
+ <ipxact:displayName>Emulate TDP dual clock mode</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_VAR_WIDTH" type="bit">
+ <ipxact:name>GUI_VAR_WIDTH</ipxact:name>
+ <ipxact:displayName>Use different data widths on different ports</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RAM_BLOCK_TYPE" type="string">
+ <ipxact:name>GUI_RAM_BLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>Ram Block Type</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LC_IMPLEMENTION_OPTIONS" type="int">
+ <ipxact:name>GUI_LC_IMPLEMENTION_OPTIONS</ipxact:name>
+ <ipxact:displayName>How should the memory be implemented?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_FILE_REFERENCE" type="int">
+ <ipxact:name>GUI_FILE_REFERENCE</ipxact:name>
+ <ipxact:displayName>Initialization File:</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_OPTIMIZATION_OPTION" type="int">
+ <ipxact:name>GUI_OPTIMIZATION_OPTION</ipxact:name>
+ <ipxact:displayName>Which timing/power optimization option do you want to use?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLOCK_TYPE" type="int">
+ <ipxact:name>GUI_CLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>Which clocking method do you want to use?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDEN_SINGLE" type="bit">
+ <ipxact:name>GUI_RDEN_SINGLE</ipxact:name>
+ <ipxact:displayName>Create a 'rden' read enable signal</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDEN_DOUBLE" type="bit">
+ <ipxact:name>GUI_RDEN_DOUBLE</ipxact:name>
+ <ipxact:displayName>Create 'rden_a' and 'rden_b' read enable signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_A" type="bit">
+ <ipxact:name>GUI_BYTE_ENABLE_A</ipxact:name>
+ <ipxact:displayName>Create byte enable for port A</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_B" type="bit">
+ <ipxact:name>GUI_BYTE_ENABLE_B</ipxact:name>
+ <ipxact:displayName>Create byte enable for port B</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_DOUBLE" type="bit">
+ <ipxact:name>GUI_ECC_DOUBLE</ipxact:name>
+ <ipxact:displayName>Enable Error Correction Check (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_TRIPLE" type="bit">
+ <ipxact:name>GUI_ECC_TRIPLE</ipxact:name>
+ <ipxact:displayName>Enable Error Correction Check (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_PIPELINE" type="bit">
+ <ipxact:name>GUI_ECC_PIPELINE</ipxact:name>
+ <ipxact:displayName>Enable ECC Pipeline Registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECCENCBYPASS" type="bit">
+ <ipxact:name>GUI_ECCENCBYPASS</ipxact:name>
+ <ipxact:displayName>Enable ECC Encoder Bypass</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_COHERENT_READ" type="bit">
+ <ipxact:name>GUI_COHERENT_READ</ipxact:name>
+ <ipxact:displayName>Enable Coherent Read</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_FORCE_TO_ZERO" type="bit">
+ <ipxact:name>GUI_FORCE_TO_ZERO</ipxact:name>
+ <ipxact:displayName>Enable Force To Zero</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_PR" type="bit">
+ <ipxact:name>GUI_PR</ipxact:name>
+ <ipxact:displayName>Implement clock-enable circuitry for use in a partial reconfiguration region</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_WIDTH" type="int">
+ <ipxact:name>GUI_BYTE_ENABLE_WIDTH</ipxact:name>
+ <ipxact:displayName>What is the width of a byte for byte enables?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WRITE_INPUT_PORTS" type="bit">
+ <ipxact:name>GUI_WRITE_INPUT_PORTS</ipxact:name>
+ <ipxact:displayName>All write input ports</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_INPUT_RDADDRESS" type="bit">
+ <ipxact:name>GUI_READ_INPUT_RDADDRESS</ipxact:name>
+ <ipxact:displayName>rdaddress port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DIFFERENT_CLKENS" type="bit">
+ <ipxact:name>GUI_DIFFERENT_CLKENS</ipxact:name>
+ <ipxact:displayName>Use different clock enables for registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_WRITE_INPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_WRITE_INPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for write input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_READ_INPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_READ_INPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for read input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_READ_OUTPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_READ_OUTPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_INPUT_REG_A" type="bit">
+ <ipxact:name>GUI_CLKEN_INPUT_REG_A</ipxact:name>
+ <ipxact:displayName>Use clock enable for port A input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_INPUT_REG_B" type="bit">
+ <ipxact:name>GUI_CLKEN_INPUT_REG_B</ipxact:name>
+ <ipxact:displayName>Use clock enable for port B input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_OUTPUT_REG_A" type="bit">
+ <ipxact:name>GUI_CLKEN_OUTPUT_REG_A</ipxact:name>
+ <ipxact:displayName>Use clock enable for port A output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_OUTPUT_REG_B" type="bit">
+ <ipxact:name>GUI_CLKEN_OUTPUT_REG_B</ipxact:name>
+ <ipxact:displayName>Use clock enable for port B output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_ADDRESS_STALL_A" type="bit">
+ <ipxact:name>GUI_CLKEN_ADDRESS_STALL_A</ipxact:name>
+ <ipxact:displayName>Create an addressstall_a input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_ADDRESS_STALL_B" type="bit">
+ <ipxact:name>GUI_CLKEN_ADDRESS_STALL_B</ipxact:name>
+ <ipxact:displayName>Create an addressstall_b input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_WRADDRESSSTALL" type="bit">
+ <ipxact:name>GUI_CLKEN_WRADDRESSSTALL</ipxact:name>
+ <ipxact:displayName>Create an wr_addressstall input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_RDADDRESSSTALL" type="bit">
+ <ipxact:name>GUI_CLKEN_RDADDRESSSTALL</ipxact:name>
+ <ipxact:displayName>Create an rd_addressstall input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_INPUT_RDADDRESS" type="bit">
+ <ipxact:name>GUI_ACLR_READ_INPUT_RDADDRESS</ipxact:name>
+ <ipxact:displayName>rdaddress port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_ACLR_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_ACLR_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SCLR_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_SCLR_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SCLR_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_SCLR_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Q_PORT_MODE" type="int">
+ <ipxact:name>GUI_Q_PORT_MODE</ipxact:name>
+ <ipxact:displayName><html>How should the q_a and q_b outputs behave when reading a memory location<br>that is being written from the other port?</html></ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CONSTRAINED_DONT_CARE" type="bit">
+ <ipxact:name>GUI_CONSTRAINED_DONT_CARE</ipxact:name>
+ <ipxact:displayName><html>Do not analyze the timing between write and read operation. Metastabillity issues are<br>prevented by never writing and reading at the same address at the same time.</html></ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDW_A_MODE" type="string">
+ <ipxact:name>GUI_RDW_A_MODE</ipxact:name>
+ <ipxact:displayName>What should the q_a output be when reading from a memory location being written to?</ipxact:displayName>
+ <ipxact:value>New Data</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDW_B_MODE" type="string">
+ <ipxact:name>GUI_RDW_B_MODE</ipxact:name>
+ <ipxact:displayName>What should the q_b output be when reading from a memory location being written to?</ipxact:displayName>
+ <ipxact:value>New Data</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_NBE_A" type="bit">
+ <ipxact:name>GUI_NBE_A</ipxact:name>
+ <ipxact:displayName>Get x's for write masked bytes instead of old data when byte enable is used</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_NBE_B" type="bit">
+ <ipxact:name>GUI_NBE_B</ipxact:name>
+ <ipxact:displayName>Get x's for write masked bytes instead of old data when byte enable is used</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BLANK_MEMORY" type="int">
+ <ipxact:name>GUI_BLANK_MEMORY</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_INIT_FILE_LAYOUT" type="string">
+ <ipxact:name>GUI_INIT_FILE_LAYOUT</ipxact:name>
+ <ipxact:displayName>The initial content file should conform to which port's dimensions?</ipxact:displayName>
+ <ipxact:value>PORT_B</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_INIT_SIM_TO_X" type="bit">
+ <ipxact:name>GUI_INIT_SIM_TO_X</ipxact:name>
+ <ipxact:displayName>Initialize memory content data to XX..X on power-up in simulation</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MIF_FILENAME" type="string">
+ <ipxact:name>GUI_MIF_FILENAME</ipxact:name>
+ <ipxact:displayName>File name</ipxact:displayName>
+ <ipxact:value>./ram_1024.hex</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="clock" altera:internal="ram_2port_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="data" altera:internal="ram_2port_0.data" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="data" altera:internal="data"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="q" altera:internal="ram_2port_0.q" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="q" altera:internal="q"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rdaddress" altera:internal="ram_2port_0.rdaddress" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rdaddress" altera:internal="rdaddress"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="wraddress" altera:internal="ram_2port_0.wraddress" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="wraddress" altera:internal="wraddress"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="wren" altera:internal="ram_2port_0.wren" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="wren" altera:internal="wren"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.vhd b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..145e9a1d040e80a98952204cf75a49c73a039673
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.vhd
@@ -0,0 +1,159 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D. F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper / Instantiate RAM IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_r_w_ram_2port_2040_gbkw2ny.vhd
+
+library ieee, technology_lib;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use technology_lib.technology_pkg.all;
+
+library altera_lnsim;
+use altera_lnsim.altera_lnsim_components.all;
+
+entity ip_agi027_xxxx_ram_r_w is
+ generic (
+ g_inferred : boolean := false;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port (
+ clk : in std_logic := '1';
+ data : in std_logic_vector(g_dat_w - 1 downto 0) := (others => '0');
+ rdaddress : in std_logic_vector(g_adr_w - 1 downto 0) := (others => '0');
+ wraddress : in std_logic_vector(g_adr_w - 1 downto 0) := (others => '0');
+ wren : in std_logic := '0';
+ q : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_ram_r_w;
+
+architecture SYN of ip_agi027_xxxx_ram_r_w is
+ constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
+
+ component altera_syncram
+ generic (
+ address_aclr_b : string;
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_b : string;
+ init_file : string;
+ -- enable_force_to_zero : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_b : string;
+ -- outdata_sclr_b : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ -- read_during_write_mode_mixed_ports : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer
+ );
+ port (
+ address_a : in std_logic_vector(g_adr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_adr_w - 1 downto 0);
+ clock0 : in std_logic;
+ data_a : in std_logic_vector(g_dat_w - 1 downto 0);
+ wren_a : in std_logic;
+ q_b : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+ end component;
+
+ signal rdaddr : natural range 0 to g_nof_words - 1;
+ signal wraddr : natural range 0 to g_nof_words - 1;
+
+ signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
+ signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
+begin
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
+
+ gen_ip : if g_inferred = false generate
+ u_altera_syncram : altera_syncram
+ generic map (
+ address_aclr_b => "NONE",
+ address_reg_b => "CLOCK0",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ init_file => g_init_file,
+ -- enable_force_to_zero => "FALSE",
+ intended_device_family => "Agilex7",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words,
+ numwords_b => g_nof_words,
+ operation_mode => "DUAL_PORT",
+ outdata_aclr_b => "NONE",
+ -- outdata_sclr_b => "NONE",
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ -- read_during_write_mode_mixed_ports => "DONT_CARE",
+ widthad_a => g_adr_w,
+ widthad_b => g_adr_w,
+ width_a => g_dat_w,
+ width_b => g_dat_w,
+ width_byteena_a => 1
+ )
+ port map (
+ address_a => wraddress,
+ address_b => rdaddress,
+ clock0 => clk,
+ data_a => data,
+ wren_a => wren,
+ q_b => q
+ );
+ end generate;
+
+ gen_inferred : if g_inferred = true generate
+ rdaddr <= to_integer(unsigned(rdaddress));
+ wraddr <= to_integer(unsigned(wraddress));
+
+ u_mem : entity work.ip_agi027_xxxx_simple_dual_port_ram_single_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ clk => clk,
+ raddr => rdaddr,
+ waddr => wraddr,
+ data => data,
+ we => wren,
+ q => out_q
+ );
+
+ reg_q <= out_q when rising_edge(clk);
+
+ q <= out_q when g_rd_latency = 1 else reg_q;
+ end generate;
+
+end SYN;
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.ip b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.ip
new file mode 100644
index 0000000000000000000000000000000000000000..1b3be728cc1cac8887766843b7891780727484d1
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.ip
@@ -0,0 +1,1029 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_ram_rw_rw</ipxact:library>
+ <ipxact:name>ram_2port_0</ipxact:name>
+ <ipxact:version>20.4.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>data_a</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datain_a</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>data_a</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>q_a</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataout_a</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>q_a</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>data_b</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datain_b</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>data_b</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>q_b</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataout_b</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>q_b</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address_a</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address_a</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>address_a</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address_b</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address_b</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>address_b</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>wren_a</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wren_a</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wren_a</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>wren_b</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wren_b</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wren_b</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>ram_2port</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>data_a</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>q_a</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>data_b</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>q_b</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>address_a</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>address_b</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wren_a</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wren_b</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_ram_rw_rw</ipxact:library>
+ <ipxact:name>ram_2port</ipxact:name>
+ <ipxact:version>20.4.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device Family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MODE" type="int">
+ <ipxact:name>GUI_MODE</ipxact:name>
+ <ipxact:displayName>Operation Mode</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEM_IN_BITS" type="int">
+ <ipxact:name>GUI_MEM_IN_BITS</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEMSIZE_BITS" type="int">
+ <ipxact:name>GUI_MEMSIZE_BITS</ipxact:name>
+ <ipxact:displayName>How many bits of memory?</ipxact:displayName>
+ <ipxact:value>256</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MEMSIZE_WORDS" type="int">
+ <ipxact:name>GUI_MEMSIZE_WORDS</ipxact:name>
+ <ipxact:displayName>How many words of memory?</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_QA_WIDTH" type="int">
+ <ipxact:name>GUI_QA_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'q_a' output bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_QB_WIDTH" type="int">
+ <ipxact:name>GUI_QB_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'q_b' output bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DATAA_WIDTH" type="int">
+ <ipxact:name>GUI_DATAA_WIDTH</ipxact:name>
+ <ipxact:displayName>How wide should the 'data_a' input bus be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH" type="string">
+ <ipxact:name>GUI_MAX_DEPTH</ipxact:name>
+ <ipxact:displayName>Set the maximum block depth to</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_ECCENCPARITY" type="int">
+ <ipxact:name>GUI_WIDTH_ECCENCPARITY</ipxact:name>
+ <ipxact:displayName>Set the ecc enc parity width</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TBENCH" type="bit">
+ <ipxact:name>GUI_TBENCH</ipxact:name>
+ <ipxact:displayName>TESTING</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TDP_EMULATE" type="bit">
+ <ipxact:name>GUI_TDP_EMULATE</ipxact:name>
+ <ipxact:displayName>Emulate TDP dual clock mode</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_VAR_WIDTH" type="bit">
+ <ipxact:name>GUI_VAR_WIDTH</ipxact:name>
+ <ipxact:displayName>Use different data widths on different ports</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RAM_BLOCK_TYPE" type="string">
+ <ipxact:name>GUI_RAM_BLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>Ram Block Type</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LC_IMPLEMENTION_OPTIONS" type="int">
+ <ipxact:name>GUI_LC_IMPLEMENTION_OPTIONS</ipxact:name>
+ <ipxact:displayName>How should the memory be implemented?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_FILE_REFERENCE" type="int">
+ <ipxact:name>GUI_FILE_REFERENCE</ipxact:name>
+ <ipxact:displayName>Initialization File:</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_OPTIMIZATION_OPTION" type="int">
+ <ipxact:name>GUI_OPTIMIZATION_OPTION</ipxact:name>
+ <ipxact:displayName>Which timing/power optimization option do you want to use?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLOCK_TYPE" type="int">
+ <ipxact:name>GUI_CLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>Which clocking method do you want to use?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDEN_SINGLE" type="bit">
+ <ipxact:name>GUI_RDEN_SINGLE</ipxact:name>
+ <ipxact:displayName>Create a 'rden' read enable signal</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDEN_DOUBLE" type="bit">
+ <ipxact:name>GUI_RDEN_DOUBLE</ipxact:name>
+ <ipxact:displayName>Create 'rden_a' and 'rden_b' read enable signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_A" type="bit">
+ <ipxact:name>GUI_BYTE_ENABLE_A</ipxact:name>
+ <ipxact:displayName>Create byte enable for port A</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_B" type="bit">
+ <ipxact:name>GUI_BYTE_ENABLE_B</ipxact:name>
+ <ipxact:displayName>Create byte enable for port B</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_DOUBLE" type="bit">
+ <ipxact:name>GUI_ECC_DOUBLE</ipxact:name>
+ <ipxact:displayName>Enable Error Correction Check (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_TRIPLE" type="bit">
+ <ipxact:name>GUI_ECC_TRIPLE</ipxact:name>
+ <ipxact:displayName>Enable Error Correction Check (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECC_PIPELINE" type="bit">
+ <ipxact:name>GUI_ECC_PIPELINE</ipxact:name>
+ <ipxact:displayName>Enable ECC Pipeline Registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ECCENCBYPASS" type="bit">
+ <ipxact:name>GUI_ECCENCBYPASS</ipxact:name>
+ <ipxact:displayName>Enable ECC Encoder Bypass</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_COHERENT_READ" type="bit">
+ <ipxact:name>GUI_COHERENT_READ</ipxact:name>
+ <ipxact:displayName>Enable Coherent Read</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_FORCE_TO_ZERO" type="bit">
+ <ipxact:name>GUI_FORCE_TO_ZERO</ipxact:name>
+ <ipxact:displayName>Enable Force To Zero</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_PR" type="bit">
+ <ipxact:name>GUI_PR</ipxact:name>
+ <ipxact:displayName>Implement clock-enable circuitry for use in a partial reconfiguration region</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BYTE_ENABLE_WIDTH" type="int">
+ <ipxact:name>GUI_BYTE_ENABLE_WIDTH</ipxact:name>
+ <ipxact:displayName>What is the width of a byte for byte enables?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WRITE_INPUT_PORTS" type="bit">
+ <ipxact:name>GUI_WRITE_INPUT_PORTS</ipxact:name>
+ <ipxact:displayName>All write input ports</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_INPUT_RDADDRESS" type="bit">
+ <ipxact:name>GUI_READ_INPUT_RDADDRESS</ipxact:name>
+ <ipxact:displayName>rdaddress port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DIFFERENT_CLKENS" type="bit">
+ <ipxact:name>GUI_DIFFERENT_CLKENS</ipxact:name>
+ <ipxact:displayName>Use different clock enables for registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_WRITE_INPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_WRITE_INPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for write input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_READ_INPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_READ_INPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for read input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_READ_OUTPUT_REG" type="bit">
+ <ipxact:name>GUI_CLKEN_READ_OUTPUT_REG</ipxact:name>
+ <ipxact:displayName>Use clock enable for output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_INPUT_REG_A" type="bit">
+ <ipxact:name>GUI_CLKEN_INPUT_REG_A</ipxact:name>
+ <ipxact:displayName>Use clock enable for port A input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_INPUT_REG_B" type="bit">
+ <ipxact:name>GUI_CLKEN_INPUT_REG_B</ipxact:name>
+ <ipxact:displayName>Use clock enable for port B input registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_OUTPUT_REG_A" type="bit">
+ <ipxact:name>GUI_CLKEN_OUTPUT_REG_A</ipxact:name>
+ <ipxact:displayName>Use clock enable for port A output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_OUTPUT_REG_B" type="bit">
+ <ipxact:name>GUI_CLKEN_OUTPUT_REG_B</ipxact:name>
+ <ipxact:displayName>Use clock enable for port B output registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_ADDRESS_STALL_A" type="bit">
+ <ipxact:name>GUI_CLKEN_ADDRESS_STALL_A</ipxact:name>
+ <ipxact:displayName>Create an addressstall_a input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_ADDRESS_STALL_B" type="bit">
+ <ipxact:name>GUI_CLKEN_ADDRESS_STALL_B</ipxact:name>
+ <ipxact:displayName>Create an addressstall_b input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_WRADDRESSSTALL" type="bit">
+ <ipxact:name>GUI_CLKEN_WRADDRESSSTALL</ipxact:name>
+ <ipxact:displayName>Create an wr_addressstall input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN_RDADDRESSSTALL" type="bit">
+ <ipxact:name>GUI_CLKEN_RDADDRESSSTALL</ipxact:name>
+ <ipxact:displayName>Create an rd_addressstall input port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_INPUT_RDADDRESS" type="bit">
+ <ipxact:name>GUI_ACLR_READ_INPUT_RDADDRESS</ipxact:name>
+ <ipxact:displayName>rdaddress port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_ACLR_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ACLR_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_ACLR_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SCLR_READ_OUTPUT_QA" type="bit">
+ <ipxact:name>GUI_SCLR_READ_OUTPUT_QA</ipxact:name>
+ <ipxact:displayName>q_a port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SCLR_READ_OUTPUT_QB" type="bit">
+ <ipxact:name>GUI_SCLR_READ_OUTPUT_QB</ipxact:name>
+ <ipxact:displayName>q_b port</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Q_PORT_MODE" type="int">
+ <ipxact:name>GUI_Q_PORT_MODE</ipxact:name>
+ <ipxact:displayName><html>How should the q_a and q_b outputs behave when reading a memory location<br>that is being written from the other port?</html></ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CONSTRAINED_DONT_CARE" type="bit">
+ <ipxact:name>GUI_CONSTRAINED_DONT_CARE</ipxact:name>
+ <ipxact:displayName><html>Do not analyze the timing between write and read operation. Metastabillity issues are<br>prevented by never writing and reading at the same address at the same time.</html></ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDW_A_MODE" type="string">
+ <ipxact:name>GUI_RDW_A_MODE</ipxact:name>
+ <ipxact:displayName>What should the q_a output be when reading from a memory location being written to?</ipxact:displayName>
+ <ipxact:value>New Data</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RDW_B_MODE" type="string">
+ <ipxact:name>GUI_RDW_B_MODE</ipxact:name>
+ <ipxact:displayName>What should the q_b output be when reading from a memory location being written to?</ipxact:displayName>
+ <ipxact:value>New Data</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_NBE_A" type="bit">
+ <ipxact:name>GUI_NBE_A</ipxact:name>
+ <ipxact:displayName>Get x's for write masked bytes instead of old data when byte enable is used</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_NBE_B" type="bit">
+ <ipxact:name>GUI_NBE_B</ipxact:name>
+ <ipxact:displayName>Get x's for write masked bytes instead of old data when byte enable is used</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_BLANK_MEMORY" type="int">
+ <ipxact:name>GUI_BLANK_MEMORY</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_INIT_FILE_LAYOUT" type="string">
+ <ipxact:name>GUI_INIT_FILE_LAYOUT</ipxact:name>
+ <ipxact:displayName>The initial content file should conform to which port's dimensions?</ipxact:displayName>
+ <ipxact:value>PORT_B</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_INIT_SIM_TO_X" type="bit">
+ <ipxact:name>GUI_INIT_SIM_TO_X</ipxact:name>
+ <ipxact:displayName>Initialize memory content data to XX..X on power-up in simulation</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MIF_FILENAME" type="string">
+ <ipxact:name>GUI_MIF_FILENAME</ipxact:name>
+ <ipxact:displayName>File name</ipxact:displayName>
+ <ipxact:value>./ram_1024.hex</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address_a" altera:internal="ram_2port_0.address_a" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="address_a" altera:internal="address_a"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="address_b" altera:internal="ram_2port_0.address_b" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="address_b" altera:internal="address_b"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock" altera:internal="ram_2port_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock_a" altera:internal="ram_2port_0.clock_a"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock_b" altera:internal="ram_2port_0.clock_b"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="data" altera:internal="ram_2port_0.data"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="data_a" altera:internal="ram_2port_0.data_a" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="data_a" altera:internal="data_a"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="data_b" altera:internal="ram_2port_0.data_b" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="data_b" altera:internal="data_b"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="inclock" altera:internal="ram_2port_0.inclock"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="outclock" altera:internal="ram_2port_0.outclock"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="q" altera:internal="ram_2port_0.q"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="q_a" altera:internal="ram_2port_0.q_a" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="q_a" altera:internal="q_a"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="q_b" altera:internal="ram_2port_0.q_b" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="q_b" altera:internal="q_b"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rdaddress" altera:internal="ram_2port_0.rdaddress"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="valid" altera:internal="ram_2port_0.valid"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="wraddress" altera:internal="ram_2port_0.wraddress"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="wren" altera:internal="ram_2port_0.wren"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="wren_a" altera:internal="ram_2port_0.wren_a" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="wren_a" altera:internal="wren_a"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="wren_b" altera:internal="ram_2port_0.wren_b" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="wren_b" altera:internal="wren_b"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a7e4463718d05eefd97377c54659dbf80adc0f52
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd
@@ -0,0 +1,197 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper / Instantiate RAM IP with generics
+-- Description:
+-- Copied component declaration and instance example from
+-- generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_rw_rw_ram_2port_2040_uxwhvmq.vhd
+-- Remark:
+-- The outcome of the synthesis is that the parameter
+-- read_during_write_mode_mixed_ports cannot be set to the
+-- value OLD_DATA for the Agilex 7, otherwise an error occurs.
+
+library ieee, technology_lib;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use technology_lib.technology_pkg.all;
+
+library altera_lnsim;
+use altera_lnsim.altera_lnsim_components.all;
+
+entity ip_agi027_xxxx_ram_rw_rw is
+ generic (
+ g_inferred : boolean := false;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port (
+ address_a : in std_logic_vector(g_adr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_adr_w - 1 downto 0);
+ clk : in std_logic := '1';
+ data_a : in std_logic_vector(g_dat_w - 1 downto 0);
+ data_b : in std_logic_vector(g_dat_w - 1 downto 0);
+ wren_a : in std_logic := '0';
+ wren_b : in std_logic := '0';
+ q_a : out std_logic_vector(g_dat_w - 1 downto 0);
+ q_b : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_ram_rw_rw;
+
+architecture SYN of ip_agi027_xxxx_ram_rw_rw is
+ constant c_outdata_reg : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
+
+ component altera_syncram
+ generic (
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_a : string;
+ clock_enable_output_b : string;
+ indata_reg_b : string;
+ init_file : string;
+ -- enable_force_to_zero : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_a : string;
+ -- outdata_sclr_a : string;
+ outdata_aclr_b : string;
+ -- outdata_sclr_b : string;
+ outdata_reg_a : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ read_during_write_mode_port_a : string;
+ read_during_write_mode_port_b : string;
+ read_during_write_mode_mixed_ports : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer;
+ width_byteena_b : integer
+ );
+ port (
+ address_a : in std_logic_vector(g_adr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_adr_w - 1 downto 0);
+ clock0 : in std_logic;
+ data_a : in std_logic_vector(g_dat_w - 1 downto 0);
+ data_b : in std_logic_vector(g_dat_w - 1 downto 0);
+ wren_a : in std_logic;
+ wren_b : in std_logic;
+ q_a : out std_logic_vector(g_dat_w - 1 downto 0);
+ q_b : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+ end component;
+
+ -- Is used for gen_inferred:
+ signal addr_a : natural range 0 to g_nof_words - 1;
+ signal addr_b : natural range 0 to g_nof_words - 1;
+
+ signal out_a : std_logic_vector(g_dat_w - 1 downto 0);
+ signal out_b : std_logic_vector(g_dat_w - 1 downto 0);
+
+ signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
+ signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
+begin
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_rw_rw : read latency must be 1 (default) or 2" severity FAILURE;
+
+ gen_ip : if g_inferred = false generate
+ u_altera_syncram : altera_syncram
+ generic map (
+ address_reg_b => "CLOCK0",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_a => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ indata_reg_b => "CLOCK0",
+ init_file => g_init_file,
+ --enable_force_to_zero => "FALSE",
+ intended_device_family => "Agilex 7",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words,
+ numwords_b => g_nof_words,
+ operation_mode => "BIDIR_DUAL_PORT",
+ outdata_aclr_a => "NONE",
+ --outdata_sclr_a => "NONE",
+ outdata_aclr_b => "NONE",
+ --outdata_sclr_b => "NONE",
+ outdata_reg_a => c_outdata_reg,
+ outdata_reg_b => c_outdata_reg,
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ widthad_a => g_adr_w,
+ widthad_b => g_adr_w,
+ width_a => g_dat_w,
+ width_b => g_dat_w,
+ width_byteena_a => 1,
+ width_byteena_b => 1
+ )
+ port map (
+ address_a => address_a,
+ address_b => address_b,
+ clock0 => clk,
+ data_a => data_a,
+ data_b => data_b,
+ wren_a => wren_a,
+ wren_b => wren_b,
+ q_a => q_a,
+ q_b => q_b
+ );
+
+ end generate;
+
+ gen_inferred : if g_inferred = true generate
+ addr_a <= to_integer(unsigned(address_a));
+ addr_b <= to_integer(unsigned(address_b));
+
+ u_mem : entity work.ip_agi027_xxxx_true_dual_port_ram_single_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ clk => clk,
+ addr_a => addr_a,
+ addr_b => addr_b,
+ data_a => data_a,
+ data_b => data_b,
+ we_a => wren_a,
+ we_b => wren_b,
+ q_a => out_a,
+ q_b => out_b
+ );
+
+ reg_a <= out_a when rising_edge(clk);
+ reg_b <= out_b when rising_edge(clk);
+
+ q_a <= out_a when g_rd_latency = 1 else reg_a;
+ q_b <= out_b when g_rd_latency = 1 else reg_b;
+ end generate;
+
+end SYN;
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..492bd615d86af378464405b6ec36c308fd09030a
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd
@@ -0,0 +1,78 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper
+-- Description:
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses and
+-- different read/write clock
+-- Reference:
+-- Copied from ip_arria10_e2sg/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd
+-- and the inferred Altera code was obtained using template insert with
+-- Quartus 14.0a10.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+ port
+ (
+ rclk : in std_logic;
+ wclk : in std_logic;
+ raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ data : in std_logic_vector((DATA_WIDTH - 1) downto 0);
+ we : in std_logic := '1';
+ q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
+ );
+end ip_agi027_xxxx_simple_dual_port_ram_dual_clock;
+
+architecture rtl of ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
+ -- Build a 2-D array type for the RAM
+ subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
+ type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
+
+ -- Declare the RAM signal.
+ signal ram : memory_t;
+begin
+ process(wclk)
+ begin
+ if(rising_edge(wclk)) then
+ if(we = '1') then
+ ram(waddr) <= data;
+ end if;
+ end if;
+ end process;
+
+ process(rclk)
+ begin
+ if(rising_edge(rclk)) then
+ q <= ram(raddr);
+ end if;
+ end process;
+end rtl;
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e2fa5f8cfadf48162970e56436d358a32f563d61
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd
@@ -0,0 +1,74 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper
+-- Description:
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses but
+-- single read/write clock
+-- Reference:
+-- Copied from ip_arria10_e2sg/ip_arria10_e2sg_simple_dual_port_ram_simple_clock.vhd
+-- and the inferred Altera code was obtained using template insert with
+-- Quartus 14.0a10.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_agi027_xxxx_simple_dual_port_ram_single_clock is
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+ port
+ (
+ clk : in std_logic;
+ raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ data : in std_logic_vector((DATA_WIDTH - 1) downto 0);
+ we : in std_logic := '1';
+ q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
+ );
+end ip_agi027_xxxx_simple_dual_port_ram_single_clock;
+
+architecture rtl of ip_agi027_xxxx_simple_dual_port_ram_single_clock is
+ -- Build a 2-D array type for the RAM
+ subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
+ type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
+
+ -- Declare the RAM signal.
+ signal ram : memory_t;
+begin
+ process(clk)
+ begin
+ if(rising_edge(clk)) then
+ if(we = '1') then
+ ram(waddr) <= data;
+ end if;
+
+ -- On a read during a write to the same address, the read will
+ -- return the OLD data at the address
+ q <= ram(raddr);
+ end if;
+ end process;
+end rtl;
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d4386f2595cb2d37946e4b53359adf8cd7fedd1a
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd
@@ -0,0 +1,84 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper
+-- Description:
+-- Quartus II VHDL Template
+-- True Dual-Port RAM with single clock
+-- Read-during-write on port A or B returns newly written data
+-- Read-during-write on port A and B returns unknown data.
+-- Reference:
+-- Copied from ip_arria10_e2sg/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd
+-- and the inferred Altera code was obtained using template insert with
+-- Quartus 14.0a10.
+-- Remark:
+-- The orignal file is for True Dual-Port RAM with dual clock. However, that is
+-- not supported by the Agilex 7 in the way it is used before Agilex 7.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_agi027_xxxx_true_dual_port_ram_single_clock is
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+ port
+ (
+ clk : in std_logic;
+ addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;
+ addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;
+ data_a : in std_logic_vector((DATA_WIDTH - 1) downto 0);
+ data_b : in std_logic_vector((DATA_WIDTH - 1) downto 0);
+ we_a : in std_logic := '1';
+ we_b : in std_logic := '1';
+ q_a : out std_logic_vector((DATA_WIDTH - 1) downto 0);
+ q_b : out std_logic_vector((DATA_WIDTH - 1) downto 0)
+ );
+end ip_agi027_xxxx_true_dual_port_ram_single_clock;
+
+architecture rtl of ip_agi027_xxxx_true_dual_port_ram_single_clock is
+ -- Build a 2-D array type for the RAM
+ subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
+ type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
+
+ -- Declare the RAM
+ shared variable ram : memory_t;
+begin
+ process(clk)
+ begin
+ if(rising_edge(clk)) then
+ -- Port A
+ if(we_a = '1') then
+ ram(addr_a) := data_a;
+ end if;
+ q_a <= ram(addr_a);
+ -- Port B
+ if(we_b = '1') then
+ ram(addr_b) := data_b;
+ end if;
+ q_b <= ram(addr_b);
+ end if;
+ end process;
+end rtl;
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index 03824a363bbc29eb63f0ed759b60007b6088ec50..bd0e7b218f363323e76d83d4f0fb4e9335786c17 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram ip_ultrascale_ram
+hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram ip_ultrascale_ram ip_agi027_xxxx_ram
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -10,13 +10,16 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_ram ip_arria10_e1sg_ram_lib
ip_arria10_e2sg_ram ip_arria10_e2sg_ram_lib
ip_ultrascale_ram ip_ultrascale_ram_lib
+ ip_agi027_xxxx_ram ip_agi027_xxxx_ram_lib
synth_files =
tech_memory_component_pkg.vhd
tech_memory_ram_cr_cw.vhd
+ tech_memory_ram_crk_cw.vhd
tech_memory_ram_crw_crw.vhd
tech_memory_ram_crwk_crw.vhd
tech_memory_ram_r_w.vhd
+ tech_memory_ram_rw_rw.vhd
tech_memory_rom_r.vhd
test_bench_files =
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index a2de0b573e79790ebdd1d71961f46a410dd4a776..e28370e31bc44afcd046c33a30ef752f8f1520b3 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -1,25 +1,27 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
-
--- Purpose: IP components declarations for various devices that get wrapped by the tech components
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Purpose:
+-- IP components declarations for various devices that get wrapped by the tech components
library IEEE;
use IEEE.std_logic_1164.all;
@@ -562,4 +564,98 @@ package tech_memory_component_pkg is
);
end component;
+ -----------------------------------------------------------------------------
+ -- ip_agi027_xxxx
+ -----------------------------------------------------------------------------
+
+ -- components ip_agi027_xxxx_ram_crwk_crw and ip_agi027_xxxx_ram_crw_crw are
+ -- not available for the Agilex 7. For more details please refer the
+ -- README.txt in the technology/ip_agi027_xxxx/ram/ folder.
+
+ component ip_agi027_xxxx_ram_cr_cw is
+ generic (
+ g_inferred : boolean := false;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port
+ (
+ data : in std_logic_vector(g_dat_w - 1 downto 0);
+ rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
+ rdclk : in std_logic;
+ wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
+ wrclk : in std_logic := '1';
+ wren : in std_logic := '0';
+ q : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_ram_crk_cw is
+ generic (
+ g_wr_adr_w : natural := 5;
+ g_wr_dat_w : natural := 32;
+ g_wr_nof_words : natural := 2**5;
+ g_rd_adr_w : natural := 4;
+ g_rd_dat_w : natural := 64;
+ g_rd_nof_words : natural := 2**4;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port
+ (
+ data : in std_logic_vector(g_wr_dat_w - 1 downto 0);
+ wraddress : in std_logic_vector(g_wr_adr_w - 1 downto 0);
+ wrclk : in std_logic := '1';
+ wren : in std_logic := '0';
+ rdaddress : in std_logic_vector(g_rd_adr_w - 1 downto 0);
+ rdclk : in std_logic;
+ q : out std_logic_vector(g_rd_dat_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_ram_rw_rw is
+ generic (
+ g_inferred : boolean := false;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port
+ (
+ address_a : in std_logic_vector(g_adr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_adr_w - 1 downto 0);
+ clk : in std_logic := '1';
+ data_a : in std_logic_vector(g_dat_w - 1 downto 0);
+ data_b : in std_logic_vector(g_dat_w - 1 downto 0);
+ wren_a : in std_logic := '0';
+ wren_b : in std_logic := '0';
+ q_a : out std_logic_vector(g_dat_w - 1 downto 0);
+ q_b : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_ram_r_w is
+ generic (
+ g_inferred : boolean := false;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port (
+ clk : in std_logic := '1';
+ data : in std_logic_vector(g_dat_w - 1 downto 0) := (others => '0');
+ rdaddress : in std_logic_vector(g_adr_w - 1 downto 0) := (others => '0');
+ wraddress : in std_logic_vector(g_adr_w - 1 downto 0) := (others => '0');
+ wren : in std_logic := '0';
+ q : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+ end component;
+
end tech_memory_component_pkg;
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 2fd68899ece51f43682353bea2de033a4cc93344..7ced5b5d579275df9abc0326fddca367cd9769b0 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -32,6 +34,7 @@ library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
library ip_ultrascale_ram_lib;
+library ip_agi027_xxxx_ram_lib;
entity tech_memory_ram_cr_cw is
generic (
@@ -94,4 +97,10 @@ begin
port map (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
end generate;
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_ram_cr_cw
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
+ end generate;
+
end architecture;
diff --git a/libraries/technology/memory/tech_memory_ram_crk_cw.vhd b/libraries/technology/memory/tech_memory_ram_crk_cw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4b691e0e805c73a5204590091f9394e68f4763f7
--- /dev/null
+++ b/libraries/technology/memory/tech_memory_ram_crk_cw.vhd
@@ -0,0 +1,115 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- D.F. Brouwer
+-- Remark:
+-- Due to the lack of support by the Agilex 7 (agi027_xxxx) for the crwk_crw
+-- IP as used for previous FPGA technology identifiers (device types), the
+-- crk_cw IP has been created and is available for use. For the previous
+-- technology identifiers, it is constructed using the crwk_crw IPs. For more
+-- details please refer the README.txt in the ip_agi027_xxxx/ram/ folder.
+-- Reference:
+-- Based on tech_memory_ram_crwk_crw.vhd and tech_memory_ram_cr_cw.vhd.
+-- Changed the generics and ports to common_ram_cr_cw_ratio.vhd and
+-- ip_agi027_ram_crk_cw.vhd. These changes have been incorporated into the
+-- existing generate-blocks and the generate-block for agi_xxxx is added.
+
+library ieee, technology_lib;
+use ieee.std_logic_1164.all;
+use work.tech_memory_component_pkg.all;
+use technology_lib.technology_pkg.all;
+use technology_lib.technology_select_pkg.all;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+library ip_stratixiv_ram_lib;
+library ip_arria10_ram_lib;
+library ip_arria10_e3sge3_ram_lib;
+library ip_arria10_e1sg_ram_lib;
+library ip_arria10_e2sg_ram_lib;
+library ip_agi027_xxxx_ram_lib;
+
+entity tech_memory_ram_crk_cw is -- support different port data widths and corresponding address ranges
+ generic (
+ g_technology : natural := c_tech_select_default;
+ g_wr_adr_w : natural := 5;
+ g_wr_dat_w : natural := 32;
+ g_rd_adr_w : natural := 7;
+ g_rd_dat_w : natural := 8;
+ g_wr_nof_words : natural := 2**5;
+ g_rd_nof_words : natural := 2**7;
+ g_rd_latency : natural := 2; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port
+ (
+ wraddress : in std_logic_vector(g_wr_adr_w - 1 downto 0);
+ wrclock : in std_logic := '1';
+ rdaddress : in std_logic_vector(g_rd_adr_w - 1 downto 0);
+ rdclock : in std_logic;
+ data : in std_logic_vector(g_wr_dat_w - 1 downto 0);
+ wrclocken : in std_logic := '1';
+ rdclocken : in std_logic := '1';
+ rden_a : in std_logic := '1';
+ rden_b : in std_logic := '1';
+ wren : in std_logic := '0';
+ q : out std_logic_vector(g_rd_dat_w - 1 downto 0)
+ );
+end tech_memory_ram_crk_cw;
+
+architecture str of tech_memory_ram_crk_cw is
+begin
+ gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
+ u0 : ip_stratixiv_ram_crwk_crw
+ generic map (g_wr_adr_w, g_wr_dat_w, g_rd_adr_w, g_rd_dat_w, g_wr_nof_words, g_rd_nof_words, g_rd_latency, g_init_file)
+ port map (wraddress, rdaddress, wrclock, rdclock, data, (others => '0'), wrclocken, rdclocken, rden_a, rden_b, wren, '0', OPEN, q);
+ end generate;
+
+ gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
+ u0 : ip_arria10_ram_crwk_crw
+ generic map (g_wr_adr_w, g_wr_dat_w, g_rd_adr_w, g_rd_dat_w, g_wr_nof_words, g_rd_nof_words, g_rd_latency, g_init_file)
+ port map (wraddress, rdaddress, wrclock, rdclock, data, (others => '0'), wren, '0', OPEN, q);
+ end generate;
+
+ gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 generate
+ u0 : ip_arria10_e3sge3_ram_crwk_crw
+ generic map (g_wr_adr_w, g_wr_dat_w, g_rd_adr_w, g_rd_dat_w, g_wr_nof_words, g_rd_nof_words, g_rd_latency, g_init_file)
+ port map (wraddress, rdaddress, wrclock, rdclock, data, (others => '0'), wren, '0', OPEN, q);
+ end generate;
+
+ gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
+ u0 : ip_arria10_e1sg_ram_crwk_crw
+ generic map (g_wr_adr_w, g_wr_dat_w, g_rd_adr_w, g_rd_dat_w, g_wr_nof_words, g_rd_nof_words, g_rd_latency, g_init_file)
+ port map (wraddress, rdaddress, wrclock, rdclock, data, (others => '0'), wren, '0', OPEN, q);
+ end generate;
+
+ gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg generate
+ u0 : ip_arria10_e2sg_ram_crwk_crw
+ generic map (g_wr_adr_w, g_wr_dat_w, g_rd_adr_w, g_rd_dat_w, g_wr_nof_words, g_rd_nof_words, g_rd_latency, g_init_file)
+ port map (wraddress, rdaddress, wrclock, rdclock, data, (others => '0'), wren, '0', OPEN, q);
+ end generate;
+
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_ram_crk_cw
+ generic map (g_wr_adr_w, g_wr_dat_w, g_wr_nof_words, g_rd_adr_w, g_rd_dat_w, g_rd_nof_words, g_rd_latency, g_init_file)
+ port map (data, wraddress, wrclock, wren, rdaddress, rdclock, q);
+ end generate;
+
+end architecture;
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 2707c1f2c1eaafb54bac3bb7dcc3ffb6c1c4c016..da074de765d37fe657eaa8327b07961d09f8f503 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -1,23 +1,33 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Remark:
+-- . The Agilex 7 (agi027_xxxx) doesn't support this IP as used for previous
+-- FPGA technology identifiers (device types). Instead, the rw_rw IP should
+-- be used. For previous technology identifiers, it is constructed using
+-- this crw_crw IP by providing the same clock twice. For more details
+-- please refer the README.txt in the ip_agi027_xxxx/ram/ folder.
+-- . For Agilex 7 (agi027_xxxx) is also the ip_agi027_xxxx_ram_rw_rw added
+-- to this package, but it is only supporting clock_b.
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -32,6 +42,7 @@ library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
library ip_ultrascale_ram_lib;
+library ip_agi027_xxxx_ram_lib;
entity tech_memory_ram_crw_crw is
generic (
@@ -99,4 +110,10 @@ begin
port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_ram_rw_rw
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
end architecture;
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index e226457910ea323fc3019f5c79ccf17244913736..63e993d3310ae6c7f2b67047767850d05f27a11d 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -1,23 +1,31 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Remark:
+-- The Agilex 7 (agi027_xxxx) doesn't support this IP as used for previous
+-- FPGA technology identifiers (device types), and unfortunately, the rwk_rw
+-- IP variant isn't supported either. Instead, the crk_cw IP can be created
+-- when necessary. For more details please refer the README.txt in the
+-- ip_agi027_xxxx/ram/ folder.
library ieee, technology_lib;
use ieee.std_logic_1164.all;
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 7bf868a390b42ebb1a0cb8f91b030a0c90e3a7b1..67780aa4b1878481458963b4ffeb47a5deff0cd4 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -31,6 +33,7 @@ library ip_arria10_ram_lib;
library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
+library ip_agi027_xxxx_ram_lib;
entity tech_memory_ram_r_w is
generic (
@@ -38,6 +41,7 @@ entity tech_memory_ram_r_w is
g_adr_w : natural := 5;
g_dat_w : natural := 8;
g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
g_init_file : string := "UNUSED"
);
port (
@@ -61,25 +65,31 @@ begin
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_ram_r_w
- generic map (false, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
port map (clock, data, rdaddress, wraddress, wren, q);
end generate;
gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 generate
u0 : ip_arria10_e3sge3_ram_r_w
- generic map (false, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
port map (clock, data, rdaddress, wraddress, wren, q);
end generate;
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
u0 : ip_arria10_e1sg_ram_r_w
- generic map (false, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
port map (clock, data, rdaddress, wraddress, wren, q);
end generate;
gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg generate
u0 : ip_arria10_e2sg_ram_r_w
- generic map (false, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (clock, data, rdaddress, wraddress, wren, q);
+ end generate;
+
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_ram_r_w
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
port map (clock, data, rdaddress, wraddress, wren, q);
end generate;
diff --git a/libraries/technology/memory/tech_memory_ram_rw_rw.vhd b/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6b692b5e07de8c9a2d77da51807626bbe61b71a2
--- /dev/null
+++ b/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
@@ -0,0 +1,120 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author:
+-- D.F. Brouwer
+-- Remark:
+-- Because the crw_crw IP isn't supported as used for previous FPGA
+-- technology identifiers (device types) by the Agilex 7 (agi027_xxxx), the
+-- rw_rw IP should be used. For the previous technology identifiers, it is
+-- constructed using the crw_crw IPs by providing the same clock twice. For
+-- more details please refer the README.txt in the ip_agi027_xxxx/ram/ folder.
+-- Reference:
+-- Copied from tech_memory_ram_crw_crw.vhd and combined two enable entity
+-- ports to one and two clock entity ports to one. These changes have been
+-- incorporated into the existing generate-blocks and the generate-block
+-- for agi_xxxx is added.
+
+library ieee, technology_lib;
+use ieee.std_logic_1164.all;
+use work.tech_memory_component_pkg.all;
+use technology_lib.technology_pkg.all;
+use technology_lib.technology_select_pkg.all;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+library ip_stratixiv_ram_lib;
+library ip_arria10_ram_lib;
+library ip_arria10_e3sge3_ram_lib;
+library ip_arria10_e1sg_ram_lib;
+library ip_arria10_e2sg_ram_lib;
+library ip_ultrascale_ram_lib;
+library ip_agi027_xxxx_ram_lib;
+
+entity tech_memory_ram_rw_rw is
+ generic (
+ g_technology : natural := c_tech_select_default;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 2; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port
+ (
+ address_a : in std_logic_vector(g_adr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_adr_w - 1 downto 0);
+ clock : in std_logic := '1';
+ data_a : in std_logic_vector(g_dat_w - 1 downto 0);
+ data_b : in std_logic_vector(g_dat_w - 1 downto 0);
+ enable : in std_logic := '1';
+ rden_a : in std_logic := '1';
+ rden_b : in std_logic := '1';
+ wren_a : in std_logic := '0';
+ wren_b : in std_logic := '0';
+ q_a : out std_logic_vector(g_dat_w - 1 downto 0);
+ q_b : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+end tech_memory_ram_rw_rw;
+
+architecture str of tech_memory_ram_rw_rw is
+begin
+ gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
+ u0 : ip_stratixiv_ram_crw_crw
+ generic map (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock, clock, data_a, data_b, enable, enable, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
+ gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
+ u0 : ip_arria10_ram_crw_crw
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock, clock, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
+ gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 generate
+ u0 : ip_arria10_e3sge3_ram_crw_crw
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock, clock, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
+ gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
+ u0 : ip_arria10_e1sg_ram_crw_crw
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock, clock, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
+ gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg generate
+ u0 : ip_arria10_e2sg_ram_crw_crw
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock, clock, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
+ gen_ip_ultrascale : if g_technology = c_tech_ultrascale generate
+ u0 : ip_ultrascale_ram_crw_crw
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock, clock, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_ram_rw_rw
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
+end architecture;
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 792942f7619813a6d5e3d35c6f38ca7c9ebcd02d..6382556de3ea1c656ca50e0a2dedc986c6cdc656 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -31,6 +33,7 @@ library ip_arria10_ram_lib;
library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
+library ip_agi027_xxxx_ram_lib;
entity tech_memory_rom_r is
generic (
@@ -99,7 +102,7 @@ begin
end generate;
gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg generate
- -- use ip_arria10_e1sg_ram_r_w as ROM
+ -- use ip_arria10_e2sg_ram_r_w as ROM
u0 : ip_arria10_e2sg_ram_r_w
generic map (false, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
port map (
@@ -112,4 +115,18 @@ begin
);
end generate;
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ -- use ip_agi027_xxxx_ram_r_w as ROM
+ u0 : ip_agi027_xxxx_ram_r_w
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ port map (
+ clk => clock,
+ --data => ,
+ rdaddress => address,
+ --wraddress => ,
+ --wren => ,
+ q => q
+ );
+ end generate;
+
end architecture;