From 5c62b3e8cd272a6e6f45bf4680608307bf4f4835 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 20 Jan 2015 14:51:39 +0000
Subject: [PATCH] Pass on g_delay_len => g_cross_domain_delay_len.
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index c2089066dc..63bff7f5db 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -154,6 +154,7 @@ ENTITY io_ddr IS
g_tech_ddr : t_c_tech_ddr;
g_sim : BOOLEAN := FALSE; -- when TRUE use internal DDR memory model
g_cross_domain_dvr_ctlr : BOOLEAN := TRUE;
+ g_cross_domain_delay_len : NATURAL := c_meta_delay_len;
g_wr_data_w : NATURAL := 32;
g_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
g_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
@@ -248,7 +249,8 @@ BEGIN
u_io_ddr_cross_domain : ENTITY work.io_ddr_cross_domain
GENERIC MAP (
- g_cross_domain => g_cross_domain_dvr_ctlr
+ g_cross_domain => g_cross_domain_dvr_ctlr,
+ g_delay_len => g_cross_domain_delay_len
)
PORT MAP(
-- Driver clock domain
--
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