From 5c46451f01db83b086a282670950b753b4469d84 Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Wed, 9 Sep 2020 16:07:15 +0200 Subject: [PATCH] Added altera libraries for jesd204b simulation --- .../altera_jesd204_180/compile_ip.tcl | 42 ++++++++++++++++ .../altera_jesd204_180/hdllib.cfg | 17 +++++++ .../altera_jesd204_phy_180/compile_ip.tcl | 40 +++++++++++++++ .../altera_jesd204_phy_180/hdllib.cfg | 17 +++++++ .../compile_ip.tcl | 36 +++++++++++++ .../hdllib.cfg | 17 +++++++ .../altera_jesd204_rx_180/compile_ip.tcl | 50 +++++++++++++++++++ .../altera_jesd204_rx_180/hdllib.cfg | 17 +++++++ .../compile_ip.tcl | 43 ++++++++++++++++ .../altera_jesd204_rx_mlpcs_180/hdllib.cfg | 17 +++++++ .../altera_jesd204_tx_180/compile_ip.tcl | 45 +++++++++++++++++ .../altera_jesd204_tx_180/hdllib.cfg | 17 +++++++ .../compile_ip.tcl | 42 ++++++++++++++++ .../altera_jesd204_tx_mlpcs_180/hdllib.cfg | 17 +++++++ .../altera_reset_sequencer_180/compile_ip.tcl | 44 ++++++++++++++++ .../altera_reset_sequencer_180/hdllib.cfg | 16 ++++++ .../ip_arria10_e1sg/jesd204b/hdllib.cfg | 3 +- 17 files changed, 478 insertions(+), 2 deletions(-) create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl new file mode 100644 index 0000000000..602606e9ca --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl @@ -0,0 +1,42 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_jesd204_180 ./work/ + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim" + vcom "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_rx_altera_jesd204_180_3rumeui.vhd" -work altera_jesd204_180 + + + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim" + vcom "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_jesd204_180_too2kia.vhd" -work altera_jesd204_180 + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg new file mode 100644 index 0000000000..fe8c51f3dd --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_jesd204_180 +hdl_library_clause_name = altera_jesd204_180 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_phy_180 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl new file mode 100644 index 0000000000..dfe1bc251d --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_jesd204_phy_180 ./work/ + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim" + vcom "$IP_DIR/../altera_jesd204_phy_180/sim/ip_arria10_e1sg_jesd204b_rx_altera_jesd204_phy_180_wv3zwea.vhd" -work altera_jesd204_phy_180 + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim" + vcom "$IP_DIR/../altera_jesd204_phy_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_jesd204_phy_180_s336zrq.vhd" -work altera_jesd204_phy_180 + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg new file mode 100644 index 0000000000..fccfb8daff --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_jesd204_phy_180 +hdl_library_clause_name = altera_jesd204_phy_180 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_rx_180 ip_arria10_e1sg_altera_jesd204_tx_180 ip_arria10_e1sg_altera_jesd204_phy_adapter_xs_180 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl new file mode 100644 index 0000000000..b79cb4af76 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl @@ -0,0 +1,36 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_jesd204_phy_adapter_xs_180 ./work/ + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim" + + vlog "$IP_DIR/../altera_jesd204_phy_adapter_xs_180/sim/mentor/altera_jesd204_phy_adapter_xs.v" -work altera_jesd204_phy_adapter_xs_180 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg new file mode 100644 index 0000000000..703a6aa2e0 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_jesd204_phy_adapter_xs_180 +hdl_library_clause_name = altera_jesd204_phy_adapter_xs_180 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl new file mode 100644 index 0000000000..f2de81ed20 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl @@ -0,0 +1,50 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_jesd204_rx_180 ./work/ + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim" + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_base.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_csr.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_ctl.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_descrambler.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_char_val.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_cs.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_data_store.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_ecc_dec.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_ecc_enc.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_ecc_fifo.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_frame_align.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_fs_char_replace.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_lane_align.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_wo_ecc_fifo.v" -work altera_jesd204_rx_180 + vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_regmap.v" -work altera_jesd204_rx_180 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg new file mode 100644 index 0000000000..c780bea065 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_jesd204_rx_180 +hdl_library_clause_name = altera_jesd204_rx_180 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180 ip_arria10_e1sg_altera_jesd204_rx_mlpcs_180 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl new file mode 100644 index 0000000000..8f3b05caff --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl @@ -0,0 +1,43 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_jesd204_rx_mlpcs_180 ./work/ + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim" + + vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_8b10b_dec.v" -work altera_jesd204_rx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_rx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_pcfifo.v" -work altera_jesd204_rx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_rx_mlpcs.v" -work altera_jesd204_rx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_rx_pcs.v" -work altera_jesd204_rx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_wa.v" -work altera_jesd204_rx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_wys_lut.v" -work altera_jesd204_rx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_xn_8b10b_dec.v" -work altera_jesd204_rx_mlpcs_180 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg new file mode 100644 index 0000000000..14bea68453 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_jesd204_rx_mlpcs_180 +hdl_library_clause_name = altera_jesd204_rx_mlpcs_180 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl new file mode 100644 index 0000000000..6886f04bce --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl @@ -0,0 +1,45 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_jesd204_tx_180 ./work/ + + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim" + + + vlog "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_base.v" -work altera_jesd204_tx_180 + vlog "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_csr.v" -work altera_jesd204_tx_180 + vlog "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_ctl.v" -work altera_jesd204_tx_180 + vlog "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_dll.v" -work altera_jesd204_tx_180 + vlog "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_regmap_opt.v" -work altera_jesd204_tx_180 + vlog "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_regmap.v" -work altera_jesd204_tx_180 + vlog "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_scrambler.v" -work altera_jesd204_tx_180 + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg new file mode 100644 index 0000000000..427108eab8 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_jesd204_tx_180 +hdl_library_clause_name = altera_jesd204_tx_180 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180 ip_arria10_e1sg_altera_jesd204_tx_mlpcs_180 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl new file mode 100644 index 0000000000..95fa227480 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl @@ -0,0 +1,42 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_jesd204_tx_mlpcs_180 ./work/ + + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim" + vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_8b10b_enc.v" -work altera_jesd204_tx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_tx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_pcfifo.v" -work altera_jesd204_tx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_tx_mlpcs.v" -work altera_jesd204_tx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_tx_pcs.v" -work altera_jesd204_tx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_wys_lut.v" -work altera_jesd204_tx_mlpcs_180 + vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_xn_8b10b_enc.v" -work altera_jesd204_tx_mlpcs_180 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg new file mode 100644 index 0000000000..cf8d72f457 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_jesd204_tx_mlpcs_180 +hdl_library_clause_name = altera_jesd204_tx_mlpcs_180 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl new file mode 100644 index 0000000000..1353d920fc --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl @@ -0,0 +1,44 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + +vmap altera_reset_sequencer_180 ./work/ +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim" + + + vlog "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_controller.v" -work altera_reset_sequencer_180 + vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_av_csr.sv" -work altera_reset_sequencer_180 + vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_deglitch_main.sv" -work altera_reset_sequencer_180 + vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_deglitch.sv" -work altera_reset_sequencer_180 + vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_dlycntr.sv" -work altera_reset_sequencer_180 + vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_main.sv" -work altera_reset_sequencer_180 + vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_seq.sv" -work altera_reset_sequencer_180 + vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer.sv" -work altera_reset_sequencer_180 + vlog "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_sequencer_180 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg new file mode 100644 index 0000000000..9efd339974 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_reset_sequencer_180 +hdl_library_clause_name = altera_reset_sequencer_180 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg index 3de92111d3..f65bebd263 100644 --- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg +++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg @@ -2,8 +2,7 @@ hdl_lib_name = ip_arria10_e1sg_jesd204b hdl_library_clause_name = ip_arria10_e1sg_jesd204b_lib hdl_lib_uses_synth = technology tech_pll common dp -# hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180 -hdl_lib_uses_sim = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180 ip_arria10_e1sg_altera_iopll_180 ip_arria10_e1sg_altera_reset_sequencer_180 hdl_lib_technology = ip_arria10_e1sg synth_files = -- GitLab